JPS607265A - Image processor - Google Patents

Abstract

PURPOSE:To attain high speed processing by storing once an image data in a memory, reading the image data from this memory and outputting the image data while being expanded or shrinked so as to be suited to the resolution of each image output device. CONSTITUTION:Figure shows contents of a bit designating register 11, a P/S register 4 and an S/P register 6 at the expansion mode. The image data per unit mm. of a picture transferred from a memory 2 to the P/S register 4 via a data bus 5 consists of a bit train ''11110000'' and on the other hand, a bit train ''01000000'' is written in the bit designating register 11 via the data bus 5. The 2nd bit ''1'' from the left of the bit train in the P/S register 4 is written repetitively twice in the S/P register 6, resulting that the content of the S/P register 6 becomes ''111110000''. Thus, the number of bits is increased from 8-bit into 9-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device, particularly an image processing device connected to a plurality of image output devices having different resolutions, which outputs image data adapted to the specific resolution of the image output device. The present invention relates to an image processing device capable of processing images.

Multiple image output devices with different degrees of fibrillation 1 Examples include laser beam type printers (@ 18'9 A field; means that 9 dots can be displayed per 1 mrn) and impact type printers (resolution). 6 pieces/
-trL) or a display (3 resolutions/,,,), etc. is connected to the image processing device.

The same image data read by the image reader and processed by the image processing device is supplied to the plurality of image output devices having different resolutions.

If the resolution of the image reader is 8/mnt, and the image data per mm output from the image processing device is 00110000 (0 corresponds to white, ■ corresponds to black), this image When data is supplied to the plurality of image output devices, it is displayed at a resolution unique to each image output device, resulting in a dot display as shown in FIG. 211. As is clear, a printer with a resolution of 9 lines/mm will enlarge the image;
'rrLtn printer and resolution is 3 wood/mm (
7) The image is displayed in a reduced size on the display.

It is undesirable for the same image to be enlarged or reduced in size and displayed in front of image output devices with different resolutions. To avoid this, in conventional devices, each time image data is output to each image output device, the electrical signal from the image reader is sampled at a sampling period according to the resolution of each image output device. Either image data adapted to the device is obtained, or image data read at a fixed resolution is extracted and re-edited using a microprogram to extract only the necessary bits.

However, according to the former method, 1. For example, when an operator prints out an image read out on a display and edited on a printer, the image is read again with an image reader and the electrical signal is sampled at a sampling frequency corresponding to the printer's resolution of 19 degrees. There must be. This has the disadvantage that processing time becomes longer.

Furthermore, according to the latter method, the microprogram operates on a byte boundary, which is not very suitable for focus processing, and has the disadvantage that bit processing takes a long time.

SUMMARY OF THE INVENTION An object of the present invention is to improve the drawbacks of the conventional apparatus by temporarily storing image data read at an arbitrary resolution by an image reader in a memory, and reading the image data from the memory.

An object of the present invention is to provide an image processing device that enables high-speed processing by enlarging or reducing image data and outputting it so as to adapt to the resolution of each image output device.

In an image processing device connected to a plurality of image output devices having different resolutions, the present invention has a memory for storing image data read at an arbitrary resolution by an image reader, and a parallel system for storing image data transferred from this memory. a parallel-to-serial conversion register that performs serial conversion; a serial-to-halal conversion register that converts image data transferred from the parallel-to-serial conversion register to serial-to-parallel and outputs it to the image output device; A clock generation circuit that supplies clocks to each of the serial-to-parallel conversion registers, and a control circuit that controls the click generation circuit; control to stop the operation of one of the conversion registers for a predetermined period of time, thereby increasing or decreasing the number of bits of image data when transferring image data from the parallel-to-serial conversion register to the serial-to-parallel conversion register; The present invention is characterized in that image data adapted to the resolution of each image output device is obtained.

According to the present invention, if bits are removed at regular intervals from a bit string constituting image data read at a high resolution, image data adapted to a lower resolution can be obtained, and if the same bits are continuously output, the image data can be obtained at a higher resolution. This was done based on the recognition that adapted image data can be obtained.

The present invention will be explained below based on one drawing. %12 figure is 1
1 is a block diagram showing the basic configuration of an image processing device 1 of the present invention. FIG. In the figure, 2 is an arbitrary degree of disassembly, for example, 8 lines/mm.
4 is a parallel-to-serial conversion register that converts parallel image data transferred from the memory 2 via the data bus 5 into serial image data. (hereinafter referred to as P/S register), 6 is a serial-parallel conversion register (hereinafter referred to as P/S register) that converts serial image data transferred from this P/S register back into parallel image data.

7 is a clock generation circuit that generates clocks to these conversion registers, and 8 is a clock generation circuit that controls this clock generation circuit to control the P/S register 4 and S/P register.
This is a control circuit that adjusts the clock to the P register 6.

This control circuit 8 includes a mode register 9 that specifies enlargement or reduction of image data, and a magnification register 1 that specifies how many times the same bit is to be output repeatedly in the enlargement mode.
0, and a bit designation register 11 that specifies which bits are to be output repeatedly or which bits are to be removed in both enlargement mode and reduction mode. In each of these registers 9, 10 and 11.

Predetermined data is supplied via a data bus 5 from a central processing unit (not shown).

The image processing device 1 has the above configuration.

Via a data bus 5, a plurality of image output devices 1 with different resolutions, such as a laser beam type printer 12, are connected to each other.
(H resolution 9 lines/rn-), impact type printer 13 (resolution 6 lines/, ) and display 1
4 (resolution 3/,) etc. are connected.

Figure N-3 (a), Figure 3 (bl) and Figure 3 (1) are
FIG. 3 is a diagram for explaining the basic principle of such an image processing device d. Tree diagram 3 (.j indicates the contents of the bit designation register 11.P/S register 4 and S/P register 6 in the expansion mode.

From memory 2 to P/S register 4 via data bus 5
The image data per image unit mm transferred to is composed of a bit string "11110000", and on the other hand,
“0” is sent to the bit specification register 11 via the data bus 5.
1000000" is written.

P corresponding to bit “1” in bit specification register 11
/S The bit in register 4 is output repeatedly the number of times specified by 1 multiplication register 10.

Transferred to S/P register 6. In this case, it is assumed that the 1 magnification register instructs to output the same bit twice. FIG. 3(a) shows bit designation register 11. The correspondence between the bits of the P/S register 4 and the S/P register 6 is indicated by broken line arrows. As is clear from the figure.

The second bit "1" from the left of the bit string in the P/S register 4 is written twice to the S/P register 6,
As a result, the content of S/P register 6 is 111110000
” Therefore, the number of bits has been increased from 8 bits to 9 bits. By repeating the above operation for each byte.

The image data can be enlarged, and the enlarged image data is transmitted through the data bus 5 to a resolution of 9 mm.
The image is supplied to the printer 12, and the same size image is printed out. FIG. 3 (cl) shows this enlarged dot display per mm.

Next, the basic principle of the image processing device in the reduction mode will be explained based on Figure 3 (bl).

hif) Designated cash register y, evening 11 contents 11. ”1
0001000".The focus in the P/S register 4 corresponding to the "1" bit of this bit string,
As is clear from the figure, bit IIIJI and bit “0”
Toga.

S/P is prohibited from being transferred to S/P register 6.
The bit string obtained in register 6 is at regular intervals (4 bits)
The bit is removed in , resulting in "111000".

Therefore, the number of bits is reduced from 8 bits to 6 bits. Image data can be reduced by repeating the above operations for each byte. This reduced image data is passed through the data bus 5 and has a resolution of 6 lines/mm.
The image is supplied to the printer 13, and the same size image is printed out. FIG. 3(6) shows this reduced dot display per unit mm.

The number of bits in P/S register 4 and S/P register 6 can be increased or decreased by operating these registers as follows. That is, when the P/S register 4 and the S/P register 6 are operated by clocks of the same phase, in the expansion mode, the operation of the P/S register 4 is stopped for a predetermined period, and the S/P register 6 is stopped during this period. If it continues to work, S/
The same bit is read into the P register 6 a predetermined number of times, and the number of bits can be increased. On the other hand, in the reduction mode, if the operation of the S/P register 6 is stopped for a predetermined period and the P/S register 4 is operated during this period, when the operation of the S/P register 6 is stopped, the P/S register 4 is The bits sent from the S/P register 6 are not read, and therefore the number of bits obtained in the S/P register 6 decreases.

The operation of the P/S, register 4, or S/P register 6 can be stopped by adjusting the clocks supplied to these registers.

FIG. 4 is a block diagram of the image processing apparatus showing more specifically the clock generation circuit 7 that generates clocks to the P/S register 4 and the S/P register 6. In the figure, the same elements as in FIG. 2 are denoted by the same numbers. The clock generation circuit 7 includes AND circuits 15, 16, 17, 1
8.19.20 and OR circuits 21 and 22, and the clock CKI is supplied from the OR circuit 21 and the OR circuit 22.

A clock CK2 is generated.

The operation of the image processing device will be explained in more detail based on FIG.

The mode register 9 is composed of a flip-flop, and generates a bit "1" in the enlargement mode and a bit "0" in the reduction mode. The magnification register 10 is composed of a counter, and the bit designation register 11 is composed of a parallel-serial conversion register. These mode registers 91, magnification registers 10. A load signal is supplied to the bit designation register 11 from an address decoder (not shown), and 1. Data is loaded via the data bus 5 when a load signal is supplied. A clock CK is supplied to the magnification register 10 and the clock generation circuit 7. "A' 51:
<l tαj and the 51st r, l tl, l in the enlargement mode and in the reduction mode. clock CK,
Output signal S of bit specification register 11, clock CK1
and CN3 waveforms are shown.

In the expansion mode, the clock CK is connected to the AND circuit 18 and (
It is outputted through the JR circuit 21 and becomes the clock CK1. On the other hand, the AND circuit 19 receives the output signal 5 of the bit designation register 11 (see FIG. AND circuit 1
The output of 9 is output through OI times M22 and clock CK.
It becomes 2.

These clocks CKI and CN3 are supplied to S/P register 6 and P/S register 4, respectively. P/
The S register 4 and the S/P register 6 perform parallel-to-serial conversion and serial-to-parallel conversion, respectively, based on these clocks. 'At5 As is clear from the diagram (α), while the two consecutive clock pulses p1 and P2 of the clock CKI occur, the clock C
One clock pulse P3 is generated in K2. Therefore, while the S/P register 6 is operating due to the clock pulse p2, the P/S register 4 stops operating. Therefore, the S/P register 6 retakes the same bit from the P/S register 4, and as a result, the S/P register 6
The number of bits available in the P register 6 increases.

In the reduction mode, the clock CK is connected to the AND circuit 2° and O
It passes through the R circuit 22 and becomes the clock CK2.

On the other hand, the AND circuit 17 receives the output signal S('')V5 (see 61) of the bit designation register 11 which has passed through the AND circuit 15, the output signal of the 9x magnification register, and the mode register 9.
The output signal of the AND circuit 17 is outputted via the OR circuit 21, and the clock CI is supplied.
Becomes KI. As is clear from the M2S diagram (bl), one clock pulse P6 of clock CKI occurs while two consecutive clock pulses P4 and P5 of clock CK2 occur, and two consecutive clock pulses P6 of clock CK2 occur. During the generation of clock pulses P7 and P8, one clock pulse P9 is generated on the clock CKI.

Therefore, by clock pulses P5 and P8, P
/When S register 4 is operating.

The S/P register 6 has stopped operating. At this time, S
/P register 6 does not take in the bits generated by P/S register 4, and as a result the number of bits available in S/P register 6 is reduced.

The image data enlarged or reduced as described above is read when the read signal is supplied from the address decoder to the S/P register 6, and is supplied to the image output device having the corresponding resolution via the data bus 5. can do.

As is clear from the above, according to the image processing device of the present invention, image data read at an arbitrary resolution is temporarily stored in the memory, and the image data retrieved from this memory is adapted to the resolution of the image output device. Since the image can be enlarged or reduced in a /·- code manner, high-speed processing is possible. Therefore, if you check the image data on the display and then print it out to a printer whose resolution is different from that of the display, the image data can be read directly from memory and enlarged or reduced, speeding up the operation during this time. It becomes possible to do so.

[Brief explanation of the drawing]

FIG. 11 is a diagram showing dot displays of various image output devices, FIG. 2 is a block diagram showing the basic configuration of the image processing device of the present invention, and FIG. 3 (σ) to FIG. 3 iC1 are image processing of the present invention. FIG. 4 is a block diagram showing a more specific configuration of the image processing device of the present invention, and FIG. 5 (α) and FIG. 5 (6) are diagrams for explaining the operation. FIG. In the figure, 1 is an image processing device, 2 is a memory, 3 is an image reader, 4 is a P/S register, 5 is a data bus, 6 is an S/P register, 7 is a clock generation circuit, 8 is a control circuit, and 9 is a 10 is a mode register, 10 is a magnification register, and 11 is a bit designation register. Figure 4 CK Figure 5 (0-) K

Claims (1)

[Claims] (1) Solution: In an image processing device connected to multiple image output devices with different image resolutions, there is a memory that stores image data read at a desired resolution by an image reader, and a memory that stores image data transferred from this memory. A parallel-to-serial conversion register that performs parallel-to-serial conversion; a serial-to-parallel conversion register to perform serial-to-parallel conversion of image data transferred from the parallel-to-serial conversion register and output to the image output device; A clock generation circuit that supplies clocks to the register and the serial-to-parallel conversion register, respectively, and a control circuit that controls the clock generation circuit.
By controlling the clocks supplied to the serial conversion register and the serial-to-parallel conversion register by the control circuit and stopping the operation of one of the conversion registers for a predetermined period, image data is converted from the parallel-to-serial conversion register to the serial-to-parallel conversion register. An image processing device characterized in that the number of bits of image data is increased or decreased during transfer to a parallel conversion register to obtain image data adapted to the resolution of each of the image output devices.