JPS59205665A - Picture processor - Google Patents

Abstract

PURPOSE:To provide plural functions of enlargement/reduction and the picture element density conversion of picture data to a single device and to process pictures with low cost, by using a master clock generating circuit, a thinning clock pulse generating circuit, a logical gate, etc. CONSTITUTION:The picture data Di to be processed is stored to an input buffer 8 from a CPU1 through a bus 6. The read or write control is given to the data Di by the master clock pulse CKm and the clock inhibition signal CKi supplied from a master clock generating circuit 9 and a thinning clock generating circuit 10 respectively. The signal CKi has a cycle obtained by thinning a specific number of pulses from the pulse CKm in accordance with the magnification ratio data Dm showing the ratios of enlargement, reduction and picture element density respectively. The storage data sent from the buffer 8 is transferred every bit to an output buffer register 11 and then written. In this case, the enlargement, reduction and picture element density conversion of the picture data are carried out by a counter, logical gates 12-14, etc. In other words, a single device can contain various functions. Furthermore the pictures can be processed at a high speed and with low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device such as an image editing device that performs reduction, enlargement, and conversion of pixel density of input image data converted into a binary dot matrix.

[Prior art]

An image editing device is a device that reduces or enlarges input image data, but in the past, when this image editing device was combined with a CRTf display to create work stage 3, a pixel density conversion device was required in addition to the image editing device. There was (rod 1
(illustration). In other words, although recent image editing devices have become capable of processing higher-density data due to the demand for improved image quality and the increased capacity of semiconductor memory, CIRT displays...17 degrees are 4 dots/my or 6 Dot/φm
The degree is limited to 7J) and it's $1. As shown in Figure 1, the workstation is connected to a common bus 6 (2) with a central processing unit (CPU) 1, an image memory 2, an enlargement/reduction device 3, and a dense IL conversion method for CRT. Technologies related to the image processing performed by the CRT display 5 include a density conversion device using logical sum (see Japanese Patent Application Laid-open No. 115124/1983), and an enlargement/reduction device using thinning and duplication ( % opening/closing 57-570
(See No. 80). However, even if these are simply combined, it is difficult to create a device 2 that can satisfy the three functions of reduction, expansion, and density conversion with a single device, and in the end, the configuration shown in Figure 1 is not possible. I can't get it. This is because when the conversion ratio is large, such as converting from 12 dots/tomo to 4 dots/tomo, the method of thinning out the dots has the disadvantage of reducing image quality (e.g., disappearance of fine lines). This is because an enlargement/reduction device for image editing cannot be simply used for density conversion for CRT.

As mentioned above, in the past, each individual device was forced to be used as shown in Figure 1, and a single (-
It was impossible to realize the above three functions at low cost with this device. Moreover, all of the above-mentioned enlargement/reduction devices require high-speed processing and are therefore expensive.

〔the purpose〕

Therefore, the present invention provides an image processing device which has the functions of enlarging/reducing image data and changing pixel density (capturing functions) and can be realized at low cost.
Ru.

〔composition〕

Hereinafter, the present invention will be explained based on the illustrated embodiment. The same parts shown in Fig. 2 and in Fig. 1 are given the same numbers. In Fig. 2 of the whistle, 7 is related to the present invention and shows enlargement, reduction, and density transformation. A close-up view of this device 7 is shown in Figure 3.

In Hani 3, the basic n-y-sei is the following, ichi-ri. The image data Di to be processed is sent from the CPU to the ml register (hereinafter referred to as input buffer register 4) through path 6.
is stored in The stored data is generated by the first clock pulse (from the first clock pulse generation means (hereinafter referred to as a master clock generation circuit) 9 and from the first clock pulse generation means (hereinafter referred to as a decimated clock pulse generation circuit) IO.
Hereinafter, reading or writing is controlled by a master clock pulse (hereinafter referred to as a master clock pulse) CKmk and a second clock pulse (hereinafter referred to as a clock inhibit signal) CKi. The clock inhibit signal CKi has a period thinned out by a specific number of pulses of the master clock pulse CKm according to the magnification data Dm indicating the ratio of enlargement/reduction/pixel density. The stored data from the input buffer register 8 is transferred one pit at a time to the Asahi 2 register (hereinafter referred to as output buffer register) 11 and written therein. When writing to this output buffer register 11,
Enlargement/reduction/pixel density conversion is performed by counters and logic gates described later.

Next, the detailed configuration and its operation will be explained.

When performing reduction/reduction, 1 edit “input E” of OR gate 12
dt logic ``''1'', 1 expansion of NAND gate 13''
Input E z p 1. 0", 1 reduction "input Rd port 11'' of NAND gate 14. f, the output of the OR gate 12 becomes N1", and the CL of the D latch circuit 15
Since the R input becomes N1", the Q output of the D latch circuit 15 always becomes "0". Therefore, B of OR Age-16
The input is always ``O'', and the data stored in the input buffer 8 is directly transferred to the output buffer 11 and stored there.In this case, the output of the NAND gate 13 is ``1'', so...
The output of the AND gate 17 is the same as the mask clock CKm. Further, since the output of the NAND gate 14 becomes the clock inhibition signal CKi, the output of the AND gate 18 is inputted to the output buffer address counter 19 as a clock thinned out from the master clock CKm according to the reduction magnification data Dm. This clock causes the input buffer register 8 to output one bit at a time. Among the single-plane image data, the data when the clock inhibit signal CKi is output is not input to the output buffer register 11; [The current image data will be thinned out. In this way, one line of image data stored in the input buffer register 8 is output, and the output buffer register 11 obtains one line of reduced data in which the image data is appropriately thinned out according to the reduction magnification data Dm. It will be destroyed.

If the expansion is not performed, the NAND gate) 13's 9 expansion "input EXTl'a"1'',
Let 1 bar be "input Rdt Yゝ0". 1- Then,
The output of the AND gate 17 is given to the input buffer address register 20 as the clock inhibit signal CKi, and
The output of D gate [8 is given to the output buffer address register 19 as the master clock CKm. Then, at the time when the clock inhibit signal is output, the same data as the image data one bit before is input to the output buffer register 11 in duplicate. So ·
As a result, the output buffer register 11 has an expanded 1
Data for each line can be obtained. Note that the thinning ratio of the clock prohibition signal CKm follows the enlargement magnification data Dm.

Pixel Density Conversion Next, cases in which pixel density changes for CRT are performed will be explained f and b. -For example, 12 dots/mmY6 dots/
Describe the case of converting to mH. To start with the conclusion, in this case, the original image data should be adjacent to each other in 2x2 vertically and horizontally.
Logical sum of dots? All you have to do is take it and make one end of the image.

First, 1/1 line/1 line request data is transferred by the CPU via the bus 6 and stored in the input buffer 8. Then OR gate 1202 edit “input Edtn O
“, 1 expansion of NAND gate 13” input Exp? XXO
“, 1-reduced” input Rdt of NAND gate 14?ゝ1
“Binding, and in the case of the first line, AND gate 21
n' New input "input N/'Yゝゝ1". −
1: In this case, the clock inhibit signal CKi is the master clock CKm? It is a signal whose frequency has been divided by 1/2, and this fact must be specified from the magnification data DmK (f7:).

When the first dot is to be output from the input buffer 8, the clock inhibit signal CKi is 10", and the AND gate 8 outputs the same clock pulse f as the master clock CKm, so the output buffer 11 is output to the first dot. The master clock signal (CKmY) is output to the D input of the KD latch circuit 15 along with the data input f.However, since the CLR input of the D latch circuit 15 is "1", the Q output is %%.
Therefore, the output (output) of the OR gate 16 (the input to the buffer 11) is also equal to the data of the first dot.

Clock prohibited in the next master clock pulse CKm)
:, signal car 1'', the address of the output buffer 11 is not updated. Also, the address of the output buffer 11 is not updated.
Since the LR input is NO'', the data of the first dot is output to the Q output.Therefore, the output of the OR gate 16 is the logical sum of the first dot Hani and the second dot Asahi. This is stored in the buffer register 11. By repeating the above operations, the output buffer register 11 will eventually be able to obtain one line of data with a logical sum for every two dots.

In the case of the second line, by setting one new line "input N/Y'o" of the AND gate 21, the data count "-Il1st
The dots are output to the Q output of the D latch circuit 15. For this reason, for every 2 dots on the 2nd line, ζ9 and 1
The logical sum of the two dots on the line is sequentially stored in the output buffer, and the second line ends at 13R.'f
Roto 12 dots/Moe to 6 dots/? It is possible to obtain the LIILK-converted first line image data. By repeating this process two lines at a time, the density change of the entire image is completed.

In the explanation above 6%, processing in the sub-scanning direction (page direction), for example, in the case of enlargement processing, the judgment of processing such as outputting the same 94772 times does not need to be particularly fast, so it is controlled by CPUIK. Be it.

〔effect〕

As described above, according to the present invention, there is no need to independently combine the enlarging/reducing device and the density converting device as in the prior art.
Can you achieve the above three functions with a single device configuration and without sacrificing high speed? It is possible to provide a capable image processing device.

[Brief explanation of the drawing]

Figure 1 is an example of a workstation that combines a conventional enlargement/reduction device and a CRT density conversion device. Fig. 2 is a schematic block diagram of an image processing apparatus according to the present invention. Figure 3 is a block diagram illustrating an embodiment of the image processing apparatus according to the present invention.

Claims (1)

[Claims] An image processing device that enlarges and reduces input image data converted into a binary dot matrix, and converts pixel density, and has a period of −9? A first clock pulse generation means having a first clock pulse generation means, and a period obtained by subtracting the specified number of pulses by 1 from the first clock pulse according to the ratio of enlargement, reduction, and pixel density. Clock pulse generation f filter rod 2 clock pulse means of the dero claw 2 and data for one line of processing oil of the input image data are stored,
The stored data is read out bit by bit by the clock pulse, and the data for one line after processing the input image data is read out bit by bit by the clock pulse.
and a second register in which each bit is read and written in response to a clock pulse;
and a logical sum means for outputting a logical sum signal Y of each output of the registers, and the stored data 4 is sequentially read from the first register by the first clock pulse, and is input to the register of Asahi 2 by the second clock pulse. Next, the input image data is reduced by inputting one item, the stored data is sequentially read from the first register by the second clock pulse, and the input image data is sequentially written to the register of the brush 2 by the first clock pulse. image data? enlarging and writing the logical sum of the data sequentially read from the first register by the first clock pulse and the data sequentially read from the second register by the second clock pulse into the second register; An image processing apparatus characterized in that pixel density conversion is performed by calculating the logical sum of a number of pixels around a pixel to be processed.