JPS61140270A - Picture element density converter - Google Patents

Abstract

PURPOSE:To obtain the best magnified/reduced picture quality with optional magnification by selecting a magnification/reducing circuit having an optimum algorithm in response to the magnifying/reduced rate so as to apply conversion processing of picture element density. CONSTITUTION:A selection circuit 61 applies a picture element data for 4 picture elements' share to one of plural magnification/reduction circuits 51-1-50-N of the magnification/reduction arithmetic part 50 according to a command of a selection signal SEL outputted from an algorithm setting part 40. Then one of the circuit 51-1-50-N executes the density operation of a magnified/ reduced picture based on a predetermined algorithm and the result is stored in a destination side shift register 53 via an OR gate 58. In this case, the picture element data of the magnified/reduced image is stored sequentially in a shift register 53 by a destination side timing pulse TPD outputted from a timing generating circuit 30. Through the operation above, the picture element data of the original image is written in an image memory 2 via the shift register 53.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a pixel density conversion device for obtaining an enlarged/reduced image of an image in which each pixel is represented by binary data of 109 and 11#. be.

[Prior Art] Conventionally, as a pixel density conversion method for converting the pixel density of a binary image to obtain an enlarged or reduced image, the SPC method,
The logical sum method, the projection method, the 9-division method, etc. are known.

The SPC method is a method that calculates the coordinates of each pixel after conversion (converted pixel) and then uses the density of the original pixel closest to each converted pixel as the density of each converted pixel. This method uses the logical sum of the densities of four neighboring pixels as the density of the converted pixel. The projection method is a method in which the average density of original pixels projected onto a converted pixel is calculated, and the result is subjected to equivalency processing to obtain the density of the converted pixel. Furthermore, the 9 division method is 4
In this method, a rectangular area having vertices at each position of the original pixel is divided into nine partial areas, and the density of the i-converted pixel is determined by a logical operation formula determined according to the partial area containing the converted pixel.

Conventionally, image processing apparatuses that handle images use one of these pixel density conversion methods to obtain enlarged or reduced images.

[Problems to be Solved by the Invention] However, each of these pixel density conversion methods has advantages and disadvantages. For example, in the SPC method, the processing is simple, but the strokes become thinner during reduction and the connectivity of the strokes is lost, so that so-called 1 omission 9 tends to occur. On the other hand, in the logical sum method, the strokes tend to become thicker, and when the strokes are reduced, the strokes are connected, which tends to cause the phenomenon of so-called one collapse 9.

Also, with the 9-division method, there is a limit to the magnification/reduction ratio (2/3~
2 times).

Therefore, if the conversion function is limited to one of these pixel density conversion methods, a converted image with good image quality can only be extracted by either enlargement or reduction, or by a magnification within a predetermined range. There was a problem.

Means and operation for solving problem 1] The present invention provides a plurality of enlargement/reduction circuits with different enlargement/reduction algorithms, and selects the optimum enlargement/reduction circuit according to the set enlargement/reduction magnification. By calculating the density of the enlarged/reduced pixels, the best enlarged/reduced image can be obtained at any magnification.

[Embodiment] FIG. 1 is an overall block diagram showing an embodiment of the present invention, and is a pixel density conversion device according to the present invention! ii is the system control circuit 10. Constant setting section 20. Enlargement/reduction timing forming circuit 30. Algorithm setting section 40. The original pixel data to be enlarged/reduced is stored in an external image memory 2, and the converted pixel data after enlargement/reduction is stored in this image memory 2 again. be remembered.

In this configuration, the system control circuit 10
Controls the overall operation and controls access to the image memory 2. On the other hand, the constant setting section 20 is constituted by a storage circuit etc. that stores address information and enlargement/reduction magnification in the image memory 2 of the original image data as constants, and the stored constants are stored in the system control circuit 10. The signal is supplied to the enlargement/reduction timing forming circuit 30 and the enlargement/reduction calculation section 50. Note that the constants such as the enlargement/reduction magnification stored in the constant setting section 20 are given from the external processor 3.

The enlargement/reduction timing forming circuit 30 divides the clock pulse based on the data of the enlargement/reduction magnification given from the constant setting section 20, forms a timing pulse corresponding to the set magnification, and outputs it. This timing pulse is supplied to the enlargement/reduction calculation section 50.

The algorithm setting unit 40 stores the optimal pixel density conversion algorithm for arbitrary enlargement magnification and reduction magnification,
When data of an arbitrary enlargement magnification or reduction magnification is given from the processor 3, a selection signal of a pixel density conversion algorithm most suitable for the data is outputted and supplied to the selection section 60. The enlargement/reduction calculation section 5o is composed of a plurality of enlargement/reduction circuits each using a different pixel density conversion algorithm such as the SPC method or the OR method. Original pixel data is given. As a result, pixel density conversion processing is performed by an enlargement/reduction circuit having an optimal algorithm for the set enlargement or reduction magnification. This pixel density conversion process is performed in synchronization with a timing pulse generated by the timing forming circuit 30.

Figure 2 shows the 30° expansion/reduction timing formation circuit.
2 is a block diagram showing the detailed configuration of a reduction calculation section 50 and a U selection section 60, in which two scanning lines of original pixel data PD are read out from the image memory 2. FIG.

PD2 is a source-side timing pulse TP output from the timing forming circuit 30 after being set in parallel to the source-side shift registers 51 and 52 of the enlargement/reduction calculation unit 50.
The data is converted into serial data by being shifted one bit at a time in synchronization with S. These two scanning lines worth of serial data are stored in registers 54 and 55 using timing pulses T.
After being delayed by one period of PS, it is input to the selection circuit 61 of the selection section 6 together with the serial data newly output from the shift registers 51 and 52. In other words, selection circuit 6
1 includes pixel data for two pixels output from the shift registers 51 and 52 at the time of generation of the current timing pulse TPS, and pixel data for two pixels output from the shift registers 51 and 52 at the time of generation of the immediately preceding timing pulse TPS. Pixel data for a total of four pixels is extracted and input as pixel data to be converted. Then, the selection circuit 61
The pixel data for these four pixels is sent to the algorithm setting section 40.
A plurality of enlargement/reduction circuits 51-1 to 50- of the enlargement/reduction calculation section 50 according to the instruction of the selection signal SEL output from the
Supplied to one of N.

Then, one of the enlarging/reducing circuits 51-1 to 50-N that receives the pixel data for four pixels executes the density calculation of the enlarged/reduced image based on a predetermined algorithm, and the result is sent to an OR gate. 58 and stored in the destination side shift register 53. In this case, enlarge
The pixel data of the reduced image is sequentially stored in the shift register 53 by the destination timing pulse TPO output from the timing forming circuit 30.

Such concentration calculation is performed every time the timing pulse TPS is generated, and during this time the source side dot counter 5
6 counts the amount of shift of pixel data in shift registers 51 and 52 by counting timing pulses TPS. When the count value reaches a value equal to the storage capacity of the shift registers 51 and 52, a read request RRQ is sent to the system control circuit 10 in order to set the next new original image data in the shift registers 51 and 52. Output.

Similarly, the test nation side dot counter 57 receives the timing pulse T P r'l 1 + −+ L j
By this, the shift amount of pixel data in the shift register 53 is counted. When the count value becomes equal to the storage position of the shift register 53, a write request WRQ is sent to the system control circuit 10 to store the pixel data of the enlarged/reduced image stored in the shift register 53 in the image memory 2. supply to

Through these operations, a certain amount of pixel data of the original image is
The image is enlarged or reduced in units according to the enlargement/reduction magnification and written into the image memory 2 via the shift register 53.

On the other hand, in the timing forming circuit 30, data χ of the enlargement magnification or reduction magnification given from the constant setting section 20 is sequentially accumulated in an accumulating circuit 33 consisting of a register 31 and an adder 32 every time a clock pulse ck is generated. . As a result, the adder 32 outputs a carry signal CRY having a period corresponding to the enlargement magnification or reduction magnification. This carry signal CRY is synchronized with the clock pulse ck at the AND gate 34, and then synchronized with the AND gate 35°36.
is input.

A control signal CT of 109 when enlarging and 1# when reducing is input to AND gates 35 and 36, and the output signals thereof are input to OR gates 39 and 40, respectively.

The OR gate 39 receives the clock pulse ck and the output signal of the AND gate 37 which receives the control signal CT, and the OR gate 40 receives the clock pulse ck
and the output signal of an AND gate 38 which receives the control signal CT as input. In this case, and gate 35
．． 38 receives the control signal CT in negative logic.

The output signals of these Ao gates 39 and 40 are outputted as a source side timing pulse TPS and a guest nation side timing pulse TPO.

Assuming that the numbers ro and 7J are set as the enlargement or reduction magnification on the gold plate, and the adder 32 outputs the carry signal CRY with the added value of rl and OJ, the clock pulse ck is generated 10 times. At this stage, the carry signal CRY is generated a total of seven times as shown in Table 1 below.

Table 1 Therefore, when reducing the carry signal CRY, the test nation side timing pulse T is passed through the AND gate 36.
By simultaneously outputting the clock pulse ck as the source timing pulse TPS via the AND gate 37, the clock pulse ck calculated by one of the enlargement/reduction circuits 50-1 to 50-N is input to the shift register 53. Of the pixel data, only the pixel data at the time when the timing pulse TPO occurs is stored. That is, the shift register 53 stores pixel data of the number of pixels obtained by thinning out the pixel data calculated by one of the enlargement/reduction circuits 50-1 to 50-N by 30%.

Conversely, when enlarging, the carry signal CRY is sent to the AND gate 35.
By outputting it as a source side timing pulse TPS through the shift register 53, pixel data having a 30% overlapping portion is stored in the shift register 53.

Thereby, pixel data enlarged or reduced at an arbitrary magnification can be obtained from the shift register 53.

Note that the output data of the register 31 is input to the enlargement/reduction circuits 50-1 to 50-N in addition to the magnification data χ and the control signal CT indicating whether the image is enlarged or reduced. The reason why the output data of the register 31 is input to the enlargement/reduction circuits 50-1 to 50-N is to determine which area of the original pixel the converted pixel belongs to.

By the way, the above explanation is for obtaining converted pixel data in the horizontal scanning direction, but the process in the vertical direction is exactly the same depending on which horizontal scanning line the pixel data input to the shift registers 51 and 52 is to be used for. Converted pixel data in the vertical scanning direction can be obtained. Specifically, the addresses of the image memory 2 may be sequentially advanced in the direction corresponding to the vertical scanning direction while monitoring the generation status of the carry signal CRY.

Note that the resolution during expansion/reduction is "1/2°" when the number of bits of the adder 32 is n pits, and when n=8, expansion or reduction can be performed in approximately 0.4% increments.

In addition, for multi-gradation image data or color image data, a source-side shift register and a destination-side shift register are provided for each gradation or color.
Enlargement or reduction can be performed in exactly the same way by using the enlargement/reduction circuit in a time-sharing manner.

[Effects of the Invention] As is clear from the above explanation, in the present invention, an enlargement/reduction circuit having an optimal algorithm is selected according to the enlargement/reduction magnification and pixel density conversion processing is performed. The effect is that the best enlargement/reduction image quality can be obtained at the magnification.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram showing the detailed configuration of the main parts in FIG. 1. 1... Pixel density conversion device, 2... Image memory, 30
...Enlargement/reduction timing formation circuit, 50-1 to 50
-N... Enlarging/reducing circuit, 60... Selection circuit.

Claims (1)

[Claims] A target pixel extraction circuit that extracts pixel data of pixels to be enlarged/reduced, and multiple enlargement/reduction circuits that input pixel data from this target pixel extraction circuit and form enlarged/reduced pixel data using different enlargement/reduction algorithms. and a selection circuit that causes one of the plurality of enlargement/reduction circuits to form enlarged/reduced pixel data according to the set enlargement/reduction magnification, and a selection circuit set for the plurality of enlargement/reduction circuits. and a timing pulse forming circuit that supplies a timing pulse according to the enlargement/reduction magnification.
Enlargement and conversion by converting the pixel density of the original image from one of the reduction circuits.
A pixel density conversion device characterized by outputting pixel data of a reduced image.