JPH01264070A - Line density conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by applying picture conversion by the 1/9 division method and the picture conversion by the OR method by means of one and same circuit. CONSTITUTION:A conversion picture element address calculation circuit 1 calculates a conversion picture element address 7. A reference 4-picture element output circuit 2 outputs a reference 4-picture element 6 (I00, I01, I10, I11) in response to a conversion address 7. Then a multi-system picture element conversion picture element circuit 4 applies picture element conversion by the 1/9 division method or the OR method according to a command of a conversion system command circuit 3 in response to the reference 4-picture element 6 (I00, I01, I10, I11) and the conversion picture element address 7 and a conversion picture element output 5 is obtained. Thus, the scale of the circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image processing apparatus, and more particularly to a linear density conversion circuit in a facsimile machine.

2. Description of the Related Art Conventionally, in this type of linear density conversion circuit, the circuit that performs image conversion using the 9-division method and the circuit that performs image conversion using the OR method have been independent.

Problems to be Solved by the Invention In the conventional linear density conversion circuit described above, the circuit that performs image conversion using the 9-division method and the circuit that performs image conversion using the OR method are independent, so it is necessary to provide both conversion methods. However, the linear density conversion circuit had the disadvantage that the scale of the circuit increased accordingly.

The present invention has been made to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to provide a novel linear density conversion circuit that allows the circuit scale to be significantly reduced. There is a particular thing.

Means for Solving the Problems In order to achieve the above object, a linear density conversion circuit according to the present invention includes a conversion pixel address calculation circuit that outputs a conversion pixel address, and a conversion pixel address calculation circuit that receives the output of the conversion pixel address calculation circuit and converts the surrounding area. a reference 4-pixel output circuit that outputs the reference 4 pixels; a conversion method selection instruction circuit that sets a selection instruction of the 9-division method or the logical sum method in the main scanning direction and the sub-scanning direction; the converted pixel address calculation circuit; and the surrounding area. It is configured to include a reference 4-pixel output circuit and a multi-system pixel conversion circuit that receives the output of the conversion method selection instruction circuit and realizes pixel conversion using the 9-division method or the OR method.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a linear density conversion circuit according to the present invention.

In FIG. 1, ■ indicates a converted pixel address calculation circuit, 2 indicates a reference 4-pixel output circuit, 3 indicates a conversion method selection instruction circuit, 4 indicates a multi-system pixel conversion circuit, and 5 indicates a converted pixel output.

Referring to FIG. 1, a converted pixel address calculation circuit 1 outputs a converted pixel address 7. The converted pixel address 7 is input to the reference 4 pixel output circuit 2 and the multi-system pixel conversion circuit 4. The reference 4 pixel output circuit 2 outputs the reference 4 pixel 6 (I I
Output lO+ I (Il, I to, I ++). Reference 4 pixels 6 (I no, I H, It
o.

1++), the converted pixel address 7 and the output of the conversion method selection instruction circuit 3 are input to the multi-system pixel conversion circuit 4. The multi-system pixel conversion circuit 4 outputs a converted pixel output 5.

Next, the operation of this circuit will be explained. A converted pixel address calculation circuit 1 calculates a converted pixel address 7. Reference 4
The pixel output circuit 2 outputs the reference 4 pixels 6 according to the conversion address 7.
Outputs (Ion, Iot, I Ion 1 ++). The multi-system pixel conversion pixel circuit 4 converts the reference 4 pixels 6
(Ioo, Ios, ++o, 111) and the converted pixel address 7, pixel conversion is performed by the 9-division method or the logical sum method according to the designation of the conversion method instruction circuit 3, and a converted pixel output 5 is output.

FIG. 2 is a specific internal configuration diagram of the multi-system pixel conversion circuit 4 shown in FIG. 1.

Referring to FIG. 2, 8 is a parameter of the 9-division method, 9 is a logical sum instruction circuit, IO is a logical sum circuit, 11 is a converted pixel output section, and 12 is a logical sum reference 4 pixel Q. (++Qul,
Q IOr Q ++, 13 is the main scanning direction OR instruction,
14 indicates a logical sum instruction in the sub-scanning direction.

Reference 4 pixels 6 (Ioo, Ion, 110+
Its> is input to the OR circuit IO. OR circuit 1
0 is the logical OR reference 4 pixels 12 (Qoo, Qol, Q+
o, Q+t). The converted pixel address 7 is input to the OR instruction circuit 9 and the converted pixel output section 11. The output of the conversion method selection instruction circuit and the output of the parameter 8 of the 9-division method are input to the OR instruction circuit 9. OR instruction circuit 9
is the main scanning direction logical sum instruction 13 and the sub scanning direction logical sum instruction 1
Outputs 4. The main scanning direction OR instruction 13 and the sub-scanning direction OR instruction 14 are input to the OR circuit IO. OR reference 4 pixels 12 (Q oo, Q o+ , Q t
o.

Qz) is the converted pixel output section! input into l. The converted pixel output section 11 outputs a converted pixel output 5.

Next, the operation of this circuit will be explained. OR circuit 10
is the reference 4 pixels I00+ '01+ I IOr
I11 is input, and the main scanning direction OR instruction 13 is “
High''.

In this case, the logical sum of pixel values is calculated for each set of reference pixels in the main scanning direction, and the resulting value is used as the value for each set of pixels in the main scanning direction, and is output as the four reference pixels 12 for the logical sum. That is,
Q oo” Q o+ = I ooV I o+ .

Q + o = Q ++ = I to V I ■.

On the other hand, when the sub-scanning direction logical sum instruction 14 is "old gh", the logical sum circuit 10 calculates the logical sum of pixel values for each set of reference pixels in the sub-scanning direction, and uses that value in the sub-scanning direction. It is set as a value for each pixel set and output as a logical OR reference 4 pixels 12. That is, Q oo= Q +o= I ooV I
to.

Q o+= Q ++= I otV I tt. Also, the OR circuit 10 instructs the OR in the main scanning direction! 3 and the sub-scanning direction logical sum instruction 14 are both “High”, the values of the four reference pixels are logically summed, and the value is output as the logical sum reference four pixels 12. That is, Qoo=
Qo+=Q+o=Qs+= I ooV I otV
I toV r tt.

When the conversion method selection instruction circuit 3 specifies the 9-division method in the main scanning direction or the sub-scanning direction, the OR instruction circuit 9 selects 9 according to the conversion pixel atosis 7 and the 9-division method parameter 8. According to the logic of the division method, the main scanning direction OR instruction 13 or the sub-scanning direction OR instruction 14 is set to 'old gb'.On the other hand, the OR instruction circuit and the conversion method selection instruction circuit 3 indicate whether the main scanning direction or sub-scanning direction is If the logical sum method is specified in the direction, unconditionally set the main scanning direction logical sum instruction 13 or the sub scanning direction logical sum instruction 14 to "High". It is also possible to combine the logical sum method.The converted pixel output unit 11 outputs the converted pixel output 5 according to the converted pixel address 7 and the logical sum reference 4 pixels 12, but the converted pixel value is the same as that of the reference 4 pixels. If the pixel value is the same for each set in the main scanning direction or the sub-scanning direction, it is equal to the pixel value of the set of pixels on the side that includes the converted pixel address in the area surrounded by four pixels.Therefore, the multi-system pixel conversion circuit 4 In response to an instruction from the conversion method selection instruction circuit 3, the logical sum reference four pixels 12 converted according to the 9-division method or the logical sum method are input, and converted pixels according to the 9-division method or the logical sum method are output.

As described in detail of the invention, the linear density conversion circuit in the present invention includes:
By performing image conversion using the 9-division method and image conversion using the logical sum method in the same circuit, it is possible to achieve the effect that the circuit scale can be made smaller than the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a linear density conversion circuit according to the present invention, and FIG. 2 is a circuit diagram showing a specific internal configuration of the pixel conversion circuit 4 of FIG. 1. 1... Conversion pixel address calculation circuit, 2... Reference 4 pixel output circuit, 3... Conversion method selection instruction circuit, 4...
Multi-system pixel conversion circuit, 5... Conversion pixel output, 6...
Reference 4 pixels I (10, I O++ 11O+ I
11.7...Conversion pixel address, 8...Parameters of 9-division method, 9-mount theory ready instruction circuit, 10...OR circuit, ++...Conversion pixel output section, +2... Logical sum reference 4 pixels Qoo, Qo+, Q IIJ, Q
++, 13...Order instruction in the main scanning direction, 14...Order instruction in the sub-scanning direction Patent applicant NEC Corporation Representative Patent attorney Yuta Kumagai Figure 1 Figure 2

Claims (1)

[Claims] The image processing device includes a converted pixel address calculation circuit that outputs a converted pixel address when linear density conversion is performed, a reference 4 pixel output circuit that receives an output from the converted pixel address calculation circuit and outputs surrounding reference 4 pixels, and a main circuit. a conversion method selection instruction circuit for setting a selection instruction of a 9-division method or a logical sum method in the scanning direction and the sub-scanning direction; outputs of the conversion pixel address calculation circuit; the surrounding reference 4-pixel output circuit; and the outputs of the conversion method selection instruction circuit. 1. A linear density conversion circuit comprising: a multi-method pixel conversion circuit that realizes pixel conversion using a 9-division method or a logical sum method based on the received data.