SU1231496A1 - Device for displaying information - Google Patents

Abstract

The invention relates to the field of automation and computer technology and is intended for input, storage and display of graphic information. The purpose of the invention is to expand the scope of application by dynamically controlling the input and output parameters. This is achieved by introducing blocks that allow control signals to be generated by the value of the current address, affecting the characteristics of the image, such as bit depth, color, scale, etc. When displaying information on the screen (as in the exchange with a computer), the regeneration address generated in the block the formation of the address goes to the first and second blocks of RAM as the address of these blocks of memory. According to information from their outputs, a final regeneration address is generated, which is fed to the address buses of the memory blocks. At the same time, the data in the second memory unit is analyzed and corresponding signals are generated. The use of the invention allows, for example, in the presence of a display memory whose capacity exceeds the capacity of the screen, to organize information fields of various configurations. It is possible to analyze the bit depth of the output information and change the size of the information field of the memory accordingly. It is possible to bypass the defective parts of the device’s memory and thereby increase its reliability. 7 il. i cl

Description

ten

15

20

25

The invention relates to automation and computing technology and can be used to form graphic images on video terminal screens.

The purpose of the invention is to simplify and. expanding the field of application of the device by providing a dynamic change in the characteristics of the displayed information.

FIG. 1 shows a block diagram of the device; in fig. 2 — data storage and processing unit; in Fig „3 - synchronization unit; 4, a control unit; Fig. 5 shows an address generation unit; in fig. 6 - temporary sequence of operations in the modes of recording and regeneration on the screen; in fig. 7 is a variant of the information word recorded in the first and second blocks of the RAM.

The device contains the first register 1, the synchronization unit 2, the control unit 3, the address generation unit 4, the data storage and processing unit 5, the visualization unit 6, the switch 7, the counter 8, the first operational unit 9, the second operational unit 0, the third register 1I, the second register 12, the decoder 3.

The data storage and processing unit 5 contains memory blocks 14-19, switches 20-25, main memory blocks 26-28, digital-to-analog converter 2F9,

The synchronization unit 2 contains a master 1 generator 30, a point counter 31, a line counter 32, a decoder 33.

The control unit contains an input decoder 34, a test circuit 35, a counter 36, a mode and feature register, 3 7, a decoder for control 38, a decoder 39.

The address forming unit 4 contains a switch 40, a starting address register X 41, a modification register X 42, an adder for coordinate X 43, an output register X 44, a switch 45, a register for starting address X 46, a modification register U 47, an adder for coordinate Y 48, output register Y 49, the register of the starting address 50, the counter address of the regeneration 51, the output switch 52.

FIG. 6 shows the temporal sequence of operations in the recording and regeneration modes on the screen and the following notation is entered: t, - P key

12314962

output registers 44 and 49 to the input of the first 9 and second 10 blocks of RAM; t | - the appearance of the address of the record ira of the output of block 9 and the signs of control at the output of block 10; t, j, is recording the write address in the third register 11 and the write attributes in the second register 12, selecting the memory block and the write mode, connecting the regeneration address counter 51 to the output switch 52; t - the formation of the address in the counter address regeneration 51; t,) is the appearance of the address of the regeneration of the nth word of the image at the output of block 9 and the control indications on the memory, memory,

thirty

35

40

45

tf write address and

block 10;

signs of regeneration in the second and third registers, the choice of the memory unit and the mode of regeneration; tg - formation of the next address in the regeneration address counters 51; t ;, is the appearance of the address of the regeneration of the image word at the output of block 9 and the control signs at the output of block 10; tg - write the address and signs of regeneration into the second and third registers, the choice of the memory block and the regeneration mode; switching switches 20-22 to pass information from selected memory blocks (14-16 or I7--19) and control switches 23-25 (selection of single-channel black-and-white or track-channel color image regeneration option).

FIG. 7a shows a variant of the information word recorded in the second RAM block and inserted

t dena X

YK signs

50

the end of the work on the coordinates X and Y, respectively; Go to page — memory page number (zero page — memory blocks 44-16, first page — memory blocks 17-19); Central Bank - color or black and white version of the regeneration isobrgzhe1P1; BT - bit of the recorded (or regenerated) information.

ria FIG. 75 shows a variant of the information word recorded in the first RAM block, the following designations are introduced here:

R, G, B - channel numbers in the memory page; R — memory block 14 or 17; G — memory block 15 or 18; B - block

memory

16 or 19; Y, Y,

2

X

X, by

two higher address bits in the X and Y coordinates, arriving at the memory blocks.

tf write address and

block 10;

signs of regeneration in the second and third registers, the choice of the memory unit and the mode of regeneration; tg - formation of the next address in the regeneration address counters 51; t ;, is the appearance of the address of the regeneration of the image word at the output of block 9 and the control signs at the output of block 10; tg - write the address and signs of regeneration into the second and third registers, the choice of the memory block and the regeneration mode; switching switches 20-22 to pass information from selected memory blocks (14-16 or I7--19) and control switches 23-25 (selection of single-channel black-and-white or track-channel color image regeneration option).

FIG. 7a shows a variant of the information word recorded in the second RAM block and inserted

t

Denotes X

YK signs

the end of the work on the coordinates X and Y, respectively; Go to page — memory page number (zero page — memory blocks 44-16, first page — memory blocks 17-19); Central Bank - color or black and white version of the regeneration isobrgzhe1P1; BT - bit of the recorded (or regenerated) information.

ria FIG. 75 shows a variant of the information word recorded in the first RAM block, the following designations are introduced here:

R, G, B - channel numbers in the memory page; R — memory block 14 or 17; G — memory block 15 or 18; B - block

16 or 19; Y, Y,

2

X

X, by

two higher address bits in the X and Y coordinates, arriving at the memory blocks.

3

The operation of the device is considered in coi terms with the words of FIG. 7 and the timing diagram of FIG. 6, constructed with regard to the use of dynamic memory in memory blocks 14-19 (e.g., K565RU5).

Record mode.

Preliminarily, in block 9 and block O, the necessary information is loaded, the starting address of the record and its modifications are entered into the corresponding registers 41 and 42, 46 and 47.

Upon arrival in register 1 of data that must be recorded in block 5 of storing and processing data, in block 3 of control, a testing circuit 35 is started. After subsynchronization to the RAS signal generated by counter 36 and decoder 39, the address switching trigger is activated (nef. controlling output switch 52 and connecting to switch 7 the value of the start address of the record, which is in output register X 44 and output register Y 49. Control of switch 7 coming from control decoder 38 is provided, under the condition and there is no record in block 9 or block 10, connecting block 9 and data block Go to the address buses from output switch 52. Thus, the starting address of the record (its most significant bits) goes to block 9 and block 10, and to register input 11 (low-order bits) This happens at time t (Fig. 6). If the starting address of the record in the X and Y coordinates is zero, then the cell address of block 9 and block 10, from which information is read, is also zero. Let the information that appears at the output of the indicated blocks 9 and 10 at the moment of time t, be: all bits are zero and only the sign P is 1. Then at the moment of time t according to the impulse of 3 n generated in the control decoder 38, the signs Y |, Yj, X, Xj and the least significant bits of the address are written along the X and Y coordinates in the register 11, and the signs R, G, B page p. The CB, BT is in register 12. Signs of R, G, B, p. No. go to the decoder 13, at the output of which a signal is formed that allows writing to the memory block 14. A resolution signal is produced. shziy passage to the memory block 14

496

all m signals necessary for recording information. At the same time, a reset occurs indicating that the device can receive the next data for recording. The output switch 52 connects to the switch 7 the contents of the counter of the regeneration address 51. In the address generation block 4, the new write address is prepared by adding on the adder

/ 1o

43 of the contents of the output register X 44 with the value of the register of modifications X 42 and the recording of the obtained result in the output register X 44. A similar operation is performed on the Y coordinate on the adder 48.

The described operation of the device in the Record mode repeats on each write cycle (formed from the arrival of the next data in register 1) until the record address changes one of the most significant bits that are not fed to the inputs of the register 11, but to the address bits. bus block 9. Now from block 9 and block 10 reads the next cell in which other data can be recorded. For example, if there are signs 1 and page number 1, then the information in register 1 will be recorded in memory blocks 17-19. If the sign X is signified on the wils, meaning that the horizontal recording should be completed, then in block 4 of the address generation using the signals generated in the decoder of control 38, a new address of the coordinate X is determined by writing the contents of the initial address register X 41 to the output register X 44. (when the sign Y appears, similar operations are performed on the Y coordinate) i Thus, it is possible to record the information field of a given configuration without defining in the computer the boundaries of this field.

Regeneration Mode.

Beforehand, the register of the start address 50 and the memory blocks 26-28 records the necessary information defining the law for converting data read from memory blocks 14-19 in the process of their advancement to the visualization block and the start address of the reading on the screen (the start address of the regeneration ).

At the beginning of each regeneration frame, the GK signal records the contents of the regeneration address 51 counter.

starting address register 50. This address is via output switch 52 (if not set) and switch 7 (if there is no entry in block 9 and block y enters the inputs of register 11 and the address buses of block 9 and block 10. Let the starting address regeneration is equal to zero, as in the Record mode. In this case, from the output of blocks 9 and 10, they read zeroes from all bits except for the sign P 1. Consider the regeneration cycle immediately following the write cycle. preparation of the regeneration address that comes from the regen address counter Operations 51.

At the moment of BpeMeini t, the final address of the regeneration of the nth word is written to register 11, and the control signs are written to register 12,

The block from which reading will be performed is selected by analyzing in the decoder 13 signs R, G, B and p. and begins reading the information from the selected block. At the same time, at the time tg, the signal from the control decoder 38 increases the content of the regeneration address counter 51 by one, and the new current regeneration address goes to block 9 and block 10.

At the time-tg information (the word regeneration), read from the memory chips of block 14 is written

about

The register of this block, which stores information about several rows of image elements (usually 8 elements). The address of the next n + 1 word of regeneration is recorded in register 11 and at the same time signs of R, G, B and page number of the n-th word of regeneration stored in register 12 are rewritten into buffer trigger of register 12.

This is achieved by compensating for the delay in reading information from memory 14 in the case of using dynamic memory.

In the exporter 13, the feature is analyzed (Rstr. And the control signal of switches 20 and 21 is generated. Information from memory blocks 14–16, or from 17–19 is skipped. At the same time, the contents of the second trigger

g

the register storing the sign of the CB, and the contents of the triggers with the signs R, G, B in the decoder are generated

switch control signal 23-26.

In the case under consideration (i.e., with R 1 and CB 0), the information from the output of the switch 20 is passed through all the switches 23-25 and is fed to all the conversion channels. If blocks 9, 10 and 26-28 are filled in the same way, then on the screen of block 6 visualization there will be a black and white image. If not the same, the image is in the false color.

The described regeneration cycle is repeated throughout the entire frame time. After the regeneration counter 51 in the process of adding to its content changes one of the higher bits that goes to the address buses of block 9 and block 10, the address of the readable cell changes, i.e. the signs at the output of blocks 9 and 10 change.

In this case, R G B i and p. , 1 and through the switches 20-22 passes the contents of the memory blocks 17-19., And through the switches 23-25 passes the information of its channel, i.e. information from memory unit 17 is passed through the switch 23, through switch 24 from the memory block 18 and through the switch 25 25 from the memory block 19. A color image is formed on the screen of the visualization unit 6.

In the Regeneration mode, the signs X and K indicate the boundaries of the floor of the image and ensure the prohibition of the exit from this floor during the process of image movement.

The sign BT, which enters the control unit 3 and the memory blocks 14-18, ensures the formation of picture elements with a given bit rate in the memory blocks.

Thus, the proposed device provides a dynamic change in image characteristics.

Characteristics such as the image bit depth, the number of connected channels of the I-channel, its scale can be changed, the operation in the specified image field and with the specified portions of the memory blocks is ensured. This ensures the bypass of defective parts of the memory, which increases the reliability of the device. On the screen of the visualization block, you can

7

have several independent screens. It is possible, for example, to simultaneously consider some image in color and black-and-white versions, in different bits, i.e. apply the method of bit sections, view without magnification, and near have an enlarged (scaled) image.

Claims (1)

Invention Formula A device for displaying information comprising serially connected first register, data storage and processing unit and visualization unit, sequentially connected synchronization unit, the second output of which is connected to the second input of the storage and data processing unit, control unit, the second output of which is connected to the third input of the storage unit and data processing, and the address generation unit, the second input of which is connected to the second input of the control unit, the input of the first register and is the input of the device, distinguishing in that, in order to simplify the device and the application area expansion by providing a dynamically varying the characteristics of the display information, it comprises a switch, a counter, per31496 the first and second blocks of RAM, the second and third registers and the decoder, the output of which is connected to the fourth input of the storage unit 5 and data processing, the fifth input of which is connected to the third input of the control unit, the input of the decoder and the output of the second register, the first input of which is connected to the first input 10 of the third register, the first entry switch, the first input of the counter, the first input of the first and second RAM blocks, respectively, the output of the second RAM block 15, the memory is connected to the second input of the second register, the third input of which is connected to the second input of the third register and the output of the first memory block, the second input of which. 20 is connected to a second input of a second memory unit, a second input of a counter, and is an input of a device, the output of a counter is connected to a second input of a switch, the third input of which 25 is connected to the output of the address generation unit, and the output of the switch is connected to the third inputs of the first and second RAM blocks and the third register, respectively, 30, the output of the third register is connected to the sixth input of the block x; injury and data processing. 5 FIG. 2 Jall rshllllglnnnшulllJshnlJShll / ulp Ras t per. Adp 1I R sn Rezenetsi. on screen g: 1 regeneration per screen H1h H11ti ty tg tj tg tg FIG. 6 Compiled by, Fountova A. Makovska Editor Tehred V. Kadar Proofreader M, Sharoshi Order 3021 Circulation 671. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Mo Squa, F-35, Raushska nab. D. 4/5   J, .. h gj and J. 4J., Mrs ,, .., in V .. TJ It and h 1-L and JJ I | G I-J, I I, 1-T1 - and 1.., Gj. l 1Л. lg and q 1 Production and printing company, Uzhgorod, st. Project, 4 H11is tg tj