SU732934A1 - Data display on the screen of cathode ray tube - Google Patents

Description

one

The invention relates to automation and computing and can be used in automatic design systems for displaying graphical information using television-type indicators.

A device for displaying vectors containing a high-speed memory, a comparison circuit, an arithmetic unit, shifting registers, a clock generator 1 is known.

A disadvantage of this device is the use of elements, the speed of which makes it difficult to implement the device in practice, as well as the limited number of maps of vectors,

The closest in technical essence is a device for displaying information on a screen of a cathode ray tube containing serially connected exchange register and command decoder connected to a character counter and an interpolator connected to a memory unit connected to a word line connected to a buffer register to genera-

py signs, and series-connected synchronizer and counter 2.

The disadvantage of this device is the need for a large amount of equipment that performs various types of logical transformations and arithmetic calculations.

The purpose of the invention is to increase the reliability of the device due to the simplification of conversions and reduction of the equipment.

This goal is achieved by the fact that the device has entered a task block

15 addresses, adder unit counter ,, comparison circuit, switch and storage register, with 1 INPUTS of the address setting unit connected to the numerical busbar and the outputs of the counter

20 characters and an interpolator, and the output with the first input of the switch and with one input of the comparison circuit, the other input of which is connected to the counter and the second input of the switch, output

25 cxeNKi comparisons are connected to the third input of the switch, the output of which is connected to the address bus connected to the input of the memory unit, the inputs of the adder are connected to the numeric

thirty

bus, unit counter and quad. the input of the switch, and the output with the inputs of the interporter and with one input of the unit counter, the other input of which is connected to the numeric bus connected to the cumulative register,

. Simplification of conversions and reduction of hardware volume is achieved by consistently n-times transforming information presented in coordinate form into a bit map with a step-by-step increase in resolution of conversions. In the described device, the variant for f3 is implemented. At the same time, the image presented in coordinate the form is divided into parts that correspond to the division of the screen into K squares or rectangles, each of which forms a matrix of points.

In the first cycle (at the first stage, a bit map is determined (K bits) for these parts, i.e., units are formed and stored for those parts where there is information (vector part, point or sign) and zeros for those parts where there is no information. Then, each of the K parts of the image is in turn divided into M. The second cycle determines the bit map consisting of M bits for each part where information is available. Those parts that correspond to O in the original bit map are skipped.

The amount of information after the second conversion is

P-M-L,

where L is the number of units in the first bit map.

This information is recorded sequentially, without gaps, into the corresponding zone of the memory block, the number of zones in which is determined by the number of conversion steps.

The device determines that the number of the cell containing the information corresponds to the address of the memory block when converting vectors of arbitrary orientation.

Similarly, each of the M parts is divided into smaller parts and a third of the bit map is defined, the amount of information in which is equal to / n

.L

where N is the number of parts into which each of the M parts is divided;

L. - (The number of units in the second card is bits.

The received information is recorded in the third zone of the memory block, for which the device determines the addresses corresponding to the number of the cell containing the information.

In each conversion cycle, information from the computer enters the complete image frame, where, for example, a point is determined by coordinates on the X, Y axes, a vector by the coordinates of its end points or an increment value, and a sign by a sign code. The type of information is determined by the KOMfHdi (order) computer data, the pixel data (point coordinates, vector coordinates or sign code) information received from the computer at the request of the device, which issues a request for new information on the data conversion end signal of the previous element to the computer. The character codes are written into one of the zones of the memory block with the corresponding identifier, i.e. one bit is allocated in the cell of the memory block, the unit value of which determines the character code in this cell, and the zero value of this bit corresponds to the bit map in this cell.

The drawing shows a block diagram of the device.

The graphic information display device comprises an exchange register 1, which serves to exchange information with a computer; the decoder of 2 commands, which provides storage and decoding of the operation modes of the converter, determines the modes of signs, points or vectors, depending on (order) a command received from a computer; a 3 character counter, intended to determine the sequence of matrix addresses in which the characters are to be displayed; the address setting unit 4, which serves to find the address of the memory cells corresponding to the matrix number in vector mode, and to generate memory address addresses corresponding to the matrices in which the vector starting point, sign or point, whose coordinate is given from the computer, interferes: an adder 5 in which the units read from the first and second zones of the memory block are counted and the values of the coordinate increments for interpolating the vectors are determined; interpolator 6 defining the coordinates of screen points and. the corresponding addresses of the matrices through which this vector passes; a 7 units counter for decrypting and counting units in a word selected from a memory block; a synchronizer 8 generating a pulse train for synchronizing the operation of the device; counter 9, which sets the sequence of selected matrixes in the first zone of the memory block; circuit 10

comparison, designed to determine the moment of equality of the current address of the matrix formed during the sequential polling of the first zone of the memory block with the address formed by the address generation circuit; a switch 11 serving to transmit the received address of the memory block. at the corresponding points in time to the address bus of the memory block; a memory tree 12, which stores the converted information and provides for the regeneration of the image on the indicator screen; a cumulative register 13 for generating a matrix of bits of the matrix and storing information when several vectors or points pass through one matrix; buffer register 14, ensuring the coordination of the speed of sampling information from the memory block and the issuance of this information on the indicator; 15 character generator, in which the character code is converted into a sequence of points when the character is displayed. on the screen.

The device works as follows.

Information from the computer enters the exchange register and is divided into graphic and control information. The control information is remembered and, after decryption by the decoder of the commands, determines the mode of operation of the device,

In the vector mode, the graphical information, for example, the coordinates of the starting and ending points of the vector, from the exchange register goes to an interpolator, in which the numbers of the matrices through which the vector passes are determined. The matrix numbers are converted into addresses of the first zone of the memory block, in which the units are written into the corresponding cells. This is a rough interpolation.

In the point mode, the matrix address is uniquely determined by the coordinates of this point, and the unit is written only in one cell corresponding to the matrix.

Such a transformation is performed for all vectors and frame points, the boundaries of which are determined by the command (order). Start of frame

After this, the second stage of information conversion occurs, at which information is recorded in the second zone of the memory block. For this, vector interpolation is performed and the cut of the bit of each matrix through which the vector passes is determined. This bit map is written to a register, for example with a capacity of 64 bits. The information in the register is then divided, for example, into 8 parts, and an 8-bit code is compiled, in which the unit corresponds to the section of the register in which there is information, and the zero corresponds to the section with zero information. Then the 8 - bit code is written into one of the cells of the second zone of the memory block. The address of this cell is determined as follows. The matrix number is determined by the interpolator just as when filling the first zone, and is supplied by the task block

0 addresses 4 to one of the inputs of the comparison circuit 10, Then, sequential reading of information from the first zone and counting of units recorded there is performed.

five

The code of the current matrix number from counter 9 is fed to the second input of the comparison circuit, and if it is equal to the unit code of the 4 address assignment, the code from the unit counter, which is the cell address of the second block zone

0 memory, passes through the switch 11 to the address bus, g. If the first and second zones are located in the same memory block, the address of the second zone is determined

5 as the sum of the code defining H9mer of the last cell of the first zone, and the code of the unit counter 7, This - the sum is calculated in the adder 5,

To get in one

0 matrix information about several lines (points, signs) passing through this matrix,; cumulative register 13 records information already existing in this matrix, and

5 it is added - new data from the interpolator, after which the summary information is again written into the memory block.

When displaying the characters, the position of the first character is determined and the address of the memory location is determined, where this character is located. This address is written to character counter 3. When each next character is written, the counter increments the address by

5, the characters and all the signs of the sign zone are recorded sequentially in the cells of the memory block corresponding to the sequential arrangement of the matrices on the screen. When writing a mark

0 unit is added to the memory unit cell, which is a character code identifier.

After i completion of the second stage of conversion, the formation and recording of information into the third zone is performed. This stage differs from the second only in the method of determining the addresses of the memory block and in that the information about the characters

0

The address of the third zone is defined as follows.

The number of the desired and current matrixes is supplied to the comparison circuit, as when writing to the second zone. Then

five

sequential reading of information from the first zone is performed, and if there is a unit in it, a successor is selected, and information from the second zone of the memory block is selected. The code of the cells of the second zone of the memory block passes through the adder 5 and accumulates in the unit counting unit 7. When a comparison with cxe№j compares 10, the signal is equal to, the code from the unit counting unit goes through the switch 17 to the address bus of the memory unit.

Further, the information from the third zone of the memory block is read into the cumulative register 13 and after adding the code to it, the interpolator is written again into the memory block so that each part of the register and powerful information, for example, of 8 bits, are written sequentially into eight-bit memory cells. The parts of the register that correspond to zeros in the word of the second zone of the memory block are skipped and are not recorded anywhere,

Before the start of a full cycle of converting all the information in the three zones of the memory block is erased by a command from the computer.

The process of image regeneration, i.e. The output of information to the indicator is performed as follows. The sequential addresses of the cells of the third zone of the memory block are determined and the information from them is written to the corresponding places of the buffer register 14. The buffer register has a capacity equal to the product of the number of matrices located along the screen line by the number of points in one matrix. So, if the screen is divided into 512 512 points, then 64 matrices are placed along the line, and the buffer register must have a capacity of 4096 bits or 512 bytes,

Thus, by repeating the same operations, a reduction in the equipment and a gain in reliability of the device is achieved.

Claims (2)

Invention Formula 5 A device for displaying information on the screen of a cathode ray tube containing serially connected exchange register and descriptor, commands connected to a counter and an interpolator connected to a memory block connected to a word line connected to a buffer register connected to the character generator , and sequentially connected synchronizer and counter, characterized in that, in order to increase the reliability of the device, an address setting block, a score 0-Chick units, a comparison circuit, a switch are entered into it op and a cumulative register, the inputs of the address setting block are connected to the numeric bus and the outputs of the character counter and interpolator, and the output is connected to the first input of the switch and one input of the comparison circuit, the other input of which is connected to the counter and the second input of the switch, the output of the circuit compare connected to the third input of the switch, the output of which is connected to the address bus connected to the input of the memory unit, the inputs of the adder are connected to the numeric bus, the unit counter and the fourth input of the commutator, and the output to the inputs of the interpolator and one input of the unit counter , whose other input is connected to a numeric bus connected to a cumulative register, 0Sources of information taken into account in the examination 1, Patent IT W 3893075, .kl, 340 / 172.5; 340/324, 01.07. 75. 2. US patent 3891982, cl. 340/324, 1975, Lr-7 dfecHOiA lima na