SU1741123A1 - Apparatus for representing information - Google Patents

Abstract

The device contains a control unit 1, an address selector 2, a multiplexer 3, two registers 4 and 10, four elements 5, 6, 7 and 14, a synchronization unit 8, a signal conditioner 11, a decoder 12, a counter of 13 characters. 1-2-5-3-9-4, 1-4, 1-9-10-14, 1-5-3-9, 1-6-4. 2-6, 2-7-1.8-13- 3.9- 13, 8- 10, 8- 11 -14, 8-9, 8-3, 8-4, 8- 1, 8-7, 11 - 14- 13, 11 - 13. 2 Il.

Description

1

The invention relates to automation and computing and can be used to display information on the screen of a cathode ray tube (CRT) in data processing systems controlled by a microprocessor, in particular in video terminals, displays, personal computers.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a structural device diagram for displaying information; figure 2 - timing charts of his work.

The device contains a control unit 1, an address selector 2, a multiplexer 3 / first register 4, a first element AND 5, a second element AND 6, a third element AND 7, a synchronization unit 8, a block 9 of memory, a second register 10, a driver 11, a decoder 12, the counter is 13 characters, the fourth element is And 14. FIG. 1 shows the data bus 15 of block 1, the bus 16 of the address of block 1, the output 17 of the device, the exit 18 of the horizontal scan, the output 19 of the frame scan.

One example of a device implementation is the following solution.

The first 5, the second 6, the third 7 and the fourth 14 elements And - K555LI1; block 1 - microprocessor KR1810VM86, ROM - K573RFCHA, RAM - KR537RU8A; multiplexer 3 - KR531KP7; counter 13 characters with parallel entry - К555IE10; synchronization unit 8 - integrated circuits of series KP531; Km 1556; block 9 of video information memory - КР565РУ5В; the first register 4 with three exit states is K555IR23, the second register 10 is shear K555IR10; shaper 11 signals of horizontal and vertical synchronization - integrated circuits of series K555, KM 1556; the decoder 12 and the selector 2 addresses - K555ID4.

The synchronization unit 8 in the simplest case can be made in the form of a generator, a binary counter-divider and a programmable logic matrix. The generator generates pulses with a frequency of points arriving at the input of the counter-divider. The outputs of the divider counter are connected to a programmable logic array in which the logical functions of all outputs of synchronization unit 8 are flashed (except for the sixth output of synchronization unit 8, which is the output of the clock generator) in accordance with FIG. 2.

The shaper 11 signals horizontal and frame synchronization can be performed on two counters with a reset (not shown). The first counter receives a signal with a frequency of characters from the seventh exit

block 8 sync. This counter counts the number of characters corresponding to the forward and reverse course of the ETL beam along the line, and at the output of its most significant bit (first output 18 of the imaging unit 11), a reverse signal is generated along the line. The second counter counts the number of lines corresponding to the forward and reverse paths of a CRT beam across the frame, and the output of its high-order bit (the second output 19 of the imaging unit 11) generates a reverse signal over the frame. The blanking signal at the third output of the imaging unit 11 of the horizontal and vertical sync signals, which is fed to the first input of element 14 I, is the sum of the return signals for the line and the return signal for the frame.

The device works as follows.

The synchronization unit 8 generates, at the second and third outputs, the row selection (PA) and column selection (CA) signals of the dynamic memory, respectively, arriving at the corresponding inputs of the video information memory block 9, with a frequency twice as high as necessary to support the image regeneration process Thus, the cycle of accessing block 9 consists of two cycles: the cycle of reading information into the shift register 10 and the cycle of transmitting or receiving information from (or in) block 1.

This increase in frequency slightly increases the speed requirement of video memory block 9, but at the same time guarantees high image quality, since the process of information exchange from block 1 does not affect the information display process.

The signal from the second output of the synchronization unit 8 also goes to one of the control inputs of the multiplexer 3. Thus, the address bits for the dynamic memory of the block 9 are multiplexed, for a single value of the signal at the second output of the block 8 with a zero value - the bits of the choice of columns. The other control input of the multiplexer 3 receives a signal from the first output of the synchronization unit 8. When this signal is zero, multiplexer 3 connects the address inputs of block 9 of video information memory to bus 15 of address from block 1. At a single signal value at the first output of block 8, multiplexer 3 connects to address inputs of bls. e 9 counter outputs 13 characters for reading information into the shift register 10 and displaying it on the E.PT screen. The signal from the first output of block 8 is also delivered to the clock input of register 4 with three output states, which is on the front of the signal from the first output of block 8 (i.e. at the end of the cycle intended to communicate with block 1) information is written from the outputs of block 9 for reading into block 1. When accessing (reading or writing) to block 9, block 1 generates an address that arrives on the address bus 16 to the first information inputs of the multiplexer 3. The higher address bits also come from the address bus 16 to the inputs of the selector 2 address, the output of which is formed sig Selecting block 9. When reading information into block 1 from block 9, the selection signal and the read signal coming from the corresponding output of block 1 coincide at the inputs of element 6. At the output of this element, in this case, a signal is generated that goes to the output of the output resolution register 4, and information from block 9 to register 4 is read via data bus 15 to block 1.

In order to synchronize the information exchange cycle of block 9 with block 1 and the read cycle to the shift register 10, synchronization block 8 generates a clock signal at the fourth output of block 8 arriving at the clock input of block 1, as well as the signal at the fifth output of block 8, controlling readiness. The signal from the fifth output of the block 8 is fed to the first input of the element And 7, the second input of which receives the signal to select the block 9 from the output of the address selector 2. The signal from the output of the element And 7 enters the ready input of block 1. Thus, in the absence of a signal to select block 9, a low level signal is generated at the ready input of block 1, which corresponds to the presence of readiness. When a select signal of block 9 appears at the ready input of block 1, a high level signal appears (unavailability) and block 1 is put into a standby state until the signal from the fifth output of synchronization block 8 goes into a low level state.

When recording information from block 1 to block 9, data from block 1 via the data bus 15 is fed to the information inputs of block 9 of the video information memory. Unit 1 sets the address to the address bus 16 and the write signal arriving at the first input of the And element 5. The second input of this element receives the signal of selecting block 9 from the output of the address selector 2. In the presence of a select signal, the recording signal passes to the output of an Ibis element to the input of multiplexer 3. Upon the arrival of a signal from the first

the output of block 8 is low to the control input of multiplexer 3, which corresponds to the cycle of information exchange between block 1 and block 9, multiplexer 3 connects the address inputs of block 9 of video information memory to address bus 16, and the write input of block 9 to output element I 5 Thus, data is recorded in the video memory block 9.

0

When the power is turned on, block 1 records in block 9 the information necessary for displaying on a CRT screen, a memory area allocated for one television channel.

5 line must contain one cell more than is necessary for video information. And in each TV line in the last cell, the contents of which is not displayed on the screen, block 1

0 writes a binary code defining the starting address of the next TV line. This code is entered in the counter 13 characters after the end of the regeneration of each television line. And this code

5 is calculated as the difference between the starting address of the line and the number of characters required on the return stroke on the line. Since, during a return stroke on a row, the 13-digit counter continues counting in the mode of summation, the current at the time of the beginning of the forward stroke on the row its contents will be equal to the initial address of the next displaying television row. Such a method makes it possible to place the displayed information B with the minimum memory size, without empty cells usually left in the memory to compensate for the fact that the power of two is not twice the length of the displayed line.

Image formation is as follows.

The signal at the output 19 of the reverse beam CRT on the frame received from the second output of the imaging unit 11 signals horizontal and frame synchronization to the input

5 reset the counter of 13 characters, the counter of 9 characters is synchronized with the beginning of the image frame. Thus, the first television line of the raster has a fixed zero initial adobe and in most cases is used as a service line. For a single signal at the first output of block 8, multiplexer 3 connects the output of the counter 13 characters to the adress inputs of block 9

5 video memories. The information read in this case from block 9, with a low signal level at the seventh output of the synchronization block 8, which enters the control input of the parallel recording of the shift register 10, is written to this

register on the leading edge of the clock signal from the sixth output of block 8.

With a single value of the signal at the seventh output of block 8, the shift register 10 converts the recorded information into a sequence of points displayed on a CRT screen. The signal from the seventh output of block 8 is also fed to the counting input of the counter 13 characters, increasing the address of the information read into the shift register 10 with the frequency of characters. The same signal is fed to the counting input of the imaging unit 11 signals horizontal and frame synchronization. The first counter of the imaging unit 11 (not shown) counts on the front of the signal from the seventh output of block 8, the number of pulses corresponding to the number of characters on the forward and reverse course of the ETL beam along the line; at the output of its higher bit, a reverse signal is generated on the line arriving at the output 18. This signal also arrives at the counting input of the second counter of the imager 11. The second counter counts the number of lines on the forward and reverse run of the CRT beam over the frame and at the output of its high-order bit a reverse signal is generated on the frame arriving at output 19. Information from the outputs of the generator 11 of the horizontal and vertical synchronization signals (outputs of the first counter) is fed to the inputs of the decoder 12, which decrypts the moment of the end of the forward stroke along the line and generates a signal to the input of the control by parallel recording of the counter 13 characters.

At the output of the 13-character counter, at this moment there is a cell address in which a code is stored defining the starting address of the next TV line. This code is read from block 9 of video memory and is loaded into the counter 13 characters on the next clock edge coming from the seventh output of block 8. This same code is written to the shift register 10 and in order to block its output to the device output 17 (output video signal), between this output and the output of the shift register 10, an element 14 is switched on, the second input of which receives a blanking signal from the output of the generator 11 of the horizontal and vertical synchronization signals, which is the sum of the reverse signals on line and reverse on frame.

Thus, by introducing 13 characters into the device for displaying the counter information by parallel entry of information, decoder 12 and AND element 14 and corresponding links, it is possible to arbitrarily change the order of information display by changing the codes at the end of the lines written in block 9

video memories defining the starting address of the next displayed line. This factor explains the increase in the speed of the device, since for such a change it is not necessary to rewrite the entire amount of video information. Such changes include, in particular, such functions as switching the displayed video memory pages, replacing an arbitrary number of information lines with others, deleting an arbitrary part of the lines, inserting an arbitrary number of lines, moving the image horizontally, moving the image with a jump (or hard rolling) on

0 one information line (for a text image), moving the image vertically with discrete to one TV line (or smooth rolling), etc.

5 For example, the algorithm of the last named function can be implemented as follows (moving up). In the last upper unmovable row A in its last cell, the code of the address of the next line A + 1 is replaced with the address code of the line A + 2, i.e. line A + 1 is excluded, and in its place line A + 2 is displayed. In the last bottom floating line B in its last cell, the address code

The next 5 lines B + 1 is replaced with the code of the address of the new, inserted B line, in the last cell of which the code of the address of the B + 1 line is recorded. Thus, all lines after line A are moved up.

0 by one TV line, line A + 1 is eliminated and a new line B appears at the bottom of line B + 1. To realize this movement, it is enough to change the contents of the three cells containing the codes of address addresses of lines, whereas in the prototype, when implementing this movement function, you need to programmatically produce overwrites equal to (BA) -C, where (BA) is the number of rows to be moved, and

0 С - the number of characters in a line. For example, with (BA) 240 and C 50, the number of overwrites with the software method is 12,000, then the speed increase can be considered equal to 12,000: 3,000 times.

5 Building on the basis of the proposed device for displaying information, the data display system can significantly improve speed and improve ergonomic indicators.

Claims (1)

The invention includes a device for displaying information comprising a control unit, an address selector, a first register, first, second and third elements AND, a synchronization unit, a memory unit, a second register and a signal conditioner, the input / output of the control unit being connected to the information input of the memory unit. and the output of the first register, the output of the memory unit is connected to the information inputs of the first and second registers, the address input of the memory unit and the record control input are connected to the first and second outputs of the multiplexer, the first and the formation input of which is connected to the first input of the control unit connected to the information input of the address selector, the first control input of the multiplexer is connected to the output of the first And element, the first information input of which is connected to the second output of the control unit, the second information input of the first I element is connected to the output of the address selector connected to the first information inputs of the second and third And elements, the second information input of the second And element is connected to the third output of the control unit The output of the second element I is connected to the control input of the first register, the clock input of which is connected to the first output of the synchronization unit connected to the second control input of the multiplexer, the third control input of which is connected to the first control the memory input, the second control input of which is connected to the third output of the synchronization unit, the fourth output of which is connected to the clock input of the control unit, the control input is ready which is connected to the output of the third element I, the second information input of which is connected to the fifth output of the synchronization unit, the sixth output of which is connected to the clock input of the second register, the input of the control for entering characters is connected to the seventh output of the synchronization unit connected to the information input of the signal conditioner, the first and the second outputs of which are the outputs of the horizontal and vertical synchronization of the device, characterized in that, in order to increase the speed of the device, the decoder, the character counter and the fourth And element, the output of which is the output of the modulated signal of the device, the first information input of the fourth And element is connected to the output of the second register, the second information input of the fourth And element is connected to the third output of the signal conditioner, the fourth output of which is connected to the information input the decoder, the output of which is connected to the control input of the character counter, the output of which is connected to the second information input of the multiplexer, the counting input account ika signs connected to the seventh output of block synchronization characters price calculation information input connected to the output memory unit, signs of the counter reset input connected to the second output of the signal shaper. Out 6 block sync Out blockade sync Out 2 blocks Vyh.Z 5loko 8 Output 1 block in Zsh4 block 8 Output 5 block 8 15 o 2 3 5 6 S 11 12 13 No. 15 O TJlJl rLJl n nj J JHJ JlJ 5 6 S 11 12 13 No. 15 O