JPS6353755B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a storage device (hereinafter referred to as memory).
The present invention relates to an image display device having an image display device, and in particular improves the structure of a memory.

In an image display device, for example, to display an input image signal having a scanning speed different from that of the display section, or to perform signal processing such as averaging on the input image signal and then display it. In recent years, a memory has been installed in an image display device to perform scan conversion. Conventionally, as a form of memory control in a display device having such a memory, a temporary memory of an appropriate size is provided, and the main memory is read out continuously in accordance with the scanning of the display section. Methods such as using the retrace time of scanning to move the contents of temporary memory to main memory are used. However, this type of method has the disadvantage that it requires a temporary memory, or that it is troublesome to control the transfer from the temporary memory to the main memory.

This invention operates on an independent clock source for each write/read operation of the main memory, and has dedicated sections for each write/read operation so that, for example, one write operation can be performed multiple times. By providing this, it is possible to independently perform the writing of the image signal into the memory and the reading and displaying of the image signal from the memory with a simple configuration, thereby facilitating scanning exchange.

The contents of this invention will be explained below with reference to embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of this embodiment.

In FIG. 1, numeral 1 denotes an encoding circuit that encodes an image signal to be displayed. 2 is a synchronous circuit, and 3 is a write clock generation circuit, which is a write clock (hereinafter referred to as W).
(referred to as a clock). 4 is a buffer for writing. Reference numeral 5 denotes a write address selection circuit, which is configured to sequentially scan the address to which the image signal encoded by the encoding circuit 1 is to be written every W clock. 6 is a write flag circuit, 7 is a write enable circuit, and the memory 12 writes data in the write buffer 4 when the write enable signal output from the write enable circuit 7 is [1]. It is configured to write to the address specified by the address selection circuit 5. Reference numeral 8 denotes a read clock generating circuit which generates a read clock (hereinafter referred to as R clock) having a required period determined from the scanning speed of the display section 14. 9 is a write/read control circuit, R
Generates memory control signals synchronized with the clock. The memory control signal determines a write section (hereinafter referred to as W section) and a read section (hereinafter referred to as R section) having a required number of times ratio. Reference numeral 10 denotes a read address selection circuit which scans the address of data to be read from the memory 12 in every R section in synchronization with the scan of the display section 14. Furthermore, 11 is an address signal switching circuit,
The address signal applied to the memory 12 is switched so that it is applied from the write address selection circuit 5 when the memory control signal indicates the W section, and from the read address selection circuit 10 when the memory control signal indicates the R section. The read address selection circuit 10 and the write enable circuit 7 are a write/read operation control circuit that performs a write operation to the image signal memory 12 and a read operation of the image signal from the memory mutually independently. Configure. 13 is a read buffer, and 14 is a display section. Display section 14
The details are omitted as they are not related to the essence of the present invention, but the data read out to the read buffer 13, that is, the image signal to be displayed, is displayed at the display position corresponding to the address of the read address selection circuit 10. be.

Now, the operation of this embodiment is as follows. As described above, the memory control signal is divided into a W section and an R section having a required frequency ratio of 1:N, and this is shown in FIG. 2A.

First, the write operation will be explained. The image signal to be displayed is sampled every W clocks by the encoding circuit 1, encoded, and set in the write buffer 4. Note that the W clock does not need to be synchronized with the R clock, as will be clear from the following explanation. Here, one read and write time is T ₀ ,
If the frequency ratio N and T 0 of the R interval and the W interval are selected so that the period T _W of the W clock, that is, the period T W at which the image signal is sampled, is T _W (N+2)T ₀ , then the frequency ratio N and T ₀ of the R interval and the W interval are selected as shown in Fig. 2B. The period of the W clock as shown in
At least one W interval is completely included between T _W. On the other hand, as shown in Figure 2C,
The write flag circuit 6 is set every W clock. This write flag is tested at the rising edge of each W interval, and when the write flag is set, the write enable circuit 7 is set to generate a write enable signal (FIG. 2D). This write enable signal causes a predetermined write operation to occur. If the W clock is generated in the middle of the W interval, no write enable signal is generated during that interval, and no write operation occurs during that interval. Further, after writing is completed, the write flag and write enable signal are reset. Therefore, one (and only one) write operation is always performed for one W clock, and the image signal sampled by that W clock is sent to the write address selection circuit 5. Written to the specified predetermined address.

Note that the correspondence between the sample point coordinates of the image signal and the address of the memory is realized by the synchronization circuit 2 resetting the write address selection circuit at a predetermined period.

Next, the read operation will be explained. During the R period synchronized with the R clock, the address of the memory 12 is designated by the read address selection circuit 10. Also, at each end of each R section, the read data from the memory 12 is transferred to the read buffer 1.
It is set to 3. Therefore, for each R interval, as shown in FIG.
3. This image signal is transferred to the display section 14 and displayed there. The average scanning speed for each sample in this read operation is N/(N+1)
It is clear from the above explanation that T ₀ .

Note that when the write/read control circuit 9 is configured such that N=1, that is, the R interval and the W interval occur alternately, the read cycle and write cycle for each sample are 2T ₀ and 3T, respectively. It is ₀ .

In addition, in the above explanation, when the memory control signal is generated in synchronization with the read clock and the read cycle per sample, that is, the display cycle is shorter than the write cycle per sample, that is, the sample cycle of the input signal. However, with regard to the former, it is clear that the same operation can be realized even if the memory control signal is generated in synchronization with the write clock. Also, regarding the latter, 1
It is also clear that by providing a plurality of write sections for one read section, the present invention can be applied even when the write period is shorter than the read period.

As explained above, the present invention provides a read clock independent of a write clock that matches the sampling period of an image to be displayed, and uses this read clock to distinguish between a read-only section and a write-only section having a required frequency ratio. By generating a memory control signal consisting of You can try to get it.

As a result, an advantage is obtained that it is possible to easily display not only images having a scanning period different from that of the display section but also images having a scanning format different from that of the display section.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG. In the figure, 1 is an encoding circuit, 2 is a synchronization circuit,
3 is a write clock generation circuit, and 4 is a write buffer. Further, 5 is a write address selection circuit, 6 is a write flag circuit, and 7 is a write enable circuit. Furthermore, 8 is a read clock generation circuit, 9 is a write/read control circuit, 10 is a read address selection circuit, and 11 is an address signal switching circuit. Furthermore,
12 is a memory, 13 is a read buffer, and 14 is a display section.

Claims (1)

[Claims] 1. In an image display device having a storage device that stores an image signal to be displayed, reproduces it and displays it directly or after performing necessary signal processing on a display section, the image signal is sampled and A write clock source for writing to the storage device and the write clock source are configured independently, and a read clock source for reading image signals from the storage device and the write clock source or the read clock source. dividing the storage device into a read-only section several times in succession for every write-only section of the storage device, or a write-only section several times in succession for every read-only section in synchronization with one of the sources; a write/read control circuit for generating a memory control signal; and a write/read control circuit that independently performs a writing operation of the image signal to a storage device and an operation of reading the image signal from the storage device based on the memory control signal. An image display device comprising: a write/read operation control circuit.