JPH10171434A - Synchronous conversion device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous conversion device which does not cause so-called jumping phenomenon in which two kinds of images are read in one screen. SOLUTION: This device has a FIFO(first-in first-out) type frame memories 1A, 1B, switches SW1, SW2, a D flip-flop 3, and an inverter 5. Here, a write memory selection signal WFMEMSEL which shows a memory frame in the writing at the time of beginning to be read, is latched by the D flip-flop 3, and the switch SW2 selects the ground memory by a read memory selection signal R FMEMSEL which is the reversed signal of WFMEMSEL, and the image data of the frame preceding to the one in the writing are read.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a synchronization conversion apparatus and method for converting synchronization of a video signal.

[0002]

2. Description of the Related Art Heretofore, there has been known a synchronous conversion device of this type which converts the synchronization of a video signal displayed on a monitor screen of a computer or the like. FIG. 3 is a diagram showing a configuration of a frame memory used in a conventional synchronous conversion device and a timing chart of its input / output signals. In the synchronous converter, a FIFO (Firt in Firt Out) type frame memory 10a is used. The FIFO type frame memory is a memory that sequentially reads out image data that has been written first, and usually performs a write operation and a read operation simultaneously. The frame memory 10a has a data input terminal for inputting image data (DATAN) of a video signal to be written, a write clock terminal for inputting a write clock (WCK), and a write reset terminal for inputting a reset signal (WRST) for a write address counter. A data output terminal for outputting read image data (DATA OUT), a read clock terminal for inputting a read clock (RCK), and a read reset terminal for inputting a reset signal (RRST) of a read address counter.

FIG. 4 is a diagram showing writing and reading of image data in the frame memory 10a. When writing the image data of the video signal to the frame memory 10a, the writing is performed in order from the 0th frame in the cycle Tw. When the writing of the 0th frame is completed, the reset signal (WRST) of the write address counter is input, the write address returns to the start address of the frame memory 10a, and the next frame (first frame) is written therefrom. A similar operation is repeated for each frame. On the other hand, when reading image data written in the frame memory 10a, reading is performed sequentially from the 0th frame at a period Tr shorter than the period Tw at the time of writing. Although the write operation and the read operation are asynchronous, it is assumed here that the phases are aligned at the beginning of the first frame on the write side and the first frame on the read side for convenience. The read operation is faster than the write operation (Tr <T
w), the image of the 0th frame, which has already been written, is read in the first frame on the reading side. Subsequently, at the start of the second frame on the reading side, the writing on the first frame on the writing side has been completed about ／, and the image on the first frame is read on the reading side. When reading the third frame, the writing side has finished writing the second frame by about 1/4 at the start of the reading of the third frame (point a in the figure). Start reading.

[0004]

However, since the writing side has not finished writing the second frame when the reading side has finished reading the third frame,
A read operation jumps a write operation within one screen. When such a so-called jumping phenomenon occurs, the image currently being written (the image of the second frame) is read before the jumping occurs, but after the jumping, the image of the frame before the writing has already been completed (the image of the second frame). The image of the first frame is read out (see the third frame on the reading side in the figure). This jump phenomenon occurs in a certain cycle due to the time difference between the cycle Tw and the cycle Tr. In the figure, the skipping phenomenon similarly occurs in the sixth frame on the reading side. Therefore, two images are read in one screen, which results in a loss of image quality in the case of a moving image. Therefore, an object of the present invention is to provide a synchronous conversion device and method which do not cause a so-called jump phenomenon in which two types of images are read on one screen.

[0005]

In order to achieve the above object, a synchronous conversion device according to the present invention writes image data in a frame memory at a predetermined writing cycle, and writes a predetermined amount of image data from the frame memory to which the writing has been performed. In the synchronous conversion device for converting the synchronization of the video signal by reading the image data in the read cycle, a plurality of frame memories storing the image data in frame units, and any one of the plurality of frame memories Writing memory selecting means for sequentially selecting in the writing cycle, writing means for writing the image data in the selected frame memory, and detecting the frame memory which has just finished writing immediately in the reading cycle. Detecting means, reading memory selecting means for selecting the detected frame memory, and the image data from the selected frame memory. Characterized by comprising a reading means for reading out. Also, the synchronous conversion method of the present invention writes the image data in a frame memory at a predetermined writing cycle, and reads out the image data at a predetermined reading cycle from the written frame memory, thereby synchronizing the video signal. In the synchronous conversion method, any one of a plurality of frame memories storing image data in units of frames is sequentially selected in the writing cycle, and the image data is written in the selected frame memory. The frame memory for which writing has been completed is sequentially detected in the read cycle, the detected frame memory is selected, and the image data is read from the selected frame memory.

In the present invention, one of a plurality of frame memories storing image data in frame units is sequentially selected at a predetermined writing cycle, and the image data is stored in the selected frame memory by the writing means. And the detecting means sequentially detects the frame memory for which writing has been completed immediately before in the reading cycle, selects the detected frame memory by the reading memory selecting means, and selects the detected frame memory from the selected frame memory by the reading means. Since the image data is read, the so-called jump phenomenon does not occur, and the period conversion can be performed correctly.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a synchronous conversion device and method according to the present invention will be described. The synchronization conversion device according to the present embodiment converts the synchronization of a video signal projected on a monitor screen of a personal computer or the like. FIG. 1 is a circuit block diagram showing a configuration of the synchronous conversion device according to the embodiment. The synchronous converter includes FIFO type frame memories 1A and 1B, switches SW1 and SW
2, a D flip-flop 3 and an inverter 5. F
The IFO type frame memories 1A and 1B are memories that sequentially read image data from the first written image data as described above, and usually perform a write operation and a read operation simultaneously. The frame memories 1A and 1B have a data input terminal (DIN) for inputting image data (DATA IN) of a video signal to be written, and a write clock (WC).
K), a write reset terminal for inputting a reset signal (WRST) of the write address counter, and image data (D
ATA OUT), a read clock terminal for inputting a read clock (RCK), and a reset signal (RRS) for a read address counter.
A read reset terminal for inputting T) is provided.

The switch SW1 is a switch for switching the connection between the input terminal DIN of the frame memory 1A or the input terminal DIN of the frame memory 1B and the signal input line VIDEO IN in accordance with the write memory selection signal WFMEMSEL. The switch SW2 is connected to either the output terminal DOUT of the frame memory 1A or the output terminal DOUT of the frame memory 1B and the signal output line VIDEO.
OUT is connected to the read memory selection signal RFMEMSE.
A switch that switches according to L. The D flip-flop 3 sets the signal level of the write memory selection signal WFMEMSEL input to the D terminal to the reset signal (R) of the read address counter input to the clock terminal CK.
RST) to the output terminal Q. Also,
An inverter 5 is connected to the output terminal Q, and a read memory selection signal RFMEMSEL is generated by inverting the signal level of the output terminal Q by the inverter 5.
Thus, the read memory selection signal RFMEMSEL
Is a signal obtained by latching the write memory selection signal WFMEMSEL according to the reset signal (RRST) of the address counter and then inverting the latched signal. Therefore, the switch SW2 is no longer selected by the write memory selection signal WFMEMSEL, that is, selects the frame memory for which writing has been completed immediately before.

FIG. 2 is a diagram showing the operation of writing and reading image data. FIG. 3A shows the operation on the writing side, and FIG. 3B shows the operation on the reading side. On the writing side, when writing image data sequentially from the 0th frame in the cycle Tw, the frame memory 1A,
1B is switched to alternately write image data.
The switch SW1 is connected to the write memory selection signal WFMEMSE.
When L is at H level, the signal input line VIDEO IN is connected to the input terminal DIN of the frame memory 1B, and when L is at L level, the signal input line VIDEO IN is connected to the input terminal DIN of the frame memory 1A. On the read side, on the other hand, a signal indicating the memory frame selected by the write memory selection signal WFMEMSEL is input to the D terminal of the D flip-flop 3, and the reset signal RRRST of the read address is clocked to the output terminal Q (C).
K), that is, the write memory selection signal WFMEMSEL indicating the memory frame being written at the start of reading is latched. Therefore, the read memory selection signal RFMEMSEL which is the inverted signal of the frame is already written. Memory. Also, a reset signal RRSST of the read address
Is set shorter than the writing period Tw.

The switch SW2 is connected to the signal output line VID when the read memory selection signal RFMEMSEL is at the H level.
EO OUT is connected to the output terminal DOUT of the frame memory 1B.
To the signal output line VIDEO O when it is at the L level.
The UT is connected to the output terminal DOUT of the frame memory 1A. Therefore, in this synchronous converter, the image data of the frame immediately before the frame being written is read, and the skipping phenomenon that has conventionally occurred is eliminated. As described above, two types of image data are not read out in one frame, and when image data is displayed on a monitor screen of a computer or the like, generation of noise on the screen can be prevented. In addition, synchronous conversion of a video signal can be correctly performed, and when a moving image is displayed, image quality can be prevented from being impaired.

In the above embodiment, since a FIFO type frame memory capable of simultaneously performing writing and reading is used, the number of frame memories is only two, and "frame memory for which writing has been completed immediately before" is used. Simply refers to the other frame memory that is not the frame memory currently being written. When using a RAM type frame memory which cannot perform reading and writing at the same time, three or more frame memories are required. For example, if three frame memories are A, B, and C, then A →
When writing is performed in the order of B → C → A → B → C..., C is read when A is being written, A is read when B is being written, and C is being written. In this case, B is read. Further, the synchronous conversion device of the present invention is applicable not only to a case where image data is displayed on a monitor screen of a computer or the like but also to a case where a video signal is transferred between various devices.

[0012]

As is apparent from the above description, according to the present invention, any one of the plurality of frame memories in which the image data of each frame is stored by the write memory selecting means.
One by one in a predetermined writing cycle, and the writing means writes the image data into the selected frame memory.
The detecting means sequentially detects the frame memory for which writing has been completed immediately before in the reading cycle, selects the detected frame memory by the reading memory selecting means, and reads the image from the selected frame memory by the reading means. Since the data is read, the so-called jump phenomenon does not occur, and the synchronous conversion can be performed correctly. Therefore, when the read image data is displayed on the monitor screen, two types of images are not displayed on one screen, and the generation of noise on the screen can be prevented. Further, when displaying a moving image, the image quality is not impaired. Further, according to the present invention, the frame memory is a FIFO type memory capable of simultaneously performing reading and writing, and since two frame memories are provided, the number of frame memories can be minimized. Further, according to the present invention, the detection means comprises a D flip-flop and an inverter, the write memory selection means selects one of the two frame memories by a write memory selection signal, and the read memory selection means When one of the two frame memories is selected by a read memory select signal, the write memory select signal is input to the D terminal of the D flip-flop, and the reset signal at the start of reading is input to the D flip-flop as a clock. Since the write memory selection signal latched in accordance with the clock is inverted by the inverter to be the read memory selection signal, the frame memory in which writing has been completed immediately before is detected. Can be easily and reliably performed.

According to the present invention, the write memory selection means is a switch for switching according to the write memory selection signal, and the read memory selection means is a switch for switching according to the read memory selection signal. Switching can be performed easily and reliably. Further, according to the present invention, since the read image data is displayed on the monitor screen, it is possible to prevent noise from occurring on the monitor screen. Further, according to the present invention, the frame memory is a RAM-type memory that cannot perform reading and writing at the same time, and includes three or more frame memories, so that a versatile memory can be used. Further, according to the present invention, the synchronization of the video signal is converted by writing the image data to the frame memory at a predetermined write cycle and reading the image data at a predetermined read cycle from the written frame memory. In the synchronous conversion method, any one of a plurality of frame memories in which image data in frame units is stored is sequentially selected in the writing cycle, and the image data is written in the selected frame memory, and the immediately preceding writing is performed. Are sequentially detected in the read cycle, the detected frame memory is selected, and the image data is read from the selected frame memory, so that the so-called skipping phenomenon does not occur and the synchronous conversion is performed. Can be performed correctly.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration of a synchronous conversion device according to an embodiment.

FIG. 2 is a diagram showing write and read operations of image data.

FIG. 3 is a diagram showing a configuration of a frame memory used in a conventional synchronous conversion device and a timing chart of input / output signals thereof.

FIG. 4 is a diagram showing writing and reading of image data in a frame memory 10a.

[Explanation of symbols]

1A, 1B ... frame memory, 3 ... D flip-flop, 5 ... inverter, SW1 ... switch, SW2
……switch.

Claims (7)

[Claims] 1. Synchronous conversion for converting image signal synchronization by writing image data to a frame memory at a predetermined writing cycle and reading the image data at a predetermined reading cycle from the written frame memory. A plurality of frame memories for storing image data in frame units; a write memory selecting means for sequentially selecting any one of the plurality of frame memories in the writing cycle; Writing means for writing the image data into the memory; detecting means for sequentially detecting the frame memory for which writing has been completed immediately before in the read cycle; read memory selecting means for selecting the detected frame memory; Reading means for reading out the image data from the selected frame memory. 2. The synchronous conversion device according to claim 1, wherein said frame memory is a FIFO type memory capable of simultaneously performing reading and writing, and comprising two frame memories. 3. The detection means comprises a D flip-flop and an inverter, the write memory selection means selects one of the two frame memories by a write memory selection signal, and the read memory selection means selects a read memory selection. When selecting one of the two frame memories by a signal, the write memory selection signal is input to a D terminal of the D flip-flop, and a reset signal at the start of reading is input to the D flip-flop as a clock, The write memory selection signal latched in accordance with a clock,
3. The synchronous conversion device according to claim 2, wherein the frame memory in which writing has been completed immediately before is detected by inverting the frame memory by the inverter to obtain the read memory selection signal. 4. The write memory selection means is a switch that switches according to the write memory selection signal, and the read memory selection means is a switch that switches according to the read memory selection signal. Synchronous conversion device as described. 5. The synchronous conversion apparatus according to claim 1, wherein the read image data is displayed on a monitor screen. 6. The synchronous conversion device according to claim 1, wherein said frame memory is a RAM type memory which cannot perform reading and writing at the same time, and includes three or more frame memories. 7. Synchronous conversion for converting image signal synchronization by writing image data to a frame memory at a predetermined writing cycle and reading the image data at a predetermined reading cycle from the written frame memory. In the method, any one of a plurality of frame memories in which image data in a frame unit is stored is sequentially selected in the writing cycle, and the image data is written in the selected frame memory. Synchronously converting the detected frame memory in the read cycle, selecting the detected frame memory, and reading the image data from the selected frame memory.