JPH0837649A - Memory control circuit of picture display device - Google Patents

Abstract

PURPOSE:To convert interlace signals into non-interlace signals even when a specified memory is used by controlling the write speed of the horizontal blanking period of the interlace signals to be faster than the write speed of a period other than the horizontal blanking period. CONSTITUTION:A changeover switch 22 selectively leads write reset signals RSTW; read reset signals RSTR, write clocks WCK, read clocks RCK and picture data DATA outputted from a non-interlace signal converter 12 and the RSTW to DATA outputted from a non-display part additional circuit 16 to a field memory 17 by the changeover control of a controller 18. In this case, a clock changeover switch is changeover-controlled so as to supply the clocks WCK of 1440fh to the field memory 17 in the horizontal blanking period and to supply the clocks WCK of 770fh to the field memory 17 in the period other than the horizontal blanking period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for selectively displaying an image signal of an interlace or a non-interlace, and more particularly to a non-interlace of the interlace signal. -Improvement of a memory control circuit for converting to a digital signal.

[0002]

2. Description of the Related Art As is well known, recently, a liquid crystal type image display device capable of selectively displaying an image signal of a video signal output from a personal computer and an ordinary television signal has been available. Has been developed. By the way, generally, a video signal output from a personal computer is a non-interlace signal, and a normal NTSC television signal is an interlace signal. For this reason, in this type of image display device, when displaying a normal television signal as an image, the interlace signal is converted into a non-interlace signal.

FIG. 5 shows such a conventional image display device. Normal television signals are input terminal 11
And is supplied to the non-interlace signal converter 12 via. The non-interlace signal converter 12 is based on the input television signal and outputs image data DATA, a write clock WCK, and a write reset signal RST.
W, read reset signal RSTR, read clock RCK, and liquid crystal panel drive timing signal CONSTV
Is generated and output.

Of these, image data DATA, write clock WCK, write reset signal RSTW, read reset signal RSTR and read clock RCK.
Are respectively supplied to the line memory 13. And
The image data DATA is interleaved by the write / read processing of the line memory 13 based on the write clock WCK, the write reset signal RSTW, the read clock RCK, and the read reset signal RSTR.
From the non-interlaced signal to the non-interlaced signal.

On the other hand, the image signal PCDATA output from a personal computer (not shown), together with the synchronizing signal SYNC taken out from the personal computer, is passed through the input terminals 14 and 15 to the non-display portion described later. It is supplied to the additional circuit 16. This non-display part addition circuit 16
Is based on the image signal PCDATA and the synchronizing signal SYNC, image data DATA, a write clock WCK,
Write reset signal RSTW, read clock RC
K, a read reset signal RSTR, a liquid crystal panel drive control signal CONSPC, etc. are generated. Of these, image data DATA, write clock WCK,
Write reset signal RSTW, read clock RC
The K and the read reset signal RSTR are output to the field memory 17. Then, the image data DATA
Is a write clock WCK and a write reset signal R
Based on STW, the read clock RCK, and the read reset signal RSTR, the data is written into the field memory 17 and then read.

Line memory 13 and field memory 1
The image data DATA output from 7 is selected by the switch 19 which is switch-controlled by the controller 18 based on the input operation of the video mode, and is guided to the liquid crystal panel 20. At this time, the liquid crystal panel drive timing signal CONSTV for the normal television signal output from the non-interlace signal converter 12 and the image signal PCD of the personal computer output from the non-display section addition circuit 16
LCD panel drive timing signal CONSPC for ATA
And a switch 21 which is switch-controlled by the controller 18.
Thus, the image signal PCDATA selectively supplied to the liquid crystal panel 20 and the television signal or the image signal PCDATA output from the personal computer is selectively displayed on the liquid crystal panel 20.

By the way, the liquid crystal panel 20 is composed of, for example, pixels of horizontal 640 dots × vertical 480 dots, but the number of pixels of the image signal PCDATA output from the personal computer is not necessarily 640 × 480. Is not limited to the number of pixels of 640 × 400,640
There are various numbers such as × 350. Therefore, 64
For example, 640 × 35 on the liquid crystal panel 20 of 0 × 480 pixels
Considering the case of displaying the image signal PCDATA of 0 pixel, the image signal PCD to be displayed on the display screen is displayed.
Since the number of pixels of the ATA in the vertical direction is insufficient, it is necessary to generate a portion where no image is displayed on the upper side, the lower side, or both of the liquid crystal panel 20.

In this case, in the liquid crystal panel 20, it is necessary to write "data not to display" in the liquid crystal even in a portion which is not displayed. Therefore, to the image signal PCDATA having a smaller number of pixels than the liquid crystal panel 20, non-signal data is added by the non-display section addition circuit 16 to obtain data corresponding to the number of pixels of the liquid crystal panel 20. I am trying to convert to.

FIG. 6 shows the configuration of the non-interlace signal converter 12. The conversion method of the non-interlace signal converter 12 is a method called simple double swing, and a signal for one horizontal scanning line (line) of the interlace signal is written in the line memory 13. It is converted into a non-interlace signal by reading out at a speed twice as high as the speed at which it was written. The line memory 13 used in this example does not become unreadable because there is no limitation on the relationship between the write address and the read address.

That is, in FIG. 6, the television signal supplied to the terminal 12a is supplied to the sync separator 12b and separated into an image component and a sync signal component. Of these, the synchronization signal component is supplied to the timing generator 12c, and the liquid crystal panel drive timing signal CONSTV and the write reset signal RSTW for the line memory 13 are supplied.
And a read reset signal RSTR. Then, the liquid crystal panel drive timing signal CONST
V is output to the switch 21 via the terminal 12d, and the write reset signal RSTW and the read reset signal RSTR are supplied to the line memory 13 via the terminals 12e and 12f.

Further, in this example, since it is premised that one line of a normal television signal is sampled at 770 samples, if the horizontal synchronizing frequency of the normal television signal is fh, it is given to the line memory 13. The frequency of the write clock is 770 fh, and the frequency of the read clock is 1440 fh, which is double the frequency. Therefore, by supplying the horizontal synchronizing signal output from the timing generator 12c to the 1440fh clock generator 12g, a 1440fh clock is generated and is output to the line memory 13 via the terminal 12h as the read clock RCK. ing. Further, the clock output from the 1440fh clock generator 12g is a divide-by-2 circuit 12i.
Is supplied to the line memory 13 via the terminal 12k as the write clock WCK.

Further, 7 output from the frequency dividing circuit 12i
The 70fh clock is supplied to the A / D (analog / digital) converter 12j. This A / D converter 12j is
The image component separated by the sync separator 12b is digitized by using the 770fh clock output from the divide-by-2 circuit 12i as a sampling clock, and the image data DAT is obtained.
A is output to the line memory 13 via the terminal 12l.

FIG. 7 shows the configuration of the non-display portion addition circuit 16. Here, as an addition of a non-display portion to the liquid crystal panel 20 described above, an image signal of 640 × 350 pixels (total scanning line number 400) PCDATA is 640 ×.
An example of conversion into an image signal of 480 pixels (total number of scanning lines: 500) will be described. That is, the image signal PCD from the personal computer supplied to the terminal 16a.
The ATA is digitized by the A / D converter 16b, and its image data DATA is output to the field memory 17 via the terminal 16c.

Further, the synchronization signal S supplied to the terminal 16d
YNC is supplied to the write clock generator 16e to generate the write clock WCK, and the terminal 16
It is supplied to the field memory 17 via f. Further, the write clock generator 16e generates a sampling clock for digitizing the image signal PCDATA from the personal computer by the A / D converter 16b based on the input synchronizing signal SYNC. There is. The sampling clock given to the A / D converter 16b and the write clock WCK given to the field memory 17 are clocks having a frequency corresponding to the total number of horizontal pixels of the computer. Here, the horizontal frequency is 800 fh.
The clock is assumed.

On the other hand, the synchronization signal S supplied to the terminal 16d
The YNC is supplied to the read clock generator 16g to generate the read clock RCK, and is supplied to the field memory 17 via the terminal 16h. The frequency of the read clock RCK is the write clock WCK.
Is multiplied by the reciprocal of the ratio of the total number of scanning lines. In this case, the frequency of the write clock WCK (800 fh) is 5
The clock is 00/400 times, that is, 1000 fh.

By the above, the image data DATA read from the field memory 17 is compressed by the ratio of the write clock WCK and the read clock RCK (in this case 400/500 = 0. 8
Compressed twice.) Therefore, the signal output from the non-display portion addition circuit 16 is 400 out of the total 500 scanning lines.
Since the image data PCDATA is included in the book portion, non-signal data is added to the remaining 100 scanning line portions. Since the level of this no-signal data is indefinite, the timing generator 1 is based on the output of the synchronization signal SYNC and the read clock generator 16g.
Liquid crystal panel drive timing signal CON generated by 6i
By supplying SPC to the liquid crystal panel 20 via the terminal 16j, the level of no signal data is controlled on the liquid crystal panel 20. Also, the timing generator 1
6i generates a write reset signal RSTW and a read reset signal RSTR once in one field and outputs them to the field memory 17 via terminals 16k and 16l.

By the way, both the line memory 13 and the field memory 17 described above are of the FIFO (first in first out) type, and the difference between the two is only the difference in memory capacity in principle. is there. And
The line memory 13 is used only when a normal television signal is supplied, and the field memory 17 is used only when an image signal PCDATA of the personal computer is supplied. Therefore, since both memories 13 and 17 are not used at the same time, it is considered in principle that the field memory 17 having a large capacity substitutes for the line memory 13 to share the memories.

FIG. 8 shows the operation when the line memory 13 is replaced by the field memory 17 and the interlace signal is converted into the non-interlace signal. In FIG. 8A, the vertical axis indicates the field memory 1
7 shows write and read addresses, and the horizontal axis shows time. The image data DATA is written in the field memory 17 by writing a reset signal RS at the beginning of the effective screen of each scanning line as shown in FIG. 8B.
This is executed by outputting TW and counting the write clock WCK from the write address 0 by the field memory 17. When the writing is started, the write address changes as shown in the characteristic (a) of FIG. 8A, and the image data DATA is changed as shown in FIG. 8C based on the change of the write address. Is written in the field memory 17.

On the other hand, the reading of the image data DATA from the field memory 17 is performed at the beginning of the effective screen of each scanning line and at the intermediate portion of the write reset signal RSTW as shown in FIG.
As shown in (d), the read reset signal RSTR is output, and the field memory 17 is executed by counting the read clock RCK from the read address 0. When the reading is started, the read address changes as shown in the characteristic (b) of FIG.
Based on the transition of the read address, the image data DA
TA is the field memory 17 as shown in FIG.
Is read out at a speed twice as high as that at the time of writing, and the interlace signal is converted into a noninterlace signal there. In FIG. 8A, the memory address 640
From 1 to 770, the horizontal blanking period is set, and it is assumed that no image is displayed during this period.

By the way, in general, the field memory is
Since the access speed of the internal large-capacity RAM (random access memory) is slow, the data is temporarily stored in an internal memory that can be accessed at high speed, and a fixed amount of data is stored in this internal memory.
After the data is stored, the data is stored in blocks in the large capacity RAM.
Data transfer. Therefore, the written data can be read only after a certain number of write cycles (for example, 200 cycles or more in the 2Mbit field memory μPD42280 manufactured by NEC Corporation). That is, the image data DATA written by the write address shown by the characteristic (a) in FIG. 8A cannot be read out in the hatched area (c) in the figure. Therefore, when the read address indicated by the characteristic (b) in FIG. 8A overlaps the area (c) in the figure, the image data DATA of that portion, that is, the shaded portion in FIG. This causes a problem that the image data DATA cannot be read.

[0021]

As described above, in the conventional image display device, the interlace signal is non-interlaced.
It is difficult to substitute a field memory for generating a non-display period as a line memory for converting into a race signal, and there is a problem that the efficiency of the memory cannot be improved.

An object of the present invention is to convert an interlace signal into a non-interlace signal even if a memory which is in a non-readable state until a predetermined time elapses from the time when the written data is written is used. An object of the present invention is to provide a memory control circuit of an image display device capable of performing the above.

[0023]

A memory control circuit of an image display apparatus according to the present invention includes a memory which is in a non-readable state until a predetermined time elapses from the time when the written data is written, and an interface to the memory. Writing means for sequentially writing the lace signal and reading means for converting the interlace signal written in the memory by the writing means into a non-interlace signal by reading at a speed twice as fast as the writing time. It is intended for an image display device provided with.

In the read state of the non-interlace signal from the memory by the reading means, the length of the horizontal blanking period of the non-interlace signal is alternately changed every other line. In the write state of the interlace signal to the memory by the read address control means for controlling the applied read address and the write means, the writing speed of the interlace signal during the horizontal blanking period is set to other than the horizontal blanking period. The write address control means for controlling the write address given to the memory is provided so as to be faster than the write speed during the period.

[0025]

According to the above construction, when the non-interlace signal is read from the memory, the non-interlace signal is read.
The read address given to the memory is controlled so that the length of the horizontal blanking period of the race signal is alternately changed every other line, and the interlace signal is written in the memory while the interface is being written. Since the write address given to the memory is controlled so that the writing speed of the horizontal blanking period of the race signal is higher than the writing speed of the period other than the horizontal blanking period,
The interlace signal can be converted into the non-interlace signal even by using the memory which cannot be read until a predetermined time elapses from the time when the written data is written.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the overall configuration of the image display device described in this embodiment. In FIG. 1, the same parts as those in FIG.
That is, the write reset signal RSTW, the read reset signal RSTR, the write clock WCK, the read clock RCK and the digitized image data DATA output from the non-interlace signal converter 12.
Is supplied to one input side of the changeover switch 22.

On the other hand, the write reset signal RSTW, the read reset signal RSTR, the write clock WCK, the read clock RCK and the digitized image data DATA output from the non-display portion addition circuit 16 are:
It is supplied to the other input side of the changeover switch 22.

The change-over switch 22 is output from the non-display part addition circuit 16 and RSTW, RSTR, WCK, RCK and DATA outputted from the non-interlace signal converter 12 by the change-over control of the controller 18. RST
It operates so as to selectively lead W, RSTR, WCK, RCK and DATA to the field memory 17. Then, the field memory 17 stores the input image data D
ATA is written and read based on the write reset signal RSTW, the read reset signal RSTR, the write clock WCK, and the read clock RCK, and is output to the liquid crystal panel 20.

FIG. 2 shows the case where the field memory 17 is used to convert an interlaced television signal into a non-interlaced signal.
It shows a state in which the read address given to is controlled. Note that FIGS. 2A to 2E are respectively shown in FIG.
To (e), respectively. That is, when the video signal is displayed on the liquid crystal panel 20, it is not necessary to set the horizontal blanking period HBLK in the video signal supplied to the liquid crystal panel 20, so that the image data DATA from the field memory 17 is stored. The horizontal blanking period H of the image data DATA read from the field memory 17 is controlled by controlling the read address.
BLK is alternately controlled line by line as shown in FIG.

That is, as shown in FIG.
The characteristic (b) of the read address that overlaps the unreadable area (c) from the memory 17 is shifted to the right of the characteristic (b) shown in FIG. In this case, the characteristic (b) of the read address that overlaps the area (c) is such that it is returned to 0 when the memory address exceeds 640, that is, when the reading of the horizontal blanking period HBLK is started. Is shifted to. Such control of the characteristic (b) of the read address is shown in FIG.
As shown in (d), this can be realized by changing the generation cycle of the read reset signal RSTR for each line, and as a result, as shown in FIG. 2 (e), only the effective screen is read twice consecutively. It is possible to shorten the period during which the data is issued and cannot be read. However, even if this method is used, the data in the shaded area in FIG. 2 (e) cannot be read.

Therefore, the non-interlace signal converter 12 is improved as shown in FIG. In FIG. 3, the same parts as those of FIG. That is, 1440 fh clock generator 12 g
1440fh read clock RCK output from
And a write clock WCK of 770 fh output from the divide-by-2 circuit 12i.
In this way, it is selectively applied as a write clock to the field memory 17 via the terminal 12k.
The clock changeover switch 12m is a synchronous separator 12b.
The switching control is performed according to the signal HBLKSIG corresponding to the horizontal blanking period HBLK of the image data DATA generated by the timing generator 12c based on the horizontal synchronizing signal separated by.

That is, the field memory 17 has 77
Two types of write clocks W, 0fh and 1440fh
CK is selectively supplied. In this case, the clock changeover switch 12m controls the write clock WCK of 1440 fh during the horizontal blanking period HBLK.
Is controlled to be applied to the field memory 17,
770 fh during periods other than horizontal blanking period HBLK
The write clock WCK is controlled so as to be applied to the field memory 17.

In short, as shown in FIG. 2 (e), the image data DATA written in the field memory 17 during the period in which the data cannot be read is the horizontal blanking as shown in FIG. 2 (c). It is the data of the period HBLK,
Since the address to write the data and the address to read the data do not satisfy a certain relation condition, the data cannot be read. By the way, the horizontal blanking period H
Since the BLK data is not displayed on the liquid crystal panel 20, the frequency of the write clock WCK in the period HBLK should be higher than the frequency of the normal write clock WCK within the operating range of the field memory 17. As a result, the write address can be advanced rapidly, and the influence of the write address in the horizontal blanking period HBLK can be eliminated.

That is, the field memory 17 is based on the signal HBLKSIG from the timing generator 12c.
If the image data DATA supplied to the clock is a valid screen period, the clock has a frequency of 770 fh, and if it is a horizontal blanking period HBLK, the frequency is 1440 f.
The speed of the write address is controlled by selecting the write clock WCK with the clock changeover switch 12m so that it becomes the clock of h.

In this case, the transition of the write address is changed by the signal HBLK indicating the horizontal blanking period HBLK shown in FIG. 4 (f), as shown in the characteristic (a) of FIG. 4 (a).
During the H (high) level period of SIG, it is controlled so as to have the same slope as that of the read address characteristic (B). On the other hand, the transition of the read address is shown by the characteristic (B) as in FIG. 2A, so that it does not overlap with the area (C) and the field memory 1
Among the image data DATA written in 7, the data of the effective screen portion to be displayed on the liquid crystal panel 20 can be all read out.

Therefore, according to the configuration as in the above embodiment, the effective address portion of the image data DATA written in the field memory 17 is controlled by controlling the write address and the read address for the field memory 17, respectively. Since I made it possible to read all
The field memory 17 can be used to perform non-interlace conversion of a television signal for screen display on the liquid crystal panel 20, and the field memory 17 can be used for the line memory 13 for interlace conversion. Can be substituted.

[0037]

As described above in detail, according to the present invention,
An image display device capable of converting an interlace signal into a non-interlace signal even if a memory which is in a non-readable state until a predetermined time has elapsed from the time when the written data is written is used. A memory control circuit can be provided.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a memory control circuit of an image display device according to the present invention.

FIG. 2 is a diagram for explaining a control operation of a read address of the field memory in the embodiment.

FIG. 3 is a block configuration diagram showing a detailed configuration of a non-interlace signal converter in the embodiment.

FIG. 4 is a diagram for explaining the control operation of the write address of the field memory in the embodiment.

FIG. 5 is a block configuration diagram showing a conventional image display device.

FIG. 6 is a block configuration diagram showing a detailed configuration of a non-interlace signal converter in the conventional apparatus.

FIG. 7 is a block configuration diagram showing a detailed configuration of a non-display portion addition circuit in the conventional device.

FIG. 8 is a diagram for explaining the interface conversion operation of the field memory in the conventional device.

[Explanation of symbols]

11 ... Input terminal, 12 ... Non-interlace signal converter, 12a ... Terminal, 12b ... Sync separator, 12c ... Timing generator, 12d ... Terminal, 12e ... Terminal, 12f ...
Terminal, 12g ... 1440fh Clock generator, 12h ...
Terminal, 12i ... 2 frequency divider circuit, 12j ... A / D converter, 1
2k ... terminal, 12l ... terminal, 12m ... clock changeover switch, 13 ... line memory, 14 ... input terminal, 15 ... input terminal, 16 ... non-display section additional circuit, 16a ... terminal, 16
b ... A / D converter, 16c ... terminal, 16d ... terminal, 16
e ... Write clock generator, 16f ... Terminal, 16g ...
Read clock generator, 16h ... Terminal, 16i ... Timing generator, 16j ... Terminal, 16k ... Terminal, 16l ...
Terminal, 17 ... Field memory, 18 ... Controller, 19 ...
Switch, 20 ... Liquid crystal panel, 21 ... Switch, 22 ...
Changeover switch.

Claims (2)

[Claims] 1. A memory which is in a non-readable state until a predetermined time elapses from a time when the written data is written, a writing means for sequentially writing an interlace signal to the memory, and the memory by the writing means. In the image display device having a reading means for converting the interlace signal written in the above into a non-interlace signal by reading it at a speed twice as fast as the writing time, In the read state of the non-interlace signal, the read address for controlling the read address given to the memory so that the length of the horizontal blanking period of the non-interlace signal is alternately changed every other line. In the writing state of the interface signal to the memory by the control means and the writing means, the interface is written. A write address control means for controlling the write address given to the memory so that the write speed of the horizontal signal during the horizontal blanking period is faster than the write speed during the period other than the horizontal blanking period. A memory control circuit of a featured image display device. 2. The write address control means sets the writing speed of the interlace signal to the memory during a horizontal blanking period, and the read means reads the non-interlace signal from the memory. The memory control circuit of the image display device according to claim 1, wherein the memory control circuit is configured to be substantially equal to the speed.