JPH0230517B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for synthesizing video display signals, and more particularly to a method for synthesizing video display signals that combines both a background signal and a foreground signal.

Prior Art Conventionally, a signal synthesis method is well known in which a plurality of images are synthesized and displayed on a CRT. For example, as shown in FIG. 1, a foreground 110 representing a vehicle is superimposed on a background 100 representing a road. Since the video 120 obtained by combining the two can be displayed on a CRT, it is widely used in various video devices.

Such video composition is performed by combining the horizontal scanning signal components of the background 100 and foreground 110 in synchronization with the raster scanning of the CRT.

FIG. 2 shows a conventional signal synthesis device that synthesizes such signals, and this signal synthesis device includes a line buffer memory 10 and a synthesis circuit 12.
is used to transfer the foreground signal to line buffer memory 1.
The foreground signal stored in the line buffer memory 10 is read out and sent to the synthesis circuit 12.
The signal is combined with the background signal.

Here, the line buffer memory 10
is a high-speed memory that stores one horizontal scanning signal component for the foreground of the CRT, and as shown in FIG. 3, it has addresses from 0 to n that correspond to the horizontal pixels of the CRT used. FIG. 4 shows the write/read operation of the conventional line buffer memory 10, in which the foreground signal input when the write section signal is in the "H" state is transferred to a predetermined location corresponding to the display position of the CRT.
For example, it is written to an address in the range of k to k+2 (a).

The predetermined writing is completed by the time the write interval signal switches to "L", and after that the line buffer memory 10
The reading of is started, but at this time the multiplexer 16 switches its output from the foreground signal at the time of writing to the erase signal. Therefore, the information written as described above is read out in order to be combined with the background signal in the combining circuit 12. This reading is performed in order of address 0, address 1, address 2, etc. from the smallest number (b).

Once the information is read in this way, the read information is no longer needed, so an erase signal is written to each address via the multiplexer 16 in accordance with the signal erase timing c shown in FIG. The information written first is cleared sequentially. In FIG. 4, a represents the foreground signal write time, b represents the foreground signal read time, and c represents the erase signal write time.

The information thus read out from the line buffer memory 10 is latched one address at a time by the latch circuit 18, and then outputted to the synthesis circuit 12 as a foreground signal.

This synthesis circuit 12 generally includes a video detection circuit 20 that detects whether or not a foreground signal is output from the latch circuit 18, and selectively outputs an input of a foreground signal or a background signal according to instructions from this video detection circuit 20. It is formed by a multiplexer 22. Both the background signal and the foreground signal output from the latch circuit 18 are input to the multiplexer 22, and normally the background signal is selectively output, and the video detection circuit 20 receives the foreground signal from the latch circuit 18. Only when the output is detected, the foreground signal is selectively output instead of the background signal. In this way, the synthesis circuit 12 synthesizes a video signal in which the foreground signal is superimposed on the background signal, and outputs the synthesized video signal to the signal processing circuit 24.

Therefore, by using such a device, for example, a background 100 representing a roadway as shown in FIG. When input to the multiplexer 16, both signals are sequentially combined in synchronization with raster scanning of the CRT, and an image 120 representing a vehicle traveling on a road can be displayed on the CRT.

However, such conventional devices have the disadvantage that many circuits are required for signal synthesis, making the entire device complex and expensive.

OBJECT OF THE INVENTION The present invention has been made in view of such conventional problems, and its purpose is to provide a video display signal that can synthesize both a background signal and a foreground signal using a simple and inexpensive device. The object of the present invention is to provide a method for synthesizing.

Structure of the Invention In order to achieve the above object, the method of the present invention reads video information including a background signal and a foreground signal written in each address of a line buffer memory and outputs it as a video display signal. a video information reading and background writing step in which the line buffer memory is accessed while sequentially writing the background signal of the background to be displayed next; and a foreground writing step in which a predetermined foreground signal is written to each required address in the line buffer memory. The method is characterized in that it includes the steps of: and is capable of synthesizing both background and foreground signals within a line buffer memory.

Embodiments Next, preferred embodiments of the present invention will be described based on the drawings. Incidentally, members corresponding to those of the conventional example shown in FIG. 2 are given the same reference numerals, and their explanations will be omitted.

FIG. 5 shows a preferred embodiment of an apparatus to which the video display signal synthesis method of the present invention is applied.

In this device, a background signal or a foreground signal is selected by a multiplexer 16 according to a predetermined timing chart and sent to a line buffer memory 1.
0 and is sequentially written as video information at a predetermined address designated by the address counter 14.

In this way, the video information written in the line buffer memory 10 is read out when the read operation starts, and is latched by the latch circuit 18 in order from the address with the smallest number in synchronization with the raster image scanning of the CRT, and the video information is displayed. The signal is input to the signal processing circuit 24 as a signal. In this way, the signal input to the signal processing circuit 24 is subjected to predetermined video processing,
Displayed on CRT.

The apparatus of this embodiment has the above-mentioned configuration. Next, a method of synthesizing video display signals according to the present invention using this apparatus will be described.

A feature of the present invention is that both the background signal and the foreground signal can be synthesized within the line buffer memory 10.

Therefore, in the present invention, the background signal and foreground signal are written into the line buffer memory 10 according to the following procedure.

That is, writing of the background signal involves reading the video information including the background signal and foreground signal already written to each address of the line buffer memory 10 and outputting it as a video display signal, and also writing the next horizontal scan for each address. The video information reading and background writing process of the line buffer memory 10 is performed while sequentially writing background signals to be displayed in the line buffer memory 10.

After the video information reading and background writing steps are completed, writing of the foreground signal is performed in a foreground writing step in which a predetermined foreground signal is written at each necessary address of the line buffer memory 10 to be superimposed on the video information. will be carried out.

Therefore, by sequentially repeating the video information reading and background writing process and the foreground writing process as described above, the foreground signal is superimposed and synthesized on the background signal in the line buffer memory 10. Video information is sequentially written, and the video information is sequentially read out in the next video information and read background writing process, and a video with the background and foreground combined is displayed on the CRT.

FIG. 6 shows a timing chart showing one embodiment of the method of the present invention. In the same figure,
a is foreground signal writing time, d is composite signal reading time,
e represents the background signal writing time.

First, in the video information reading and background writing process, the multiplexer 16 is
The background signal is selected in line buffer memory 1.
It is input to 0. At the same time, the address counter 14 is reset and the line buffer memory 10 is reset.
The addresses are designated sequentially from the smallest number to the nth address, such as address 0, address 1, address 2, and so on.

When an address in the line buffer memory 10 is designated by the address counter 14 in this way, the video information that has already been written is read out from the designated address in the first half d of one cycle for each address, and the video display signal is At the same time as the reading of this video information ends, the second half of one cycle e
, the background signal input via the multiplexer 16 is written to the specified address.

In this embodiment, the line buffer memory 10 is moved from address 0 to
The video information is read out and the background is written toward the address n, and the video information reading and background writing process is completed when the access to the n address is completed. Therefore, when this video information reading and background writing process is completed, a background signal as shown in FIG. 7, for example, is stored as video information at each address of the line buffer memory 10.

When this video information reading and background writing process is completed, a foreground writing process is simultaneously started.

In the embodiment, the specimen writing interval signal is “H”
At this time, the foreground writing process is started, and at the same time, the multiplexer 16 switches and inputs the foreground signal to the line buffer memory 10, and the address counter 14 specifies the write address of the foreground signal. As a result, the foreground signal is written and stored in each address designated by the address counter 14, superimposed on the background signal. Address setting of the address counter 14 is performed using horizontal position data.

Therefore, as shown in FIG. 7, for example, when the address counter 14 designates addresses k to k+4 as the write addresses for the foreground signal, the newly input foreground signal is stored as video information at each of these addresses. The data will be written and stored sequentially as follows.

In this way, when the writing process is completed,
The information stored in each address of the line buffer memory 10 is information obtained by combining both the background signal and the foreground signal.

Therefore, according to the display signal synthesis method of the present invention, if the background 100 representing a road, etc. is input to the multiplexer 16 as a background signal, and the foreground 110 representing a vehicle is input to the multiplexer 16 as a foreground signal, These background and foreground signals are combined in the line buffer memory 10, and the background 100 and foreground 110 signals are displayed on the CRT.
A composite image 120, that is, an image of a vehicle represented in the foreground 110 driving on a road depicted in the foreground 100 can be displayed on a CRT.

As described above, according to the method of synthesizing video display signals of the present invention, both the background and foreground signals can be synthesized within the line buffer memory 10, which is different from that used in the conventional device shown in FIG. This eliminates the need for the synthesizer circuit 12, making it possible to synthesize signals using a simple and inexpensive device.

Note that the present invention also includes the case where the background signal is no signal, and in this case, the background signal and the foreground signal are not actually superimposed, and the predetermined foreground signal is simply transferred to each necessary line buffer memory. A video display signal can be created by simply writing to an address and reading it. For example, the background signal does not cover the entire display screen, and the foreground signal is inserted into this empty area (no signal area), or the foreground signal is inserted into the empty area (no signal) by leaving only the area corresponding to the foreground signal in the background signal empty (no signal). In this way, even when the background signal and foreground signal are not superimposed in screen creation, the compositing method of the present invention can be applied.

Next, a specific embodiment to which the video display signal synthesis method of the present invention is applied will be described.

Example 1 The device of this example synthesizes a foreground consisting of a plurality of moving objects as shown in FIG. 9 on a background as shown in FIG. 8, and creates a game image as shown in FIG. 10. It is something that is synthesized.

FIG. 11 shows a video display circuit of this embodiment that performs such video synthesis.

In the device of the embodiment, the video information reading and background writing steps are performed in accordance with the horizontal scanning period of the CRT, and a background signal representing the background shown in FIG. 8 is input from the background signal output circuit 30 to the multiplexer 16, and The foreground writing process is performed in accordance with the horizontal blanking period of FIG.
I am typing for 6.

Here, the foreground used in the device of the embodiment represents a plurality of moving specimens that make up the game, and the type, number, and display position of each of these moving specimens changes at any time as the game progresses. It is something.

On the other hand, the content of the background used in the apparatus of the embodiment has already been determined, and the background matching the foreground described above is stored in the background memory 31, and the background is set in accordance with the timing of CRT scanning. It is output via the signal output circuit 30.

Hereinafter, the circuit used in the example will be described in detail.

(1) Setting information in the specimen memory When displaying a game image on a CRT that combines a predetermined background and foreground, the foreground information,
In other words, it is necessary to set information representing the moving object.

In the apparatus of the embodiment, a predetermined program set in advance is stored in the program memory 36. Then, based on a predetermined program signal outputted from the program memory 36 and an external input signal _S1 inputted from the outside by the video game player, the CPU 34 controls the moving target to be played by one or more players. It also calculates and outputs data regarding the moving target that is automatically controlled by the program. This data consists of four data for each specimen: specimen identification data for specifying the specimen, color identification data for specifying the color, vertical position data and horizontal position data for specifying the display position.

Then, the CPU 34 transfers the four types of data regarding each of the specimens 1 to n to the data bus 3 based on the input signal _S1 from the player or the program signal from the program memory 36.
All the specimens constituting one screen are written and stored in the specimen memory 40 via the address bus 8a and the address bus 38b.

This writing is started by outputting a write signal _S2 from the CPU 34 to the switch 42 at the start of writing to the sample memory 40, and causing the switch 42 to select an address on the CPU 34 side. Then, by the switch 42 like this
When the address output from the CPU 34 is selected, data is stored in the specimen memory 40 for each specimen, that is, for each specimen 1, specimen 2, ... specimen n, according to the write address output from the CPU 34. Written and stored.

(2) Writing the background signal to the line buffer memory As mentioned above, when the video information representing the moving target is set in the line buffer memory 10 and the target writing section signal becomes "L", the video information The read and background write process begins.

That is, when the sample writing interval signal changes to "L" and horizontal scanning of the CRT starts, at the same time, the address counter 14 is reset by a reset signal output from the synchronization signal generation circuit 46, which will be described later, and the line batch is reset. Hua Memory 10
The address is designated sequentially from address 0 to address n, such as address 0, address 1, address 2, and so on. When each address of the line buffer memory 10 is designated in this way, the video information that has already been written is read out from each designated address, and at the same time, the video information is read out from the background signal output circuit 30 via the multiplexer 16. The background signal to be displayed next is written to the specified address. The video information read out from the line buffer memory 10 is then latched by the latch circuit 18 as a video display signal.
It is output to the signal processing circuit.

Since such video information reading and background writing are performed for each address from address 0 to address n of the line buffer memory 10, the image information consists of the background and foreground stored at each address of the line buffer memory 10. The video information for one scanning line is displayed as a raster image on the CRT, and at the same time, a background signal to be displayed next, which is output from the background signal output circuit 30, is written and stored in each address of the line buffer memory 10. That will happen.

(3) Writing the foreground signal to the line buffer memory As mentioned above, the line buffer memory 10
When the foreground signal is written in the line buffer memory 1 and the specimen writing interval signal becomes "H", the line buffer memory 1
The foreground write process for 0 is performed in conjunction with the horizontal blanking period of the CRT. That is, the foreground signal is written to the required address of the previously written background.

In the device of the embodiment, a synchronizing signal generating circuit 46 is provided in order to perform writing or reading into each memory incorporated in such a device and other overall control. are clock k, preset signal, reset signal,
Specimen writing period signal, etc. In addition, synchronization signals (vertical and horizontal synchronization signals) corresponding to signals associated with normal color television video display, erasure signal E,
A composite blanking signal B and a composite synchronization signal C are output.

Then, as described above, when writing of the data of specimen 1 to specimen n to the specimen memory 40 is completed,
The write signal _S2 inputted from the CPU 34 to the switch 42 is turned off, and the switch 42 selects the read address outputted from the synchronization signal generation circuit 46.

In this way, the switch 42 selects the write address on the CPU side when the write signal S ₂ is input from the CPU 34, and selects the write address on the CPU side when the write signal S ₂ from the CPU 34 is turned off. The read address outputted from 46 is selected and input into the specimen memory 40. The writing or reading addresses of this specimen memory 40 correspond to specimen identification numbers 1 to n in any case.

In this way, in the embodiment, n is stored in the sample memory 40.
Data regarding n moving objects are stored, and it is possible to display n moving objects on the CRT. Here, the specimen memory 4
To read out each of the specimens 1 to n stored in 0, the vertical position data D ₁ , specimen identification data D ₂ , colored identification data D ₃ , and horizontal position data D ₄ regarding specimen 1 are first read out in sequence. , next, the data regarding specimen 2, specimen 3, ... specimen n are sequentially read out in the same way, and the specimen signal output circuit 3
2 is input.

Here, this specimen signal output circuit 32
Next, it is determined whether or not the object can be displayed based on the vertical position data _D1 of the object and the vertical synchronization signal output from the synchronization signal generation circuit 46, and if it is determined that the object can be displayed, the object is displayed. output signal to the line buffer memory 10. At the same time, the data of the object is sent to the line buffer memory 10 via the multiplexer 16 as a foreground signal.
is input and written into the predetermined address preset in the address counter 14 by the vertical position data _D4 .

Further, when the object signal output circuit 32 determines that the object cannot be displayed, it does not output the object writing signal and moves on to determining whether the next object can be displayed.

The above is for the first specimen, specimen memory 4
These operations are from reading 0 to writing the foreground signal into the line buffer memory 10. In the device of the embodiment, these operations are continued to write the horizontal return of the CRT for the second to nth samples. This is repeated within the line erasing period. At this time, if the foreground signal of the second or later object overlaps with the foreground signal of the object previously written in the line buffer memory 10, the subsequent signal is first applied to the line buffer memory 10. It is written superimposed on the foreground signal written in the foreground memory 10. In this writing, only the effective color part of the foreground signal is written,
No writing is done in transparent areas.

(4) Completion of display signal synthesis As described above, the background signal shown in FIG. 8 output from the background signal output circuit 30 is transferred to the line buffer memory 1 in the video information reading and background writing process
The background is written in 0, and then the foreground signal shown in FIG. Both the background and foreground signals are combined in the line buffer memory 10.

(5) Reading video information from the line buffer memory In this way, the line buffer memory 10
When the signals within the range are synthesized and the specimen writing interval signal changes from "H" to "L", the next video information reading and background writing process starts and the video information that has already been written is read out. Writing of a new background starts.

Here, the reading of video information from the line buffer memory 10 is carried out by the synchronization signal generation circuit 46.
After the address counter 14 is reset by a reset signal outputted from the address counter 14, the resetting is performed for each address in synchronization with the clock K in order from the address with the smallest number to address 0, address 1, . . . to address n.
Then, the read information is transferred to the single latch circuit 18.
After being latched, the signal is input to the signal processing circuit 24 as a video display signal.

In the embodiment, the information read out in this manner is represented by colors in hexadecimal notation from $0 to $F. For this reason, the signal processing circuit 24 of the embodiment has a color ROM 24a into which color information corresponding to these hexadecimal notations is inputted in advance, and the color information corresponding to these hexadecimal notations is input based on the signal input from the latch circuit 18. color signal
Read from ROM24a, DA conversion circuit 24b
input to CRT via.

As a result, the color image shown in FIG. 10, in which the background shown in FIG. 8 and the foreground shown in FIG. 9 are combined, is displayed on the CRT.

In addition, in the video information reading and background writing process in which composite information of background and foreground signals is read from the line buffer memory 10 in this manner, the background signal for the next scan output from the background signal output circuit 30 is is line buffer memory 1
0 is written at the same time.

In the embodiment shown in FIG. 11, the address counter 14 and the line buffer memory 1
Since only one set of 0 is provided, the foreground writing process for writing the foreground signal into the line buffer memory 10 is limited to the horizontal blanking period of the CRT.

Since the horizontal blanking period of the CRT is relatively short, the data regarding the moving object that can be written and stored in the line buffer memory 10 during this horizontal blanking period is also relatively limited. As a result, only the number of moving objects limited by the horizontal blanking period can be displayed on the CRT.

To solve this problem, at least two sets of line buffer memories and address counters are provided, and the video information reading process and the background writing process and foreground writing process for each set of line buffer memories are performed using the sample writing period signal. This can be solved by synchronously switching alternately, and a preferred embodiment thereof will be described below.

Embodiment 2 FIG. 12 shows a preferred embodiment to which the video display signal synthesis method according to the present invention is applied, and FIGS. 13 and 14 show timing charts thereof. In Figure 13, 0S, 1
S, 2S, 3S, ... are the horizontal scanning periods, and 1
B, 2B, 3B, . . . indicate horizontal blanking periods.

The apparatus of the embodiment is provided with two sets of address counters 14 and line buffer memories 10, and the video information reading and background writing process and foreground writing process for each set of line buffer memories 10 are shown in FIG.
Switching is performed alternately by the switching signal P, whereby the video information reading and background writing process for one set of line buffer memories 10 and the foreground writing process for the other set of line buffer memories 10 are performed at least within the horizontal scanning period of the CRT. This makes it possible to perform the writing process at the same time.

Therefore, according to the device of this embodiment, writing of the foreground signal is more efficient than in the device of the previous embodiment in which writing of the background signal to the line buffer memory 10 is limited to the horizontal blanking period of the CRT. The amount of information written to the line buffer memory 10 in one foreground writing operation can be reduced by the amount of time required for the relatively long horizontal scanning period compared to the horizontal blanking period. It is possible to display a large number of moving objects on a CRT compared to conventional devices.

Here, in the apparatus of the embodiment, since the line buffer memories 10A and 10B are used alternately, multiplexers 16A and 16 for input selection are provided at the input stage of each line buffer memory 10A and 10B.
B, and a multiplexer 62 is provided at the output stage thereof.

Each of these multiplexers 16A, 16B, 62
The input/output terminal is alternately switched to the line buffer memory 10A side and the line buffer memory 10B side in accordance with the switching signal P outputted from the synchronization signal generation circuit 46 in synchronization with the horizontal scanning of the CRT. It's getting old.

Therefore, as shown in FIG. 13, in the apparatus of this embodiment, when the video information reading and background writing steps are performed on the line buffer memory 10A,
If the foreground writing process is being performed on another set of line buffer memories 10B, and conversely, the video information reading and background writing process is being performed on the line buffer memory 10B, the other line A foreground writing process will be performed on the buffer memory 10A.

The above steps can be changed using the address counter 70.
This is done by a preset switch 72 and a reset switch 74 that switch between preset and reset of A and 70B.

In this way, in the apparatus of this embodiment, the foreground writing process to the line buffer memory 10B can be performed with sufficient time margin, so that many moving objects can be written in one foreground writing process. It becomes possible to write.

In the apparatus of the first embodiment, the background is fixed, but in the apparatus of the second embodiment, a program is set in the program memory 36 to output a background signal according to instructions from the CPU 34, and the background is fixed according to the program. A background data signal and an address signal are input into the memory 31 .
Therefore, in the apparatus of this embodiment, a desired background can be displayed on the CRT, either corresponding to the foreground or independent of the foreground.

Note that in both the first and second embodiments, a moving object in a video game is synthesized with a background signal as a foreground signal, but the method of synthesizing a video display signal of the present invention is not limited to this. It can be widely used to synthesize various background and foreground signals.

Effects of the Invention As explained above, according to the method of the present invention,
Since both the background and foreground signals can be combined within the line buffer memory, the device used for combining the background and foreground signals can have a simple configuration and be inexpensive.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of images to be synthesized, FIG. 2 is a circuit diagram of a conventional video display signal synthesis device, FIG. 3 is an explanatory diagram of a line buffer memory used in the device shown in FIG. 4 is a timing chart of the conventional device shown in FIG. 2, FIG. 5 is a circuit diagram showing a preferred embodiment of the device to which the video display signal synthesis method of the present invention is applied, and FIG. 6 is a timing chart of the conventional device shown in FIG. FIG. 7 is an explanatory diagram of the line buffer memory 10 shown in FIG.
Figure 0 is an explanatory diagram of a video that is a composite of Figures 8 and 9, Figure 11 is a circuit diagram showing an apparatus in which the method of the present invention is applied to a video game, and Figure 12 is an illustration of a video game in which the method of the present invention is applied to a video game. FIGS. 13 and 14, which are circuit diagrams showing other devices applied to the game, are timing charts of the device shown in FIG. 12. DESCRIPTION OF SYMBOLS 10... Line buffer memory, 30... Background signal output circuit, 32... Foreground signal output circuit, 100... Background, 110... Foreground, 120... Combined video.

Claims (1)

[Scope of Claims] 1. The video information including the background signal and foreground signal written in each address of the line buffer memory is read out and output as a video display signal, and the line buffer memory is read out and outputted as a video display signal, while sequentially writing the background signal for each address. A video information reading and background writing step for accessing the buffer memory; and a foreground writing step for writing a predetermined foreground signal to each necessary address of the line buffer memory. A method for synthesizing video display signals, characterized in that both foreground signals can be synthesized. 2. The method according to claim 1, characterized in that a plurality of line buffer memories are used, and the reading of video information to each line buffer memory and the background writing step and foreground writing step are performed alternately. A method for synthesizing video display signals.