JPH0213396B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television image digital memory device, and in particular to an image memory device using dynamic memory.

Television image digital memory devices that use large-capacity dynamic MOS memory are used in a variety of applications, but as is well known, dynamic MOS memory is volatile and requires refreshing (RAM) (Random Access Memory).
It is. These dynamic RAMs use a number of bits as refresh addresses for refreshing, and data is retained by specifying all the refresh addresses at least once within the refresh time. For example, in the case of 16K bits, addressing is performed using 7 bits of the ROW address and 7 bits of the COLUMN address as shown in FIG. 1, and the ROW address is the refresh address. In order to use this memory most easily and effectively, the address counter counts up sequentially from the lower address (address with higher frequency), and if the 7 bits of the lower address are within the refresh cycle, this address is ROW. Refreshing can be performed by giving it to the address. Furthermore, in cases where not all ROW addresses can be specified within a refresh cycle, there is a method in which a special refresh time is provided and refresh is performed during that time.

Conventionally, an example of a memory device using this type of dynamic memory is a still image transmission device.
Figure 2 shows the memory block for NTSC. In Figure 2, A/D conversion is performed at a frequency approximately three times the burst frequency of the input television image signal.
PCM parallel 8-bit data 1 is written to memory input register 2. The information in the memory input register 2 is specified by the write address counter in the address counter 4, which clocks the memory 3 at a frequency fs that is approximately three times the input burst frequency and generates an address synchronized with the synchronization signal of the input signal. written to the address.
In this way, one field's worth of information is written into the memory 3. The data written to the memory 3 is read from the address specified by the read address counter in the address counter 4 and written to the memory output register 5. The data in the memory output register 5 is output as 1 word 8-bit parallel data.
After being D/A converted, it becomes an output image signal.

Now, 1 field television signal 262.5
The minimum memory capacity required to store data of 256 scanning lines and 672 samples per scanning line is 1.376256 Mbits (256 x 672
×8). If we write this information to a 16K x 1 bit memory element, the number of elements is
1.376.256÷16.384≒84 memories should be used. Here, the data written to memory 3 is 1
Since it is 8 bit parallel per sample, 84÷8
It can be divided into memory groups of ≒11 blocks. Here, we added one block for the sake of speed of writing to memory and ease of memory control.
There are 12 blocks, and these are divided into two groups of 6 blocks each, A and B. It is also assumed that the memory input register 2 is divided into two sets, A and B, each consisting of six registers. A/D converted
PCM 8-bit data is first sequentially written to memory input registers 2 of group A, and then while writing to memory input register 2 of group B,
It is written from the memory input register 2 of the set to the same address of the memory 3 of the A set. Furthermore, while data is being written to the memory input register 2 of group A, data is written from the memory input register 2 of group B to the same address in the memory 3 of group B. That is, 12 pieces of sampled PCM data are written to the same address in the memory 3, and when this writing is completed, the memory address counter 4 operates to change by one. The configuration of the address counter in this case is shown in FIG. In FIG. 3, 101 is a 1/12 counter, which controls selection of memory input register 2, reading and writing of memory 3, etc. 1
02 is the H counter, which counts up to 56 (672÷12=56). 103 is a V counter that counts up to 262. counter 1
The output of 02 and 103 becomes the memory address as is, and when the V counter 103 is 256 or more,
That is, if writing to and reading from memory is not performed when A14 is 1, the address information is 6 bits for the H address and 8 bits for the V address.
There are 14 bits in total, and the 6 bits of the H address and the lower 1 bit of the V address are ROW.
A ₇ of the V address given to the memory as an address
Give the 7 bits from ~ _A13 as the COLUMN address. FIG. 4 shows the area written into one memory element when addressing is performed using such H, V addressing method. Fourth
In the figure, the COLUMN address is 0 in the area
0H and 1H data are written, then
The COLUMN address changes by one, and the 2nd and 3rd H are written sequentially, and the COLUMN address becomes 127.
This shows how the 254th and 255th H are written when . Also, the oblique portion indicates a portion that is not addressed. In this way, addressing can be easily performed using the H, V addressing method.

However, as shown in Figure 5, one screen is divided into four,
Each of the four input image signals is halved in both the horizontal and vertical directions, so that the first input signal is the part C in FIG. 5, the second input signal is D, the third is E, and the fourth is
When writing into the F part, the configuration of the memory address counter is as shown in FIG.
A ₀ is used to control the memory input register, A ₁ to _{A 5} and V counter 103.
Give A ₆ and A ₇ as ROW addresses, and A ₈ to _{A 14}
is given as the COLUMN address, and a write command is given only when A ₆ is “0”, and A ₁₄ is “1”.
In this case, unless a write command is sent, an image reduced in size to 1/2 both horizontally and vertically can be written in the portion C in FIG. 5. Similarly, to write to part D, give "1" as the ROW address instead of _A6 , send a write command to the memory only when _A6 is "0", and send a write command to the memory when _A14 is "1". If a write command is not sent, it is possible to write to portion D in FIG. Also, in order to write to parts E and F, enter “1” in COLUMN instead of A ₁₄ .
If you give it as an address and perform the same operation as above, you can write to E and F in the same way. FIG. 6 shows the area of memory used at this time.
R ₁ part is the part where the image of C is written, similarly
The _R2 part was the part where the image of D was written, the _R3 part was the part where the E image, and the _R4 part was the part where the F image was written.

If the screen is always divided into 4 parts and the screen is divided into 4 parts, one
This is not a problem because the ROW address of the part being written is specified, but horizontally,
If we write all the information in both the vertical direction (that is, use memory as shown in Figure 4) and then write and display image signals at other times in part C shown in Figure 5, then When writing, as shown in Figure 6, the ROW address 28
~31 and 92~95 are not specified. This unspecified time is the time for one field and is approximately
It is 16.6msec. This exceeds the refresh cycle of normal 16K-bit dynamic memory (usually about 2 msec), so the ROW address of the first image written is 28-31, 92-
The image written in the 95 part will be destroyed. Also, when reading, as shown in Figure 4,
The ROW address specifies only 0 to 55 and 64 to 119, so 56 to 5 of the ROW address
9 and 120 to 123 are not specified. As a result, a part of the image drawn at part C in FIG. 5 is not refreshed and is destroyed.

Therefore, an object of the present invention is to solve the memory refresh condition by disassembling and counting the H address and changing the order of the addresses even in the H and V address counter method in which the address counter counts up sequentially as described above. It is an object of the present invention to provide a memory device capable of performing four divisions while satisfying the following. In other words, if all addresses are not always used, refresh is performed by giving addresses that are always used in the refresh cycle to the refresh address, and giving addresses and upper addresses that are not always used to other addresses. Can be done.

Next, one embodiment of the present invention is shown in FIG. 7, and the present invention will be explained in detail with reference to FIG. Figure 7 is the second
This is a portion corresponding to the address counter 4 in the figure. In FIG. 7, 201 is a 1/12 counter, which is used as a memory input/output register and to control writing and reading from the memory. 202 and 203 are H address counters, 202 counts from 0 to 27, and 203 is a 1/2 counter. i.e. 201, 20
2 and 203 constitute a horizontal counter. 205 is a counter that counts up with the output of _A0 and counts in H cycles, and 204 is a V address counter that counts from 0 to 261. 20
6 to 211 are selectors, and 206 to 210
can be switched depending on whether all the image signals of one field are stored in the memory or divided into four and each of the four input signals is stored in each position as shown in Fig. 5. 206 and 207 are ROW
An address selector 208 is a COLUMN address selector 209, 210 is a selector for specifying the position of four divisions. 211 is a selector for the ROW address COLUMN address given to the memory.

If you want to store the image signal of one field in memory without compressing it, selector 206~
The G ₁ to G ₃ side of the input to 208 is selected and provided to selector 211 . The selector 211 is
The _G6 side is the ROW address input, the _H6 side is the COLUMN address input, and the time-divided ROW,
COLUMN address is given to memory for addressing. Also, when _A14 is "1", writing to memory is not performed. The state of the memory element at this time is shown in FIG. As shown in Figure 7, assign H addresses A ₄ and A ₅ to the COLUMN address,
Since A ₆ to _{A 8} of the V address are given to the ROW address, as shown in Figure 8, when the address advances from 0 to 15 of the ROW address in the 1st H, the COLUMN address changes by 1 and the ROW address of 0 changes. ~10, and when _A5 becomes “1”, the COLUMN address changes by 1 and becomes 2, and the ROW address 0 to 16,
When A ₄ and A ₅ both become 1, the COLUMN address becomes 3, progresses from ROW address 0 to 10, the writing ends in the 1st H, and A ₆ becomes "1" in the 2nd H, so the ROW address Since the 5th bit of the ROW address is “1”,
1 is selected. Similarly, A ₆ ~ of V address
Since _A8 is the upper bit of the ROW address,
Continue writing 1H for every 16 ROW addresses, 8H
The reason is that all addresses in the ROW address are specified. Also, in the 9th H, the ROW address is 0~
16. COLUMN addresses are written to 4-7. From the above operation, the ROW address is always specified once every 8H, and this time is 63.5μs × 8≒
Since it is 508 μsec, the ROW address is sufficiently specified within the refresh cycle.

Next, when writing the image signal of one field to the position C shown in FIG.
A ₀ controls memory input/output registers and memory read/write.
A ₁ to A ₃ and counter 20 as ROW address
If outputs A ₄ ' and ₇ to A ₉ of 5 are given, and a write command is given only when A ₆ is 0, the even number H of the input signal will be written, and if a write command is given when A ₆ is 1,
Odd number H is written. Next, as the COLUMN address, _A5 ' is given to the least significant bit, and selectors 209 and 21 are given to the second and most significant bit.
0 is given, and then A ₁₀ to _{A 13} are given. Here, the selectors 209 and 210 are the fifth
The selection is made depending on which position from C to F shown in the figure is to be written. At position C, the output of both 209 and 210 is "0", and at position D, the output of 209 is "1" and the output of 210 is " 0” and at position E,
They are controlled so that they become "0" and "1", respectively, and "1" and "1" at the F position, respectively. In this way, when writing at 1/2 in both the horizontal and vertical directions, the selectors 206 to 208 select the H 1 to H 3 sides, and the selector 211 selects the H ₁ to _{H 3} sides.
ROW address COLUMN address is given to memory. The state of the memory element at this time is shown in the 9th section.
As shown in the figure. As shown in Figure 9, in the 1st H, horizontal data is written every other column, and COLUMN
0, ROW address 0-15 and COLUMN
It is written to address 1 and ROW addresses 0 to 10. Next, A ₆ of the V address counter is 1
At the 2nd H, the memory address is
The same location as 1H is specified, but as mentioned above, no write command is given, so it is not written. No.
In the 3rd H, A ₇ becomes 1, so the ROW address is 16.
Specify ~31, COLUMN address is 0 and 11
is specified. For the 4th H, the same address as the 3rd H is specified, but like the 2nd H, no write command is given. If you do the same thing below, all 16H or former ROW addresses will be specified. Then 17H
The number is A ₁₀ is 1, so the COLUMN address is 4
and 5 to specify the ROW address 0 to 15.

Next, when writing in the portion D of FIG. 5, the output of the selector 209 is "1" and the output of the selector 210 is "0", so that the data is written in the diagonally shaded portion downward to the right in FIG.
Similarly, the horizontal line portion is specified for the E portion, and the vertical line portion is specified for the F portion. From this, the fifth
No matter which part of the diagram C, D, E, or F is written, all ROW addresses are specified by 16H or more. This period is 63.5 μs×16≒1 msec, which is within the refresh cycle.

As explained above, in the present invention, the address counter is
A counter is provided to divide and count addresses, and a counter is provided to sequentially count H addresses.
By changing the order of the addresses, all the refresh addresses can be easily addressed within the refresh time even when not all the memory addresses are specified, so that the contents of the memory are not destroyed.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the addresses of a 16K bit memory, Figure 2 is a block diagram of the memory section of a still image transmission device, Figure 3 is a diagram showing the configuration of a conventional address counter, and Figure 4 is a diagram of the conventional address counter. A block diagram when using the memory according to the configuration of the address counter, Fig. 5 is a diagram showing one field of image signal divided into four parts, Fig. 6 is a diagram showing how to use the memory, and Fig. 7 is the present embodiment. Figures 8 and 9 are block diagrams showing how to use the memory according to this embodiment, and Figure 8 is a diagram when all information of one field is written. FIG. 9 is a diagram when it is divided into four parts. In the figure, 1...PCM digital data, 2
...Memory input register, 3...Memory group, 4...
...Address counter, 5...Memory output register, 101...Memory cycle counter, 1
02...H address counter, 103...V address counter, 201...memory cycle counter, 202, 203...H address counter, 204...V address counter, 205...
H period counter, 206-211...selector.

Claims (1)

[Claims] 1. A horizontal address counter consisting of a memory for storing an image signal and an address generation section for the memory, in which the address generation section divides and counts a horizontal period to generate a horizontal address consisting of a plurality of bits, and the horizontal address counter a horizontal period counter that counts a certain bit as a clock and is reset at each horizontal period; a vertical address counter that generates a vertical address consisting of a plurality of bits; at least one bit of the output from the horizontal address counter; and at least one of the outputs of the vertical address counter.
An image memory device comprising: a switch for changing the order of bits and supplying the address signal to the memory as an address signal.