JPS60254186A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a raster scan type display device, and particularly relates to a batch read period in which display data is read out from a frame memory all at once, and screen erasing, scrolling, etc. from the CPU. In allocating memory operation periods for screen operations. This invention relates to improving (increasing) the allocation ratio of memory operation periods.

(2) Background of the technology Display devices used in computer terminals, etc. have a frame memory dedicated to display, and the contents are rewritten one after another at a cycle of about 20m5ec (referred to as a frame cycle) and two displays are displayed on the screen. It is common that the display is displayed. In this case, the performance of the display device is determined by how efficiently and quickly the display data is read from the frame memory onto the display screen and the CPU rewrites the display data in the frame memory.

(3) Prior Art and Problems The conventional display device using the method described above has a display screen of, for example, 512. It is divided into grid areas called 352 vertical pixels, and each pixel is assigned, for example, 1 bit, and if it is "1", that pixel lights up,
If it is "0", the display is performed such that it does not light up. The frame memory temporarily stores the display data for this purpose, and the frame memory corresponds to the number of pixels for one display screen.
It has a memory capacity of 12 x 352 bits. Then, the CPU first writes display data to the frame memory. Thereafter, display data is read out one pixel at a time from the frame memory and applied to the display screen. In this case, generally on the display screen, pixels are displayed in order horizontally starting from the top left of the screen, and each horizontal column (referred to as l raster)
Each time the display ends, the next raster is displayed. and 1
Raster (512 pixels) display takes 56μsec (56X
10-6 seconds) as one period (called a horizontal synchronization period).

As a result, the period of one frame for displaying one screen is 5.
Add extra time to 6μ5ecX352 raster 2
It takes about 0m5ec (20x to" seconds). That is, in 20m5ec, all the display data for one screen is read out from the frame memory and displayed on the display screen. Then, when the display for one screen is completed, the display data is read out from the frame memory again. The reading is repeated from the first address. By performing high-speed scanning in this way with one frame period of about 20m5ec, it is possible to display a visually continuous screen, and this method is called the raster scan method. In such a method, the time required to sequentially read out one rask worth of display data (512 bits) from the frame memory as serial data and supply it to the display screen for one rask display is equivalent to the time required for one rask display. It occupies more than 90% of one horizontal opening period of 56 μsec for display. Therefore, the time during which display data is read from the frame memory to the display screen is less than 10% of the horizontal synchronization period for each raster display. , and the margin time (20 msec) in each frame period.
-56 μsec x 352 rasters). 1st
The figure shows the situation. Figure '1 shows the time required to display one raster in the horizontal direction, that is, one horizontal opening period is 56 μs.
ec, which means that the time it takes to scan each raster one by one and complete the display operation of 352 rasks from top to bottom in the vertical direction, that is, the period of one frame is 20 m5 ec. Of this time, the time during which display data is read from the frame memory to the display screen occupies the shaded area. In the area other than the shaded area, display data is not read from the frame memory and is used for horizontal and vertical synchronization and blanking of one screen, but this takes up at most 10 minutes of the total operating time. Only about % remains. On the other hand, when the CPU performs memory operations such as reading and rewriting display data on the frame memory, during the time indicated by the shaded area in Figure 1 when the display data is being read from the frame memory to the display screen, the CPU
cannot perform memory operations on frame memory, so
The time available for this memory operation is limited to about 10% of the time other than the time shown in the shaded area in FIG. In such a situation, let us consider, for example, erasing one screen worth of display data in the frame memory using the cPU. The effective time required by the CPU for this is generally about 0.1 sec, but since the CPU can only use about 10% of the total time, it actually takes 1 sec to erase one screen's worth of display data. It takes a while. During this time, display data is repeatedly read from the frame memory to the display screen at a frame period of 20m5ec, so during the approximately 1 sec period when the CPU is erasing display data from the frame memory, data is read from the frame memory to the display screen. The display data read out is data that is in the process of being erased. For this reason, there were problems such as the display screen flickering during this period. This kind of problem also occurs when other memory operations are performed from the CPU to the frame memory, and a major drawback is that sufficient screen operation speed cannot be obtained because there is insufficient time for memory operations. Ta.

One way to solve this problem is to prepare frame memory for two screens, make the frame memory where the CPU performs memory operations independent, and switch the display to that frame memory when the memory operation is completed. Although such a method is conceivable, there is a problem in that frame memories for two screens must be prepared, resulting in extremely high costs.

Another method has been proposed in which memory operations by the CPU and read operations for displaying one screen are alternately performed every cycle, but synchronization is required to perform the two operations alternately. occurs.

For example, a typical CPU such as Intel's 16-bit microprocessor i80B6 has the drawback of requiring a complex circuit to synchronize the two-screen display because it performs memory operations asynchronously. Currently, there are very few examples.

(4) Object of the Invention In order to solve the above problems, the present invention provides a buffer memory between the frame memory and the display screen, and reads out the display from the frame memory to the buffer memory at high speed.

To provide a display device capable of shortening the time a frame memory is occupied with reading display data, thereby increasing the memory operation time of a CPU, and enabling high-speed screen operation.

(5) Configuration of the invention In a display device having a frame memory for storing display data to be displayed on a display screen,
a storage means connected to the frame memory for temporarily storing display data; a writing means for reading display data by a fixed amount from the frame memory and writing it into the storage means at high speed; reading means for sequentially outputting to the display screen;

A display device comprising: a control means for connecting the frame memory to an external device during a period when display data is not being written from the frame memory to the storage means by the writing means.

(6) Examples of the invention Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 2 is an overall configuration diagram of a display device according to the present invention. The display control circuit 1 is interconnected with the CPU 2, and a standby signal 1-1 is supplied from the display control circuit 1 to the CPU '2.

A memory operation request signal 2-1 is supplied in the opposite direction. Further, the display control circuit 1 is connected to a display address generation circuit 3 and an address selection circuit 4.

They respectively supply an address generation timing signal 1-2 and an address selection signal 1-3. Further, the display control circuit 1 is connected to a line buffer 6 and supplies W write signals 1-4 and read signals 1-5. In addition, display control circuit 1 is connected to shift register 7 and supplies conversion clocks 1-6. The CPU 2 and display address generation circuit 3 are connected to an address selection circuit and supply address signals 2-2 and 3-1, respectively. Address selection circuit 4 is connected to five sections of frame memory and supplies address signal 4-1. Further, the CPU'2- is interconnected with the frame memory 5 and exchanges data signals 2-3. Frame memory 5 is connected to line buffer 6 and 1
Display data 5-1 is supplied. Line buffer 6 is connected to shift register 7 and supplies nine display data 6-1. The shift register 7 outputs serial display data 7-1 to the display screen.

The operation of the display device configured as above will be explained using the time chart of FIG. 3. first,
The display screen is 512 pixels horizontally (1 raster) x 35 pixels vertically.
It is composed of 2 rasters. Then, 1 bit is assigned to 1 pixel, and the frame memory 5 is 512×352
Suppose it has a memory capacity of bits. It is assumed that the display data is stored in word units in the frame memory 5 as 1 word - 16 bits. Furthermore, the line buffer pro corresponds to one raster of the display screen, has a memory capacity of 512 bits = 32 words, and has display data 5-5 read out from the frame memory 5 to the line buffer 6.
It is assumed that 32 words of 1 are read out one word at a time. In addition, the 32 words of display data temporarily stored in the line buffer 6 are output to the shift register 7, which has a buffer capacity of 1 word, as display data 6-1 for each word, and the serial display data for each word is output. It is displayed as 7-1 and output to the screen.

Now, the display operation of one raster on the display screen is controlled by the horizontal synchronizing signal H5YNC generated in the display control circuit 1, and its period is set to 56/j s.
ec (Figure 3(a)), in synchronization with the rising edge of H3YNC, address selection signals 1-3 are first set to 10μ.
sec (Fig. 3(b)). This time is defined as the display data batch readout period. If this signal is rising, the address selection circuit 4 selects the address signal 1-1 from the display address generation circuit 3 (FIG. 3(C)). During this time, the display address generation circuit 3 successively generates address signals 3-1 for display data for one raster and 32 words in the frame memory 5 in synchronization with the address generation timing signal 1-2 from the display control circuit 1. . As a result, display data corresponding to one raster and 32 words are successively read out from the frame memory 5 as display data 5-1 word by word. The display data 5-1 read out in this way is the write signal 1.
-4, so it is written to the line buffer 6. Write signals 1-4 have a batch readout period of display data of 10 ps
During the ec.

32 pulses with a period of 0.3 p sec (=9.6μ
(The remaining 0.4 μsec is the processing time before and after) (FIG. 3(d)). This signal is naturally synchronized with the readout timing of the display data 5 to 1 from the frame memory 5. In this manner, display data for one raster and 32 words is read out from the frame memory 5 to the line buffer 6 at high speed during the display data batch read period of 10 μsec. When the batch reading period of display data ends as described above, the address selection signal 1
-3 falls (FIG. 3 (bl)), and the address selection circuit 4 selects the address signal 2-2 from the CPU 2 (FIG. 3 (C)).

This connects the frame memory 5 to the CPU 2,
During the remaining 46 μsec period, excluding the 10 μsec batch readout period of display data from the 56 μsec horizontal synchronization period, the CPU 2 sends the data signal 2- to the frame memory 5.
3 allows memory operations to be performed. Here CP
If U2 is display data batch readout period 10μsec
When the memory operation request signal 2-1 is issued to the display control circuit 1 during this period.

The display control circuit 1 outputs a standby signal 1-1 to the CPU 2 until the batch reading period of display data ends,
Put CPU2 on standby. Then, when the batch read period of display data ends, the standby signal 1-1 is released and the memory operation is started. In this way, one horizontal opening period is 56 μsec.
Of this, the time that the frame memory 5 is occupied for reading one raster worth of display data is less than 10 μsec, and the remaining 46 μsec can be occupied by the CPU 2 for memory operations. Next, line buffer 6
The display data of 1 raster=32 words read out is immediately output to the shift register. For this reason, the line buffer 6 uses a two-port memory that can perform writing and reading simultaneously. In this case, the read signals 1-5 to be output to the shift register 7 are 32 pulses with a period of 1.6 μsec (FIG. 3(e)). Then, first, the first word of display data 6-1 is input to the shift register 7 by the first read pulse, and then the shift register 7 inputs the parallel display data of one word by 16 by the conversion clock 1-6. It is converted into bit serial display data 7-1 and output to the display screen within 1.6 μsec. By repeating this operation for 32 words, 1 star 5 is generated during 1 horizontal opening period of 56 μsec.
12-bit serial display data 7-1 is supplied to the display screen (FIG. 3(f)). As described above, the operation of outputting display data from the line buffer 6 can be performed under the control of the display control circuit 1 completely independently of the memory operation of the frame memory 5 by the CPU 2. When the output of display data for one raster is completed in this manner, the horizontal synchronization period for one raster of the 5th order is reached, the corresponding address of the frame memory 5 is designated, and the same operation is repeated. When the output of display data for 352 rasters is completed, the display for one screen is finished.

56μsec x 352 days (about 19.7m5ec
After adjusting the frame period to +20 m5 ec by adding a margin time to the time ), the operation of reading display data from the first address of the frame memory 5 is repeated again.

FIG. 4 is a diagram for explaining the effects of this embodiment. The meaning of this figure is exactly the same as that of FIG. 1 in the conventional explanation. In conventional display devices, the first
As shown in the figure, nearly 90% of the time the frame memory was occupied by reading display data onto the display screen. On the other hand, according to this embodiment, as shown in FIG. 4, the occupied time is only about 20 to 25% of the total. As mentioned above, out of the horizontal synchronization period of 56 μsec for each raster, the time that the frame memory is occupied by reading display data is 10 μsec.
This is because it is only a matter of degree. Therefore, the remaining 75-80%
This time can be allocated to memory operations such as rewriting and erasing display data in the frame memory by the CPU'U, and the speed of one screen operation can be greatly improved.

As an example, a comparison with the conventional method will be made assuming that the memory operation by the CPU takes 10 μsec to erase display data of 1 word and 16 pixels.

Currently, the frame period is 20m5ec + the display screen is 512
The display has ×352 pixels. At this time, the number of frames F required to erase one screen is given by the following equation.

In this formula, in the conventional method, the CPU memory operation allocation time per frame is at most 10 times the period of one frame.
%, so it is about 2m5ec, and in this embodiment, at worst, it is about 75% of the period of one frame, so about 15m5
It becomes ec. Therefore, the value of each of the above F is.

=56 (frame) =8 (frame) So, convert it to 1 hour.

Conventional method 20m5ecX 56= 1120 (m5
ec) This example 20m5ecx 8 = 160 (
msec). Therefore, in the conventional method, it took more than 1 sec to erase one screen, but in the two embodiments, it takes less than 160 m5 ec, thereby eliminating flickering when erasing the screen. Furthermore, according to the present invention, other memory operations such as rewriting can be performed using the conventional 7
~8 times faster operation speed.

According to the above two aspects of the present invention, one raster worth of display data is read out from the frame memory at high speed and temporarily stored (by providing a line bar/7-fur).

The time that the frame memory is occupied with reading display data can be reduced.

In the second embodiment, the capacity of the line buffer is set to one raster, but it is clear that it may be set to several rasters in terms of cost performance. Furthermore, although one raster has 512 bits and the operation is performed in units of one word (16 bits), it is clear that the invention is not limited to this.

(7) Effects of the Invention According to the present invention, a line buffer is provided for reading two display data from a frame memory at high speed and temporarily stored therein, and means for independently performing write and read operations in the line buffer is provided. By providing this, it is possible to shorten the time that the frame memory is occupied with reading out display data, thereby increasing the allocation of memory operations to the frame memory by the CPU, and making it possible to improve the operation speed for one screen.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the problems of the conventional display device, FIG. 2 is an overall configuration diagram of the display device according to the present invention, and FIG. 3 is an operation timing chart of the display device according to the present invention. FIG. 3 is a diagram for explaining the effects of the display device according to the present invention. 1...Display control circuit, 2...CPU,
3... Display address generation circuit 4... Address selection circuit, 5... Frame memory, 6... Line buffer. 7... Shift register, 1-1... Standby signal,
1-2...Address generation timing signal, 1-3.
...Address selection signal. 1-4...Write signal, 1-5...Read signal, 1-6...Conversion clock. 2-1...Memory operation request signal, 2-2゜3-1.
4-1...Address signal, 2-3...Data signal, '5-1.6-1...Display data, 7-1...
・Serial display data Figure 1, 415 = I xlo-6W ms = lXIQ Maki Figure 2

Claims (2)

[Claims] (1) In a display device having a frame memory for storing display data to be displayed on a display screen, a storage means connected to the frame memory and temporarily storing display data. writing means for reading display data in fixed amounts from the frame memory and writing it into the storage means at high speed; reading means for sequentially outputting the display data stored in the storage means to the display screen; 1. A display screen comprising control means for connecting the frame memory to an external device during a period when display data is not being written to the storage means. (2) The capacity of the display data written from the frame memory to the storage means is for one raster of the display screen, and the display data is sequentially output from the storage means to the display screen within one horizontal opening period. The external device connected to the frame memory is a CPU.
2. The display device according to claim 1, wherein the CPU performs memory operations on the frame memory during a period when the frame memory is connected to the cPU.