JPH0441831B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention divides a video memory into a plurality of parts, and displays the divided videos simultaneously on a display screen. It is related to scrolling.

(Prior art) Figure 1 shows a conventional CRT control circuit, and 1 is
CRT controller, 2 is a video memory that stores display data, 3 is a parallel to serial converter (P → S) that converts the parallel display data read from the video memory 2 into serial data and makes it a VIDE signal, 4 is a dot clock generation circuit that generates the above-mentioned VIDE signal sending timing. In the video memory 2, as shown in FIG. 2, display data “A”,
"B",..."H" are displayed in a divided manner on the stored CRT screen. N ₁ , N ₂ ,...N _n is the display start address, n ₁ , n ₂ ,...N _n is the number of display rasters, and y is the number of addresses per raster. To write to the video memory 2 (drawing mode), a microprocessor (hereinafter simply abbreviated as CPU), not shown, sets the mode register 110 to the drawing mode, sets the address counter 108 to the first storage address of the video memory 2, and writes the corresponding data. The output of the address counter 108 is applied to the address bus 6 of the video memory 2 via the address selector 109, a write signal is applied from the control circuit (not shown) of the CRT controller 1 to the control bus 7, and display data is applied to the data bus 8. It is given and done. Further, the CPU stores the display start addresses N ₁ , N ₂ , ...N _n of the divided display data in the video memory 2 in the corresponding display start address registers 101a, 101b, ... 101h, and sets the number of display rasters n ₁ , n ₂ ,...n _n to the corresponding display raster storage registers 102a, 102b,...1
Store in 02h. When reading display data "A", "B"..."H" from video memory 2 and displaying it on the CRT screen (display mode), use split screen counter 1.
05 and display start address selector 1.
03 and raster selector 104 select the outputs of display start address register 101a and display raster storage register 102a, and set them in display address counter 106 and raster counter 107, respectively. The output of the display address counter 106 is sent to the address bus 6 via the address selector 109.
Further, a read signal is applied to the control bus 7, and display data is read from the video memory 2 onto the data bus 8. The read data is converted to VIDE via parallel to serial converter 3.
Output as a signal. At this time, the mode register 110 is set to display mode by the CPU, and the address selector 109 operates to selectively output the output of the display address counter 106.
When the display data of one address is output as a VIDE signal, a pulse is output from the frequency dividing circuit 111 which generates a pulse (address lock) every x (one address consists of x dots) dot clock, and the display address counter 106 starts counting. rise. When the address clock is counted by the number y of addresses per raster, the frequency dividing circuit 1
A pulse (raster clock) is output from 12, and the raster counter 107 counts down.
When the count value of the raster counter 107 reaches "0", the split screen counter 105 counts up, and the display start address selector 103 and raster selector 104 output from the display start address register 101b and display raster storage register 102b of the next split screen, respectively. Select and display the output in the same way as above Address counter 106, Raster counter 1
07 and perform the same process. Thereafter, each time the count value of the raster counter 107 becomes "0", the divided screen counter 105 is counted up and the same process is performed. When display data for one screen is read from the video memory 2, the split screen counter 105 is initialized and the display start address register 101a and display raster storage register 102a are reset.
The outputs are set in the display address counter 106 and raster counter 107.

In Figure 3a, if the display start address of display data "A" is _N1 and the display start address of display data "B" is _N2 , display data "A" and "B" will be displayed on the display screen as shown in the figure. Ru. The areas where display data “A” and “B” are displayed are shown below as screen A and screen B.
Screen. Here, if display data "A ₁ " is drawn in the video memory 2 following display data "A" and displayed on the display screen with the display start address set to N' ₁ , the vertical direction of display data "A" is You will get a scrolling screen. However, A′ is display data “A”
This is some display data. However, with this method, if display data "A ₂ " is further drawn in the video memory 2 and displayed from _N''1 , if the display data "A ₂ " overlaps with the display data "B" (shaded area), the Since the display data "B" as shown in Figure 3 c cannot be displayed normally, the display data as shown in Figure 3 d
A'', A ₁ and A ₂ had to be redrawn from address N ₁ , which had the disadvantage that it took a long time to display, especially when the video memory 2 was a dot memory. However, A'' This is partial display data of data “A”.

In order to avoid redrawing as shown in FIG. 3d, the storage area in the video memory 2 for the display data "A" should be the same as the scroll range of the display data "A".
It is necessary to increase the capacity of the video memory 2, which has the drawbacks of high cost and an increase in the number of parts.

(Object of the Invention) The present invention has been made in view of the above points, and its purpose is to control a display device that takes a short time to display, has a small video memory capacity, and is capable of scrolling a split screen. The purpose is to provide a method.

(Structure of the Invention) To achieve the above object, the present invention converts a first address signal outputted from a controller having an address bus, a data bus, and a control signal line for controlling read/write of a video memory into a second address. The first split screen data is sequentially stored in the first split screen data storage area of the video memory and sequentially read out from the first split screen data storage area.
When the second split screen data storage area following the split screen data storage area is reached, the address converter adds the two's complement of the start address of the first split screen data storage area and the actual row address. The addition result is used as the address of the video memory to read/write the video memory, and will be described in detail below.

(Embodiment) FIG. 4 is a block diagram of a CRT control circuit according to an embodiment of the present invention, which differs from the conventional circuit in that an address translation section 5 is added. FIG. 5 shows an embodiment of the address translation section 5. In Figure 5, 51 is
Split screen counter 105 of CRT controller 1
52 is a register that is set to logic "1" by the CPU (not shown) only when display data for the A screen is drawn in the video memory 2. , 53 is a selector that selects and outputs the output of the decoder 51 or register 52 according to the output from the mode register 110 of the CRT controller 1, 54 is an AND circuit, and 55 is the output from the display start address register 101b of the CRT controller 1 (screen B). Display start address β) and address selector 1
A comparator that compares the output from 09 (actual row address α) and sets the output to logic "1" if α>β, and 56 is a register that stores the two complement number of β according to instructions from the CPU (not shown). , 57 is an adder,
A selector 58 selects and outputs the actual row address α or the output γ of the adder 57 based on the output from the AND circuit 54, and sends an address signal to the video memory 2.

This address translation section 5 operates as follows.

(1) When drawing to video memory 2 (a) Mode register 110 by CPU (not shown)
is the drawing mode, and the two's complement of the display start address β of the B screen is set in the register 56.

(b) Drawing screen A display data Set the register 52 (output to logic “1”) by the CPU (not shown) and input it to one terminal of the AND gate 54 via the selector 53, (a) α<β If so, the output of the comparator 55 becomes logic "0", the output of the AND gate 54 also becomes logic "0", and the output α from the address selector 109 is selected by the selector 58 and becomes the address of the video memory 2 for drawing. (6th
A″, A ₁ , A′ ₂ in Figure a) (b) If α>β, the output of the comparator 55 becomes logic “1”, the output of the AND gate 54 becomes logic “1”, and the selector 58 selects the adder 57.
The output γ is selected and becomes the address of the video memory 2 for drawing. (A″ ₂ in Fig. 6b) (c) Drawing data other than A screen display data The register 52 is reset (the output is set to logic “0”) by the CPU (not shown), and the selector 53
The signal is inputted to one terminal of the AND gate 54 via. The output of the AND gate 54 becomes logic "0", and the selector 58 selects the output α from the address selector 109, which becomes the address of the video memory 2 and is drawn.

(2) When displaying (a) Mode register 110 by CPU (not shown)
is the display mode.

(b) Display of screen A The output of the decoder 51 becomes logic "1" and one terminal of the AND gate 54 becomes logic "1" via the selector 53. (a) If α>β, address selector 109 is used as in the case of drawing. The output α from the video memory 2 becomes the address of the video memory 2 and is displayed. (A'' in Figure 6c, A ₁ ,
A′ ₂ ) (b) If α<β, the output γ of the adder 57 becomes the address of the video memory 2 and is displayed as in the case of drawing. ( _A''2 in Figure 6c) (c) Displays other than screen A The output of the decoder 51 becomes logic "0" and is input to one terminal of the AND gate 54 via the selector 53, and the output of the AND gate 54 becomes logic. The output .alpha. from the address selector 109 becomes "0" and is displayed by the selector 58 as the address of the video memory 2.

As explained above, in the first embodiment, the display data A'' ₂ in the area where display data A ₂ and B overlap is automatically drawn as shown in FIG. This has the advantage that drawing time can be shortened by not having to re-draw in another area when there is overlap.

A second embodiment of the address converter 5 is shown in FIG. 7, and an explanatory diagram of its operation is shown in FIG. The difference between FIG. 7 and FIG. 5 of the first embodiment is that the decoder 51 in FIG.
A register 59 is provided in place of the register 52, selector 53, and AND circuit 54. The operation in FIG. 7 is executed by a CPU (not shown) to set address β to register 59 and address β to register 56.
If the address α specified by the address selector 109 is larger than β, the output γ of the adder 57 is set as the address of the video memory 2, as in the first embodiment. That is, Figure 8a
The display start address of the B screen in the video memory space (virtual video memory space) specified by the address selector 109 is δ, which is the address of the video memory space (real video memory space) specified by the selector 58 as shown in FIG. Corresponds to β. The O-β area and β-δ area (A screen area) of the virtual video memory space are the O-β area of the real video memory space.
Corresponds to the area (A screen area). With such a configuration, in addition to the effects of the first embodiment,
There is an advantage that the number of interface lines between the CRT controller 1 and the address converter 5' is reduced. Further, the address converter 5' shown in FIG. 7 can be used as a read-only memory (RM) 5'' as shown in FIG. 9 to obtain the same effect.

(Effects of the Invention) As described in detail above, the present invention provides storage and readout addresses for the first split screen data in the video memory that are contiguous with the first split screen data storage area. If it is larger than the storage start address, the 2's complement of the start address is added to the actual row address, and the result of the addition is used as the address of the video memory to read/write the video memory, which reduces the capacity of the video memory and reduces the drawing time. It is possible to provide a display device with a small amount of noise, and to perform screen schooling at high speed.

[Brief explanation of the drawing]

Figure 1 is a conventional CRT control circuit diagram, Figure 2a,
b, Figures 3a to 3d are explanatory diagrams of the operation of Figure 1, Figure 4 is a CRT control circuit diagram of an embodiment of the present invention, and Figure 5 is a circuit diagram of an embodiment of the address conversion section of Figure 4. figure,
6a, b, and c are explanatory diagrams of the operation of FIG. 5, FIG. 7 is a circuit diagram of the second embodiment of the address conversion section, and FIG.
Figures a, b, and c are explanatory diagrams of the operation of Figure 7, and Figure 9 is a CRT control circuit diagram of another embodiment. 1: CRT controller, 2: Video memory,
3: Parallel to serial converter, 4: Dot clock generator, 5: Address converter.

Claims (1)

[Claims] 1 Write the data on the data bus to the video memory for each divided screen by using the data on the address bus as an address according to a write instruction from a controller having an address bus, a data bus, and a control signal line for controlling read/write of the video memory. In a control method for a display device that reads data from a video memory onto a data bus in response to a read instruction and displays a plurality of split screens on a display screen, the first address signal output from the controller is converted into a second address signal. The first split screen data is sequentially stored in the first split screen data storage area of the video memory and sequentially read out from the area, and the first split screen data is sequentially read out from the first split screen data storage area of the video memory. When the second split-screen data storage area following the second split-screen data storage area is reached, the address converter adds the two's complement of the start address of the second split-screen data storage area and the actual row address. A control method for a display device characterized by reading/writing a video memory using an addition result as a video memory address.