JPS61248084A - Address generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address generation device for generating an image memory address of a rask scanning type image output device and a gate signal for indicating its effective area.

2. Description of the Related Art Conventionally, an image is displayed not on the entire screen, but for example from the n4th scanning line to the n2nd scanning line (nl and n2 are both natural numbers). When the image memory address has a certain offset, a configuration as shown in FIG. 3 has been used to generate gate signals for indicating the memory address and its valid period.

That is, first, an offset value is loaded from a CPU or the like (not shown) into the counter 9, which can be loaded with a count start value, a clock is input, and the output thereof is used as a memory address. Furthermore, the comparator 11 compares this address with the value of the register 10 that stores the memory address to start displaying, and when they match, the R-S 71J block flag 1
4 is set, and the gate signal output becomes active.

The counter 9 is further incremented, and when its value matches the register 12 storing the display end address, the output of the comparator 13 resets the R-S flip-flop 14 and the gate signal is no longer valid. FIG. 4 shows a timing chart when the memory offset is 4, the display start memory address n1 is 8, and the display end memory address n2 is 12. In FIG. 4, q is the clock input of counter 9, h is the output of counter 9, i is the output of comparator 11, j is the output of comparator 13, and k is R-S.
This is the output of flip-flop 14.

When data ``@8'' is stored in register 10 and data 12- is stored in register 12, offset data ``4#'' is loaded into the counter at a certain point γ. The counter 9 counts up and when the value becomes equal to the value "8" of the register 10 at the time point δ, the output of the comparator 11 is l.
This output sets the gate signal k. Further, the counter 9 continues counting up, and when the value reaches ε, the gate signal k is reset. The value of the counter 9 is output as the memory address.

Problems to be Solved by the Invention When attempting to realize such a circuit as an integrated circuit, it is extremely important that the number of basic gates be small. However, a large number of gates are required to configure a comparison means and a counter into which count start data can be loaded.

In addition, in the conventional method, all registers 10, 12,
Comparators 11 and 13 and counter 9 require the same word length as the image memory address. This has the disadvantage that bits are used inefficiently, especially when the image memory space to be accessed is large compared to the number of scanning lines to be displayed.

The present invention has been made in view of these drawbacks, and an object of the present invention is to provide an address generation device that can be realized with a smaller number of gates.

Means for Solving the Problems In order to solve the above problems, the present invention provides a counter that clears data by a reset signal and counts input clocks, and a first counter that stores a dummy count amount.
a second register that stores the number of occurrences of an address, a third register that stores an access start address, and the data of the counter, the data of the first register, and the data of the second register. a comparator for comparison; an adder for adding the data of the counter and the data of the third register; and, in the comparator, when the data of the counter and the data of the first register match, the counter is cleared. means for setting a gate signal and switching input data to the comparator from a first register to a second register; and means for setting a gate signal and switching input data to the comparator from a first register to a second register; and means for resetting the register and switching the input data to the first register.

For production First, consider a state in which the counter is cleared.

The output obtained by counting the clocks is added with the offset of the third register by an adder, and is output as an access address, and at the same time, is compared with the value of the first register by a comparator. When the value of this counter equals the value of the first register, the counter is cleared, the gate signal becomes valid, and the value of the counter becomes compared with the second register. Then, when the output of the cleared counter equals the value of the second register, the gate signal is no longer valid and the counter is also cleared.

Embodiment FIG. 1 is a block diagram showing the configuration of an address generator in an embodiment of the present invention.

In register 3, set the offset of the image memory address to the scanning line address, in register 1, set the scanning line address n1 to start displaying, and in register 2, set the number of scans #j in the section to be displayed (n2 - n1 + 1). I'll keep it. Initially, when the output of flip-flop 8 is reset and selector 7 selects register 1,
When counter 4 is cleared and a clock signal is input, counter 4 starts counting from zero, and its output is sent to adder 6.
The value of register 3 is added by , and the result is output as an image memory address. At the same time, the output of counter 4 is compared with the data in register 1 by comparator 6. When the output of this counter 4, that is, the scanning line address, matches the number to start displaying and the data in register 1, the output of comparator 6 is set, and this output clears counter 4 and at the same time the flip-flop input to step 8, and a gate signal is set. Furthermore, this gate signal is input to the selector 7, and the selector 7 selects the register 2. Subsequently, when a clock is input to the counter 4, the counter 4 starts counting from zero again, and this time, when the output of the counter 4 matches the value of the register 2, the output of the comparator 5 is set.

The output of this comparator 6 is input to a flip-flop 8,
The gate signal is reset.

FIG. 2 is a timing chart in the case of "1"'t"2=8 and offset value @1o#.

In FIG. 2, a is the clock input to counter 4, b
is the output of the counter 4, C is the output of the adder 6, d is the output of the selector 7, e is the output of the comparator 6, and f is the output of the flip-flop 8. First, when the current value is "4", the counter 4 is counted up, and when the value becomes equal to d, the counter 4 is reset at the rising edge α of e, and at the same time f rises, the selector 7 is Select register 2 and d changes to "6". Next, when b becomes equal to d, the counter 4 is reset by the rise of e and si β, and at the same time 1 falls, the selector 7 selects register 1, and d becomes “4”.
Changes to

In the above embodiment, the case of generation of vertical address and control of display section was described, but this can be explained as follows.
It is possible to control the display interval of pixels in a scanning line and their data storage memory addresses in exactly the same way.

Effects of the Invention In general, the number of scanning lines for displaying an image ranges from several hundred to a dozen or more hundred at most, whereas the image memory address space ranges from several tens of blades to several million words. In the present invention, when displaying only a part of this vast address space as an image, it is possible to reduce the word length of the register for outputting the scan start address, display start address, and display end address on memory. can. Further, the functions required of the counter are only the minimum functions required for a counter, such as counting and resetting, and only one comparator is required. Saving the register word length, simplifying the functions required for the counter, and omitting the comparator as described above all promote simplification in terms of circuit configuration, especially when configured on an integrated circuit.
This will contribute to reducing the basic number of gates.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an address generator according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a block diagram of a conventional address generator. , FIG. 4 is a timing chart for explaining the operation of FIG. 3. 1.2, 3...Register, 4...Counter, 6...Comparator, 6...Adder,
7...Selector, 8...Flip-flop. Name of agent: Patent attorney Toshio Nakao and one other person

Claims (1)

[Claims] A counter that clears data by a reset signal and counts input clocks, a first register that stores a dummy count, and a second register that stores the number of address occurrences.
a third register that stores an access start address; a comparator that compares the data of the counter with the data of the first register and the data of the second register; and an adder that adds data in the third register, and the comparator clears the counter when the data in the counter matches the data in the first register, sets a gate signal, and inputs the signal to the comparator. means for switching data from a first register to a second register; means for resetting the gate signal when data in the counter and data in the second register match in the comparator; 1. An address generation device comprising means for resetting a gate signal and switching input data to a first register, and generating a memory access address and a gate signal indicating validity of the access address.