KR950003055Y1 - Circuit for generating access signal in video graphix array - Google Patents

Abstract

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Description

VGA access signal generation circuit

1 is a block diagram of a conventional VG.

2 is a timing diagram according to a mode in FIG.

3 is a memory state diagram of the text mode of FIG.

4 is a block diagram of an access signal generation circuit of a VGA of the present invention.

5 is a timing diagram according to a mode in FIG.

* Explanation of symbols for main parts of the drawings

1: VGA 2: First in, first out

3: Code storage unit 4: Font storage unit

11: counter 12: register

13 comparator 14 signal generator

15: odd signal generator 16: storm signal generator

17: multiplexer 18: horizontal memory signal generator

19: memory timing generator

AN ₁ : Andgate

The present invention relates to a timing generation for accessing a DRAM at high speed, and particularly to generate a timing for accessing the DRAM at a high speed in a 132-column text mode of VGA (Video Graphic Array, or VGA). It relates to a VG access signal generation circuit.

FIG. 1 is a block diagram of a conventional VG. As shown therein, a first-in-first-out unit (FIFO) for performing data first-in-first-out (FIFO) inside the VGA 1 and two 256 × 4 DRAMs. A code storage unit (3) for storing data used for the VGA (1), and two 256K × 4 DRAMs (DRAM), and fonts for letters used for the VGA (1). It consists of a font storage unit 4 for storing the, the code storage unit 3 stores the code (Code) and the attribute (Attribute) of the character in the text mode (Text Mode).

The operation of the conventional VG configured as described above will be described with reference to a timing diagram according to FIG. 2 mode and a memory state diagram of FIG. 3 text mode.

First, the VGA 1 has a low address as shown in FIG. 2A when in the non-page mode. And column address The data is stored in the first-in, first-out unit 2 by correspondingly generating and accessing the code storage unit 3 and the font storage unit 4.

In addition, the VGA 1 has a low address as shown in FIG. 2B when it is in page mode. Column address with Are sequentially enabled to access the code storage section 3 and the font storage section 4, thereby storing data in the first-in, first-out section 2.

On the other hand, the VGA 1 has to display 132 characters on a horizontal line when the DRAM of the code storage unit 3 is used as a display memory in a text mode using a high frequency clock. Thus, as shown in FIG. Column address in each row address (RASN) as is enabled Is generated and the data is stored in the first-in, first-out unit 2 by accessing the code storage unit 3 and the font storage unit 4.

At this time, before the first and second characters are normally displayed at the time points B and C shown in FIG. 2C, they are stored as shown in FIG. 3 of the code storage unit 3 and the font storage unit 4 in advance. The timing of reading data into the first-in first-out unit 2 and the VGA 1 reads the data in the page mode and stores and displays the data in the first-in first-out unit 2 for non-page mode. mode) and display it on the screen.

However, such a conventional circuit cannot read data in the page mode at the time point D shown in FIG. 2D when the data is displayed on the screen, and converts the data back to the non-page mode. A lot of time was spent and there was a problem of data loss inside the VGA.

SUMMARY OF THE INVENTION In view of these problems, the present invention devised a VG access signal generation circuit for generating a signal for accessing a DRAM at high speed in a text mode-configured VGA, which will be described in detail with reference to the accompanying drawings. .

4 is a block diagram of an access signal generation circuit of the V-GV of the present invention, as shown therein, a counter 11 for counting the number of lines of one character, a register 12 for storing the size of a font, and the counter. Comparators 13 for comparing and outputting the outputs V ₁ and V ₂ of the 11 and the register 12 and outputting one pulse V ₂ , the page mode signal PM and the text signal ( AND gate AN ₁ , which outputs a signal V ₄ multiplied by Text, an output V ₃ of the comparator 13, an output V ₄ of the AND gate AN ₁ , and a vertical display signal ( A signal generator 14 for outputting a vertical letter signal (O / E) as inputted by VDE), and an odd number signal generator 15 enabled according to the output (O / E) of the signal generator 14. And a multiplexer (17) for selectively outputting the odd (odd) and (even) of the odd signal generator (15) and (16) according to the output (14) of the signal generator (14). , Horizontal display signal (HDE ) Is inputted by the horizontal memory signal generator 18 for outputting the memory timing, the output V ₅ of the horizontal memory signal generator 18, and the output V ₆ of the multiplexer 17. Low address signal And column address signal The counter 11 is cleared when the output V ₃ of the comparator 13 is enabled.

The operation and effects of the access signal generation circuit of the present invention VGA configured as described above will be described in detail with reference to a timing diagram according to FIG. 5 mode.

First, when the font size is 8x8, the counter 11 counts up to 0-7, the register 12 stores the maximum value "7", and the comparator 13 stores the counter 11 and the register ( Checking the output (V ₁ ), (V ₂ ) of 12) when the counter size is the largest font size counted by the comparison signal (V ₃ ) as the input (V ₂ ) of the register 12 Are compared in the comparator 13 and match to generate a pulse V ₃ .

At this time, the signal generator 14 outputs the comparator 13 when the page mode signal PM and the text signal Text are enabled and the input AND gate AN ₁ outputs the logical signal V ₄ . When the vertical display signal VDE is enabled as V ₃ is input, the odd signal or even signal is output.

That is, when the current mode is the text mode and the page mode (PM), the signal generator 14 outputs an odd signal when the first letter is vertical, and an even signal when it is the second letter. The output is initialized when the first screen starts.

Then, as the signal generator 14 outputs the vertical letter signal (O / E), the radix signal generator 15 or the even-signal generator 16 for inputting the HT signal is enabled and the radix signal odd. Alternatively, the even signal is output and the multiplexer 17 outputs the odd signal or the even signal generator 16 of the radix signal generator 15 according to the output O / E of the signal generator 14. Outputs the output of even.

At this time, the radix signal generator 15 or the even-signal generator 16 may store the memory data in the first-in, first-out unit FIFO as shown in FIG. 3 before entering the normal standard time interval. The even signal even is outputted and the horizontal memory signal generator 18 outputs the horizontal memory signal V ₅ to the memory timing generator 19 in accordance with the vertical display signal HDE in the normal display section.

Therefore, the memory timing generation unit 19 inputs the output V ₆ of the multiplexer 17 in the font prefetch section and the horizontal memory signal V ₅ in the normal display section, respectively, so that it is vertical. Low address signal as shown in Figs. 5A and 5B depending on the number of characters And column address signal Display the letters on the screen by printing the.

The VGA's access signal generation circuit described in detail above has an effect of displaying the data of the memory on the screen without loss during the normal display period in one horizontal line.

Claims (3)

And a counter 11 for counting the line number of the kaeraekteo, and a register 12 for storing the maximum number of geuljakkol, the output (V ₂₎ of the output (V ₁₎ and the resist 12 of the counter 11 In comparison, the comparator V ₃ outputting the pulse V ₃ , the AND gate AN ₁ that logically multiplies the page mode signal PM and the text signal Text, and the output V ₃ of the comparator 13. ) And a signal generator 14 for receiving the output V ₄ of the AND gate AN ₁ and outputting the vertical letter signal O / E as the vertical display signal VDE is input, and the signal generator 14. The odd signal generator 15 and 16, which are enabled in response to the output (O / E) of the EH and output the odd signal even (odd / even) respectively as the HT signal is inputted, and the signal generator 14 The odd signal generation unit 15, 16 according to the output (O / E) of) and the odd signal generation unit 15, according to the output (O / E) of the signal generator 14, Output (odd) of (16), (even) And a select multiplexer 17 and the horizontal display signal horizontal memory signal generation section 18 for outputting the memory timing (V ₅₎ receives the (HDE) to the output of the multiplexer 17 (V ₆₎ and the horizontal Low address signal as the output V ₅ of the memory signal generator 18 is inputted , Column address signal And a memory timing generation unit (19) for outputting the access signal generation circuit of a VGA. The method of claim 1, wherein the counter (11) includes a comparator (13) output (V ₃₎ V is clear jieyi (VGA) access signal generating circuit, characterized in that the counter is configured to repeat the number of lines of characters according to the. The method of claim 1, wherein the memory timing generator 19 is a font pre-fetched (font pre-fetch) the output (V ₆₎ for, generating unit 18 horizontally memory signal in the normal display period of the multiplexer 17 at the interval Low address signal by input of output (V ₅ ) And column address signal VGA access signal generation circuit, characterized in that configured to output.