JPS6022184A - Display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Technical Field) The present invention divides a video memory into a plurality of parts, and continuously scrolls the divided videos of a display device that simultaneously displays the divided videos on a display screen by memory wrapping. It is about letting people do things.

'Prior art) Fig. 1 shows a conventional CRT control circuit, in which 1 is a CRT controller, 2 is a video memory for storing display data, and 3 is a system for serially displaying parallel display data read out from the video memory 2. Convert to data and make VI DEO signal - Parallel → serial converter (P → S), 4 is the above VI
This is a dot clock generation circuit that generates the DEO signal sending timing. As shown in FIG. 2, display data "I Al1."t 321° .

Nl r N2 H...Nm is the display start address, n
l.

n2,..."m is the number of display rasters, and y is the number of addresses per raster.Writing to the video memory 2 (drawing mode) is performed by a microprocessor (hereinafter simply C), not shown.
(abbreviated as PU) sets the mode register 110 to the drawing mode, sets the first storage address of the video memory 2 in the address counter 108, and sends the output of the address counter 10B to the address bus 6 of the video memory 2 via the address selector 109. Furthermore, a write signal is supplied from a control circuit (not shown) of the CRT controller 1 to the control bus 7, and display data is further supplied to the data bus 8. Further, the CPU sets the display start address Nl+N2 of the divided display data of the video memory 2, and the display start address Nr
n in the corresponding table, showing the start address register, 101a,
Store in 101b, -101h and display 5th fi - number r
ze n2 )...nm is stored in the corresponding display raster storage registers 102a, l 02b, -102b. Display data “A” from video memory 2.

1@B 71...When reading "H" and displaying it on the CRT screen (display mode) split screen counter 105
is reset, the display start address register 101a and the display raster storage register 102a are selected by the display start address selector 103 and the raster selector 104, and the display address counters 106 . Set in the raster counter 107. Display address counter 10
The output of 6 is applied to address bus 6 via address selector 109, and a read signal is further applied to control path 7, so that display data is read from video memory 2 onto data bus 8. The read data is ・Guralel→
It is output as a VIDEO signal via the serial converter 3. At this time, the mode register 110 is set to the display mode by the CPU, and the seat address selector 109 operates to selectively output the output of the display address counter 106. When the display data of one address is output as a VIDEO signal, the frequency dividing circuit 111 which generates a nogle (address clock) every X (one address consists of an The counter 106 counts up. When the address clock is counted by the number of addresses y for one raster, a noggle (raster clock) is output from the frequency dividing circuit 112 and the raster counter 107 counts down. When the count value of the raster counter 107 reaches 0'', the split screen counter 105 counts up and the display start address counter 103. Select an output and display the output in the same manner as above Address counter 1
06. The data is set in the raster counter 107 and similar processing is performed. Thereafter, each time the count value of the raster counter 107 reaches 0, the split screen counter 105 is incremented and the same process is performed.When display data for one screen is read out from the video memory 2, the split screen counter 10
5 is initialized and displays the start address register 101m again.
.

The output of the display raster storage register 102a is sent to the display Azores counter 106. It is set in the raster counter 107.

In FIG. 3(,), if the display start address of display data "A" is Nl and the display start address of display data "B" is N2, then display data ItA is displayed on the display screen as shown in the figure.
", °'B" is displayed. Display data It A II
, II The area where Bn is displayed is shown below on screen A.

There will be 8 screens. Here, display data "A," is drawn in the video memory 2 following the display data "I A l", and displayed on the display screen with the display start address set as N7ri. The display data II A II is then displayed on the display screen as shown in FIG. 3(b). A vertically scrolling screen is obtained. However, A' is the display data It A #
This is some display data. However, with this method, when display data II A 2 # is drawn in the video memory 2 and displayed from fl, if the display data "I A 271 overlaps with the display data II B" (shaded area), the result shown in FIG. 3 (
Since the display data II B" cannot be displayed normally as shown in c), the display data A" and AI as shown in FIG.
, A2 must be redrawn from the address Ml/, which has the disadvantage that it takes a long time to display the image, especially when the video memory 2 is a dot memory. However, A' is a partial display data of the display data "'A".

In order to avoid redrawing as shown in FIG. 3(d), the storage area in the video memory 2 of display data 'A' is
However, the capacity of the video memory 2 needs to be increased, resulting in a high cost and an increase in the number of parts.

(Object of the Invention) The present invention has been made in view of the above points, and an object thereof is to provide a display device that has a fast display time, has a small video memory capacity, and is capable of scrolling a split screen. The purpose is to provide a control method.

(Structure of the Invention) In order to achieve the above object, the present invention converts a first address signal outputted from a controller having an address signal, a data bus, and a control signal line for controlling read/write of a video memory into a second address. The first split screen data is sequentially stored in the first split screen data storage area of the video memory and sequentially read out from the first split screen data storage area. When the second split screen data storage area following the split screen data storage area is reached, the address converter adds the two's complement of the start address of the first split screen data storage area and the actual row address. This will be described in detail below.

(Embodiment) FIG. 4 is a block diagram of a CRT control circuit according to an embodiment of the present invention, which differs from the conventional circuit in that an address translation section 5 is added. FIG. 5 shows an embodiment of the address translation section 5. In FIG. 5, 51 is a decoder (52) that decodes the output from the divided screen counter 105 of the RT controller 1 and outputs the logic II II II only when the screen is on.
Only when display data for the screen is drawn in the video memory 2 is a register set to the logic It1# by the CPU (not shown). Alternatively, a selector selectively outputs the output of the register 52, and 54 is an AND circuit.

55 CRT':27) Compare the output from the display start address register 101b of roller 1 (8 screen display start address β) and the output from the 7 dress selector 109 (actual row address α), and if α> In the case of β, a comparator outputs a logic "1"; 56 is a register that stores the two's complement of β according to instructions from a CPU (not shown); 57 is an adder; A selector that selectively outputs the row address α or the output γ of the adder 57 sends an address signal to the video memory 2.

This address translation section 5 operates as follows.

(When drawing to video memory 2 (,) CPU K (not shown), multi-mode register 1,
.

is the drawing mode, and the two's complement of the display start address β for eight screens is set in the register 56.

(b) Drawing of A-screen display data The CPU (not shown) sets the register 52 (outputs the logic ``1''), and through the selector 53 selects AND/DART 5.
．． (a) If α and β, the output of the comparator 55 will be logic ``0'' (cyand f-) 54
The output from the address selector 109 is selected by the selector 58 and drawn as the address of the video memory 2.
A, 1, A'2) (b) If α>β, the output of the comparator 55 is logic 1", and the output of cyan and dart 54 is logic 1", selector 58 adds The output γ of 57 is selected and drawn at the address of the video memory 2. (FIG. 6(b) - A"2) (c) Drawing of data other than A screen display data is performed by the CPU (not shown) in the register 62. The output from the reset circuit 21 (output logic "0") is inputted to one terminal of the AND gate 54 via the selector 53.

The output of AND dart 54 becomes logic "0#" and selector 5
8, the output α from the address selector 109 is selected and drawn at the address of the video memory 2.

(2) At the time of display (,) The CPU (not shown) sets the remote control 110 to display mode.

(b) The output of the display decoder 51 on the A screen is logic It 171, and one terminal of the AND/DART 54 is set to logic ``1'' via the selector 53.
” (a) If α>β, use the address selector 10 as when drawing
The output α from 9 is displayed as the address of the video memory 2. (A“ in Figure 6(c)).

Al+A'2) (b) If α>β, the output γ of the adder 57 is displayed as the address of the video memory 2+the same as when drawing. (Figure 6 (
c) A//2) (C) The output of the display decoder 5 other than the A screen is set to the logic "o"' by the selector 5.
3 to one terminal of the AND/DART 54, and the output of the AND/DART 54 is set to a logic "0" selector 58.
The output α from the address selector 109 is displayed as the address of the video memory 2.

As explained above, in the first embodiment, the display data A″2 in the portion where the display data A2 and B overlap is shown in FIG. 6(b).
Since the images are automatically drawn as shown in the figure, there is an advantage that drawing time can be shortened because there is no need to judge whether or not there is an overlap and redraw it in another area if there is an overlap, as in the conventional case.

A second embodiment of the address converter 5 is shown in FIG. 7, and an explanatory diagram of its operation is shown in FIG. The difference between FIG. 7 and FIG. 5 of the first embodiment is the decoder 51° register 52. Selector 53. A register 59 is provided in place of the AND circuit 54.

The operation in FIG. 7 is performed by setting the two's complement of address β in register 59 and address selector 56 by a CPU (not shown), and when address α specified by address selector 109 is larger than β, the first execution is performed. Adder 57 as in the example
Let the output γ be the address of the video memory 2. That is, as shown in FIG. 8(a), in the video memory space (virtual video memory space) designated by the address selector 109, 8
The display start address on the screen is δ, which is selector 5.
Video memory space specified from 8 (actual video memory space)
corresponds to address β of . O-β of virtual video memory space
The area and the β-δ area (area for A screen) correspond to the 0-β area (area for A screen) in the real video memory space. Such a configuration has the advantage of reducing the number of interface lines between the CRT controller 1 and the address converter 5' in addition to the effects of the first embodiment. Further, the same effect can be obtained even if the address converter 5' of FIG. 7 is replaced by a read-only memory (ROM) 5'' as shown in FIG.

(Effects of the Invention) As described in detail above, the present invention provides the first
The storage and readout address for split screen data is the first
When the data storage area for the second split screen is larger than the data storage start address for the second split screen, the two's complement of the start address is added to the actual row address, and the result of the addition is used as the address of the video memory to store the image. By reading/writing the memory, a display device with a small video memory capacity and a short drawing time can be provided, and the screen can be scrolled at high speed.

[Brief explanation of the drawing]

Figure 1 is a conventional CRT control circuit diagram, Figure 2 (a),
(b). 3(,) to (d) are explanatory diagrams of the operation of FIG. 1, FIG. 4 is a CRT control circuit diagram of an embodiment of the present invention, and FIG. 5 is an embodiment of the address conversion section of FIG. 4. Circuit diagram, Figure 6(a)
, (b), (C) are operation explanatory diagrams of FIG. 5, FIG. 7 is a circuit diagram of the second embodiment of the address translation section, and FIG.
). (b) l (c) is an explanatory diagram of the operation of FIG. 7, and FIG. 9 is a CRT control circuit of another embodiment. Z: CRT controller, 2: Video memory, 3: Nogular to serial conversion section, 4: Dot clock generation circuit, 5 Near address conversion section. Patent Applicant: Oki Electric Industry Co., Ltd. Figure 2 g Kadenori tol lbl Figure 3 tol tbl Tel Figure 5

Claims (1)

[Claims] In response to a write instruction from a controller that has a control signal line that controls reading/writing of the human address path, data bus, and video memory, the data on the data bus is sent to the video memory for each split screen using the data on the human address path as an address. In a control method for a display device that reads data from a video memory onto a data bus in response to write and read instructions and displays a plurality of split screens on a display screen, the first address signal output from the controller is converted into a second address signal. The first split screen data is sequentially stored in the first split screen data storage area of the video memory and sequentially read out from the first split screen data storage area. When the second split screen data storage area following the first split screen data storage area is reached, the address converter converts the two's complement of the start address of the second split screen data storage area and the actual row address. A control method for a display device characterized by performing addition and using the addition result as an address of the video memory to read/write the video memory.