JPS6457292A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6457292A
JPS6457292A JP62212989A JP21298987A JPS6457292A JP S6457292 A JPS6457292 A JP S6457292A JP 62212989 A JP62212989 A JP 62212989A JP 21298987 A JP21298987 A JP 21298987A JP S6457292 A JPS6457292 A JP S6457292A
Authority
JP
Japan
Prior art keywords
address
data transfer
display
transfer means
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62212989A
Other languages
Japanese (ja)
Other versions
JP2954589B2 (en
Inventor
Yasuo Sakai
Nobuteru Asai
Kazuo Miyazaki
Yukio Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62212989A priority Critical patent/JP2954589B2/en
Publication of JPS6457292A publication Critical patent/JPS6457292A/en
Application granted granted Critical
Publication of JP2954589B2 publication Critical patent/JP2954589B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To decrease a data transfer process quantity by dividing a graphic memory into plural areas, translating an address from a data transfer means into a lateral or longitudinal address according to each divided area, and accessing the graphic memory. CONSTITUTION: A 1st address translator 2 changes the direction of a change in the address of the graphic memory corresponding to each divided area between lateral addresses and longitudinal addresses according to the divided areas. Therefore, a display data storing process from the data transfer means for each divided area and other data storing process can be speeded up. A 2nd address translator 18 divides an area used for display into plural parts and translates addresses from a display address generation part so as to constitute a round-up screen by addressing one of the divided areas in a loop. Consequently, screen scrolling is performed only by the plotting process of a new area and the load of a data updating process by the data transfer means is reduced.
JP62212989A 1987-08-28 1987-08-28 Information processing device Expired - Fee Related JP2954589B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62212989A JP2954589B2 (en) 1987-08-28 1987-08-28 Information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62212989A JP2954589B2 (en) 1987-08-28 1987-08-28 Information processing device

Publications (2)

Publication Number Publication Date
JPS6457292A true JPS6457292A (en) 1989-03-03
JP2954589B2 JP2954589B2 (en) 1999-09-27

Family

ID=16631621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62212989A Expired - Fee Related JP2954589B2 (en) 1987-08-28 1987-08-28 Information processing device

Country Status (1)

Country Link
JP (1) JP2954589B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004318125A (en) * 2003-03-31 2004-11-11 Seiko Epson Corp Image display device
JP2004318124A (en) * 2003-03-31 2004-11-11 Seiko Epson Corp Image display device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741753A (en) * 1980-08-26 1982-03-09 Mitsubishi Electric Corp Arithmetic device
JPS5952286A (en) * 1982-09-20 1984-03-26 株式会社東芝 Video ram writing control system
JPS6022184A (en) * 1983-07-19 1985-02-04 沖電気工業株式会社 Display control system
JPS61246790A (en) * 1985-04-25 1986-11-04 三菱電機株式会社 Address control system for frame memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741753A (en) * 1980-08-26 1982-03-09 Mitsubishi Electric Corp Arithmetic device
JPS5952286A (en) * 1982-09-20 1984-03-26 株式会社東芝 Video ram writing control system
JPS6022184A (en) * 1983-07-19 1985-02-04 沖電気工業株式会社 Display control system
JPS61246790A (en) * 1985-04-25 1986-11-04 三菱電機株式会社 Address control system for frame memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004318125A (en) * 2003-03-31 2004-11-11 Seiko Epson Corp Image display device
JP2004318124A (en) * 2003-03-31 2004-11-11 Seiko Epson Corp Image display device

Also Published As

Publication number Publication date
JP2954589B2 (en) 1999-09-27

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees