JP2004318125A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device capable of reducing display data writing processing for character data when display data are scrolled and displayed at a display part. <P>SOLUTION: This image display device is equipped with a display data storage means which stores display data to be displayed on the display means and can store display data more than display data of the display means, an external information processing means of writing the display data thereto, and a scroll display data readout means of reading the display data out of the display means in order according to sequentially set step quantities and outputting them to the display means. The information processing means has a scroll display data writing means of writing scroll display data before the display data readout means specifies a write address to the display data storage means with its own management address and begins to read, and the display data storage means has an address converting means of converting the inputted management address of the information processing means into its own management address. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image display device that can reduce the load on an information processing unit that writes image data to an image memory of an image display unit when scrolling image data displayed on the image display unit.

As a conventional image display device, when displaying a character message of up to 192 characters stored in the storage unit on a liquid crystal display unit in which the amount of characters that can be displayed at a time is limited to, for example, about 6 characters × 3 lines, The control circuit performs smooth scroll display on the display unit sequentially while expanding the character message stored in the storage unit as display data of six characters in the horizontal direction on the VRAM included in the storage unit, and touch operation of the touch sensor with the scroll display speed. There is known a communication terminal device having a function of receiving a text message, such as a mobile phone or a pager, which can be slowed down by performing the operation (for example, see Patent Document 1).
JP-A-2000-184420 (pages 1 to 5, FIG. 1)

  However, in the conventional example described in Patent Literature 1, when a character message larger than the amount of characters that can be displayed on the display unit stored in the storage unit is displayed on the display unit, the scroll display speed differs. Since the scroll display can be performed, the user can freely change the speed of the scroll display while watching the display of the character message on the display unit, so that the scroll display that is easy for the user to read is performed. However, since the control circuit performs the scroll display control in this case, the load on the control circuit when performing scroll display is large, and when performing other processing in the control circuit, the There is an unresolved issue of limited execution.

  Therefore, the present invention has been made by focusing on the unsolved problems of the above-described conventional example, and when displaying display data on a display unit such as a liquid crystal display by scrolling, display of display data such as characters and images. It is an object of the present invention to provide an image display device capable of reducing control processing.

  A first technical means includes a display means for displaying display data, a display data storage means for storing display data to be displayed on the display means, and a display data amount set to a display data amount larger than the display data amount of the display means. Information processing means for writing display data to the display data storage means; and display data for sequentially displaying display data of a display data amount required by the display means from the display data stored in the display data storage means. Display data reading means for outputting the display data reading means, read start position changing means for moving the display data reading start position of the display data reading means by a set step amount for each set scroll cycle, and required timing within the scroll cycle For notifying the information processing means of setting the display data writing start timing. Wherein the information processing means is configured to determine a write timing of display data in the display data storage means based on a required timing notified from the scroll cycle timing notification means. I have.

  According to this configuration, the display data reading start position of the display data reading means for reading the display data from the display data storage means is moved by the set step amount for each set scroll cycle by the read start position change main stage. By scrolling the display data displayed on the display means sequentially, the scroll timing timing notifying means notifies the information processing means of a required timing, for example, a scroll start timing, in the scroll cycle, so that the information processing means provides the required timing. Can determine the write timing of the display data to the display data storage means, and can execute other processing until the write timing.

Further, the second technical means is configured so that the scroll cycle timing notifying means notifies the information processing means of a scroll start timing when the read start position is changed by the read start position changing means. It is characterized by.
According to this configuration, the scroll start timing notifying unit notifies the information processing device of the scroll start timing. Therefore, the display data corresponding to the scroll step amount is calculated from the scroll start timing and the scroll cycle to the next scroll start timing. The write timing for completing the write can be accurately determined, and the time until the write timing is reached can be used for executing other processing.

Further, in a third technical means, the scroll cycle timing notifying means sets a scroll start flag at a scroll start timing, detects reading of a scroll start flag of the information processing means, and detects reading of a scroll start flag. It is characterized in that the scroll start flag is sometimes reset.
According to this configuration, the scroll cycle timing notifying unit sets the scroll start flag at the scroll start timing, and resets the scroll start flag when the information processing unit detects the reading of the scroll start flag. It is not necessary to reset the scroll start flag, and the processing on the information processing means side can be reduced by this amount.

Still further, a fourth technical means is configured such that the scroll cycle timing notifying means notifies the information processing means of notification information indicating a scroll elapsed period corresponding to an elapsed time from the scroll start timing. It is characterized by:
According to this configuration, the scroll cycle timing notifying unit notifies the information processing unit of the notification information indicating the scroll elapsed period corresponding to the elapsed time from the scroll start timing. Can be accurately determined, and the write timing for completing the writing of the display data corresponding to the display scroll step amount can be accurately determined.

Still further, a fifth technical means is characterized in that the scroll cycle timing notifying means is configured to output the notifying information as an interrupt signal to the information processing means.
According to this configuration, the notification information is output to the information processing means as an interrupt signal, so that the information processing means can accurately determine the write timing of the display data based on the interrupt signal.

Further, the sixth technical means is characterized in that the read start position changing means includes a scroll cycle setting means for setting a scroll cycle, and a step amount set when the scroll cycle set by the scroll cycle setting means is reached. Read start position determining means for determining a read start position based on the read start position.
According to this configuration, when the scroll cycle set by the scroll cycle setting means is reached, the read start position is determined based on the set step amount, so that the read start position can be set accurately.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an image display device as information processing means having a function of generating a signal for writing display data to be displayed to a controller driver 11. An information processing device 12, a liquid crystal display 13 for displaying display data output from the controller driver 11, a Y driver 14 for driving the liquid crystal display 13, and a reference clock necessary for the controller driver 11 to display a liquid crystal screen. And an oscillation circuit 15 that generates

  The controller driver 11 includes a dual port memory 16 as a display data storage unit capable of asynchronously performing an interface with the information processing device 12 and an interface with the liquid crystal display 13, and stores display data from the information processing device 12. The circuit includes a logic circuit 17 for an information processing device to be inputted and a display logic circuit 19 to which a reference clock signal DCLK from the oscillation circuit 15 and a set value from the display controller 18 are inputted.

  In addition, the controller driver 11 controls the X driver 20 that reads one line of display data from the dual port memory 16 and the read / write to the memory areas 16U, 16S, and 16L of the dual port memory 16 that store display data. A read / write circuit 21 for the information processing device, a row address decoder 22 indicating the address of the memory area 16U, 16S, 16L in the Y (row) direction at the time of reading / writing of the information processing device 12, and a memory at the time of reading / writing of the information processing device 12 A column address decoder 23 that outputs addresses in the X (column) direction of the areas 16U, 16S, and 16L, and a display data to be supplied to the X driver 20 among display data stored in the memory areas 16U, 16S, and 16L. And a display address decoder 24.

Here, the information processing device logic circuit 17 has a function of performing a process related to the information processing device 12 such as processing of a command sent from the information processing device 12 and control of display data read / written to / from the dual port memory 16. are doing.
Further, the display logic circuit 19 has a function of reading display data from the dual-port memory 16 and supplying the read data to the X driver 20 and a function of performing control related to display such as control of the Y driver 14.

Further, the X driver 20 is a circuit for converting display data read from the dual port memory 16 into a voltage required by the liquid crystal display 13.
Further, the Y driver 14 receives data for selecting a line for writing a data signal supplied from the X driver 20 via the display controller 18, and supplies a selection / non-selection voltage to drive the liquid crystal display 13. It has a function of generating an appropriate voltage. The Y driver 14 and the X driver 20 are supplied with a voltage generated by the display power supply 25 and required for display on the liquid crystal display 13.

Further, the display capacity of the liquid crystal display 13 is, for example, 176 × 180 dots, and has 180 common electrodes on the left side of the liquid crystal display 13 and 176 segment electrodes on the upper side, as shown in FIG. , An upper fixed display area 13U, a lower fixed display area 13L, and a scroll display area 13S arranged between the fixed display areas 13U and 13L.
On the other hand, the capacity of the dual port memory 16 is 176 × 240 bits larger than the display capacity of the liquid crystal display 13. In the dual port memory 16, as shown in FIG. 2, an upper fixed display data storage area to be displayed in the upper fixed display area 13U between "000" and "039" with a row address is formed, and "040" to "040". A scroll display data storage area to be displayed in the scroll display area 13S is formed between “199” and “199”, and a lower fixed display data storage area to be displayed in the lower fixed display area 13L is formed between “200” and “239”. .

The column address decoder 23 of the dual port memory 16 has the same number of 176 addresses as the number of dots in the X direction of the liquid crystal display 13. The row address decoder 22 of the dual port memory 16 has 30 addresses which are the result of dividing 240 which is the number of dots in the Y direction of the liquid crystal display device 13 by 8 since 8-bit simultaneous writing is performed.
The information processing device 12 designates an arbitrary address to the column address decoder 23 and the row address decoder 22 via the information processing device logic circuit 17 so that display data to be displayed is stored at an arbitrary position in the dual port memory 16. Writing can be performed via the information processing device logic circuit 17 and the information processing device read / write circuit 21.

One bit of the display data corresponds to one dot of the display of the liquid crystal display 13. If the display data is "0", the corresponding predetermined dot on the liquid crystal display 13 is displayed in white, and if it is "1", it is displayed in black.
The display address decoder 24 has 240 addresses equal to the number of dots in the Y direction of the liquid crystal display 13. The display logic circuit 18 specifies any one of the display addresses “0” to “239”. When a display address is designated, the dual port memory 16 outputs 176 data in parallel with the number of dots in the X direction of the liquid crystal display 13 in parallel, and supplies the data to the X driver 20. The X driver 20 converts the received display data into a voltage necessary for driving the liquid crystal display 13 and supplies the voltage to the liquid crystal display 13 for driving.

  As shown in FIG. 3, the display logic circuit 19 includes an 8-bit address counter 31a to 31c with set / reset, registers 32a to 32f for storing an 8-bit address, an 8-bit counter 33 with reset, and an 8-bit 2-system. Selectors 34a to 34c for selecting either data A or B, match detection circuits 35a to 35d for comparing data of two 8-bit systems, and "L" when a "H" level is input to the reset terminal R. Level, and when an "H" level is input to the set terminal S, an RS flip-flop 36a-36c that outputs an "H" level; an OR gate 38 for forming a set signal for the counter 31b; and an 8-bit counter 31a. Or reset signals input to RS-31c and 33 and RS flip-flops 36b-36c And a gate 39 that generates. In FIG. 3, all the buses are constituted by 8-bit buses.

  Here, the termination address FUE (for example, “039”) of the upper fixed display data storage area 16U formed in the dual port memory 16 is set in the register 32a, and stored in the dual port memory 16 in the register 32b. The display start address SAS (for example, “060”) in the scroll display data storage area 16S is set, and the start address SAL (for example, “”) of the scroll display data storage area 16S formed in the dual port memory 16 is set in the register 32c. 040 ") is set. The end address SAE (for example, “199”) of the scroll display data storage area 16S formed in the dual port memory 16 is set in the register 32d, and the scroll display area 13S of the liquid crystal display 13 is set in the register 32e. DSE (for example, “139”) corresponding to the end of “.”, And an address FLL (for example, “200”) corresponding to the head of the lower fixed display area 13L of the liquid crystal display 13 are set in the register 32f. I have.

A reference clock signal DCLK is input to clock input terminals CK of the address counters 31a to 31c. Each time the reference clock signal DCLK is input, the count value is counted up at the time of the rise, and the count value is output to the output terminal. Output from O.
Among them, the address counter 31a has its data input terminal D input with the top address DUS (for example, "000") of the upper fixed display data storage area 16U of the dual port memory 16, and the count value output from the output terminal O. Is output to the other input side of the coincidence detection circuit 35a and the data input terminal A of the selector 34b to which the final address FUE of the upper fixed display area set in the register 32a is input to one input side.

  The address counter 31b has, at its data input terminal D, the display start address SAS of the scroll data storage area 16S set in the register 32b selected by the selector 34a and the display start address SAS of the scroll display data storage area 13S set in the register 32c. Any one of the start addresses SAL is input, and the reset terminal R receives the OR output of the OR gate 39 to which the reset signal RES and the frame display completion signal DE are input, and the count value output from the output terminal O Are output to the data input terminal B of the selector 34b and the end address SAE of the scroll display data storage area 16S set in the register 32d to the other input side of the coincidence detection circuit 35b supplied to one input side.

  Further, an address FLL corresponding to the head of the lower fixed display area 13L set in the register 32f is input to the data input terminal D of the counter 31c, and the OR output of the OR gate 39 described above is input to the reset terminal R. Is input, and the address DLE (for example, “239”) corresponding to the input terminal B of the selector 34c and the end of the lower fixed display area 13L of the liquid crystal display 13 is set to one input side. Is output to the other input side of the coincidence detection circuit 35d supplied to the other.

The count value of the address counter 31a or 31b selected by the selector 34b is output to the data input terminal A of the selector 34c, and the count value selected by the selector 34c is output to the display address decoder 24 as the display address LAD. .
Further, the coincidence detection signal output from the coincidence detection circuit 35a is output to the reset terminal R of the flip-flop 36a and the set terminal S of the flip-flop 36b, and is also output to one input side of the OR gate 38. The match detection signal output from the match detection circuit 35b is input to the input side of.

The set signal output from the positive output terminal Q of the flip-flop 36a is input to the set terminal S of the selector 34a, and the set signal output from the positive output terminal Q of the flip-flop 36b is input to the set terminal S of the selector 34b. Then, the output of the OR gate 38 is input to the set terminal S of the address counter 31b.
Furthermore, a match detection signal output from the match detection circuit 35b is input to the set terminal S of the flip-flop 36a and the other input side of the OR gate 38.

  Further, the address DSE corresponding to the end of the scroll display area 13S of the liquid crystal display 13 output from the output terminal O of the register 32e and the count value output from the output terminal O of the address counter 33 are input to the coincidence detection circuit 35c. The match detection signal output from the match detection circuit 35c is input to the set terminal S of the address counter 31c and the set terminal S of the flip-flop 36c, and the set signal output from the positive output terminal Q of the flip-flop 36c is selected by the selector. The signal is input to the set terminal S of the switch 34c.

  The match detection signal output from the match detection circuit 35d is input to one input terminal of the OR gate 39 as the frame display completion signal DE, and the reset input from the display controller 18 to the other input terminal of the OR gate 39. A signal RES is input, the OR output of the OR gate 39 is input as a set signal to the set terminal S of the address counter 31a, and a reset signal of the reset terminal R of the address counters 31b and 33 and the flip-flops 36b and 36c. It is input to the reset terminal R.

  Here, as shown in FIG. 4, each of the coincidence detection circuits 35a to 35d has eight exclusive positions to which each bit position data in two systems of 8-bit count values input to the input sides A and B is input. The exclusive NOR circuits EXN1 to EXN7, the AND gate AND1 to which the outputs of the exclusive NOR circuits EXN1 to EXN4 are input, the AND gate AND2 to which the outputs of the exclusive NOR circuits EXN5 to EXN8 are input, and the AND gate AND1 AND gate AND3 to which the output of AND2 is input, a D-type flip-flop DFF to which the output of the AND gate AND3 is input to the data input terminal, and an output signal output from the positive output terminal Q of the flip-flop DFF AND gate A to which reference clock signal DCLK is input It is composed of a D4, the coincidence detection signal CDS from the AND gate AND4 outputs.

  In the flip-flop DFF, a reference clock signal DCLK is input to a clock terminal CK via an inverter INV, and a reset signal RES is input to a reset terminal R. Therefore, when the two 8-bit signals input from flip-flop DFF match, an "H" level output signal is output from positive output terminal Q at the next fall of reference clock signal DCLK, and AND gate AND4 Outputs a coincidence detection signal CDS which becomes "H" level in the next ON period of the reference clock signal DCLK.

In the display logic circuit 19, after a predetermined time (for example, a time corresponding to one clock cycle of the reference clock signal DCLK) elapses after the first reset signal RES is input from the display controller 18, the output from the oscillation device 15 is output. The supplied reference clock signal DCLK is started to be supplied to each unit.
The setting of the set values for the registers 32a to 32f of the display logic circuit 19 is performed by the display controller 18 including, for example, a microprocessor. The display controller 18 receives the end address FUE of the upper fixed display area, the start address SAL and end address SAE of the scroll display data storage area 16S, and the start address FLL of the lower fixed display data storage area 16L from the external information processing device 12. A display including a scroll start address SAS for starting scroll display, an end address DSE of the scroll display area 13S, a step amount ST indicating an address moving amount when performing scroll display, a scroll period SP indicating a scroll display cycle, and the like. A display start command is input together with the control data, and the display control process shown in FIG. 5 is executed based on the control data to set the registers 32a to 32f of the display logic circuit 19 and to set the scroll cycle. External information processing at the start Generating an interrupt signal notifying that the start of the scroll time relative location 12.

  The display control process first determines in step S1 whether display control data such as a scroll period SP and a step amount ST has been input from the external information processing device 12, and determines whether display control data has not been input. The process waits until this is input, and when the display control data is input, the process proceeds to step S2, where the input display control data is updated and stored in a predetermined storage area of a memory 18a built in the display controller 18, and then the process proceeds to step S2. Move to S3.

  In this step S3, the end address FUE of the upper fixed display data storage area included in the display control data is written into the register 32a of the display logic circuit 19, the scroll start address SAS is written into the register 32b, and the scroll display data storage area start address SAL Is written to the register 32c, the scroll display data storage area end address SAE is written to the register 32d, the scroll display area end address DSE is written to the register 32e, and the lower fixed display data storage area start address FLL is written to the register 32f.

  Next, the process proceeds to step S4, where it is determined whether or not a display start command has been input from the external information processing device 12. If the display start command has not been input, the process waits until the command is input. If so, the process proceeds to step S5 to output a power supply command to start power supply to the Y driver 14 and the X driver 20 to the display power supply 25, and then to step S6 to reset the reset signal RES. To the display logic circuit 19 and supply of the reference clock signal DLCK to the display logic circuit 19 is started slightly later.

Next, the process proceeds to step S7 to start a scroll period counting timer for counting until the input scroll period SP is reached, and then proceeds to step S8 to add the step amount ST to the current display start address SAS. After calculating a new display start address SAS (= SAS + ST), the process proceeds to step S9.
In this step S9, it is determined whether or not the scroll period counting timer has timed out, thereby determining whether or not the scroll period SP has ended. If the scroll period SP has not ended, the process proceeds to step S10. It is determined whether or not the changed display control data is input from the information processing device 12, and when the display control data is input, the process proceeds to step S11, and the changed display control data, that is, the step amount ST and / or After the scroll period SP is updated and stored in the memory 18a, the process returns to step S9, and when the scroll period ends, the process proceeds to step S12.

  In this step S12, it is determined whether or not a display end command has been input from the external information processing device 12, and when the display end command has been input, the process proceeds to step S13, where the Y driver 14 And outputs a power supply stop command to stop power supply to the X driver 20 and stops supply of the reference clock signal DCLK from the oscillation device 15 to the display logic circuit 19 before returning to step S1.

  On the other hand, if the result of the determination in step S12 is that the display end command has not been input, the process proceeds to step S14, where it is determined whether or not the step amount ST is "0". When it is determined that scroll display is not performed, the process returns to step S7. When the step amount ST is set to a value other than "0", it is determined that scroll display is performed and the process proceeds to step S15. After the display start address SAS calculated in step S8 is written in the register 32b, the process proceeds to step S16.

In step S16, an interrupt signal indicating that the scroll period is started is output to the external information processing apparatus 12, and the process returns to step S7.
In the processing of FIG. 5, the processing of steps S7 to S15 corresponds to the reading start position changing means, of which the processing of steps S7, S9 to S11 corresponds to the scroll cycle setting means, and the processing of step S8 corresponds to the reading start position. The processing of step S16 corresponds to the scroll cycle timing notifying means, corresponding to the determining means. Further, the display logic circuit 19, the X driver 20, and the display address decoder 24 correspond to a display data reading unit.

  Further, the external information processing device 12 includes a scroll display setting device 40 for selecting whether or not to perform scroll display on the image display device 10 and a step amount for setting a step amount ST for performing scroll display. A setting device 41 and a scroll period setting device 42 for setting a scroll period SP corresponding to the switching speed of the scroll display are connected, and based on these, the data display process of FIG. 6 is executed to form display control data. The display data is output to the display controller 18 and display data such as character data input from the input keys and image data input via the Internet is formed, and the display data of the formed display data is displayed on the liquid crystal display 13. The necessary display data is output to the information processing device logic circuit 17 and written into the dual port memory 16. Here, in the scroll period setting unit 42, the counter 31a of the display logic circuit 19 is set, and the counter 31b, 33 and the flip-flops 36b, 36c are reset. Is set to a scroll period SP corresponding to an integral multiple of the frame display period until is obtained.

  The data display process is executed as a timer interrupt process for a predetermined main program every predetermined time (for example, several msec). First, in step S21, a display data write completion flag FE described later completes writing of the initial display data. It is determined whether or not the display data to be displayed on the liquid crystal display 13 has been formed. It is determined whether or not the display data has not been formed, and the process proceeds to step S23 to determine whether or not the display end key has been pressed and whether or not the display has been terminated. Then, a display end command is output to the display controller 18, and then the process proceeds to step S25 to set the display data write completion flag FE. Is reset to 0 "to terminate the timer interruption processing returns to the predetermined main program, and returns to the predetermined main program as it ends the timer interrupt process when it is not in display termination state.

If the result of the determination in step S22 is that the display data to be displayed on the liquid crystal display 13 is formed, the process proceeds to step S26, where the settings of the scroll display setting device 40, the step amount setting device 41, and the scroll period setting device 42 are set. After reading the data, the process proceeds to step S27.
In this step S27, it is determined whether or not scroll display is selected by the scroll display setting unit 40. If scroll display is not selected, the process proceeds to step S28, and the step amount ST for performing scroll display is set to "0". Is set and the scroll period SP is set to the standard value, and then the process proceeds to step S30. If the scroll display is selected, the process proceeds to step S29 where the step amount ST is set by the step amount setting unit 41. After the step amount is set and the scroll period set by the scroll period setting unit 42 is set as the scroll period SP, the process proceeds to step S30.

  In step S30, the last address FUE of the upper fixed display data storage area 13U, the start address SAL of the scroll display data storage area 16S, the end address SAE of the scroll display data storage area 16S, and the lower The address information is composed of the start address FLL of the fixed display data storage area 16L, the address DSE corresponding to the end of the scroll display area 13S of the liquid crystal display 13, the scroll display start address SAS, the step amount ST, and the scroll period SP. The display controller 18 transmits display control data composed of the scroll information composed to the display controller 18.

Then, the process shifts to step S31 to output upper fixed display data to be displayed in the upper fixed display area 13U of the liquid crystal display 13 to the logic circuit 17 for the information processing device by specifying a row address and a column address of the dual port memory 16. Then, the process proceeds to step S32.
In this step S32, the display data of the data amount corresponding to the first scroll display data storage area 16S of the dual port memory 16 of the scroll display data is designated by specifying the row address and the column address of the dur port memory 16 for the information processing device. After performing the initial display data writing processing to be output to the logic circuit 17, the process proceeds to step S33.

In this step S33, the lower fixed display data to be displayed in the lower fixed display area 13L of the liquid crystal display 13 is output to the information processing device logic circuit 17 by specifying the row address and the column address of the dual port memory 16.
Then, the process shifts to step S34 to output a display start command to the display controller 18, then shifts to step S35, sets the display data write completion flag FE to "1", and shifts to step S23. .

  On the other hand, if the result of determination in step S21 is that the display data write completion flag FE is set to "1" indicating completion of initial writing to the dual port memory 16, the process proceeds to step S36, and the setting of each setting device 40 After reading the setting data of .about.42, the process proceeds to step S37 to determine whether or not there has been a change to the previous setting data. If there has been a change in the setting data, the process proceeds to step S38 to make a change. After transmitting the setting data to the display controller 18, the process proceeds to step S39. If there is no change in the setting data, the process directly proceeds to step S39.

In step S39, it is determined whether or not scroll display is selected by the scroll display setting unit 40. If scroll display is not selected, the process proceeds to step S40, and the display data write completion flag FE is set to "0". After resetting, the flow shifts to step S23, and when the scroll display is selected, the flow shifts to step S41.
In step S41, it is determined whether or not an interrupt signal indicating the completion of the scroll display has been input from the display controller 18, and if the interrupt signal has not been input, the process directly proceeds to step S23, where the interrupt signal is input. If the priority processing is not present, the process proceeds to step S44, and if the priority processing is not present, the process jumps to step S44 described later. If the priority process is present, the process proceeds to step S43. Then, the scroll period counting timer started in the display control process of the display controller 18 is read, and it is determined whether or not the timer is equal to or more than a predetermined value. When the scroll period counting timer is less than the predetermined value, the process proceeds to step S23. If the value is equal to or more than the specified value, the process shifts to step S44 to display the current liquid crystal display 1 The display data corresponding to the step amount ST is designated to the data storage area continuous in the scroll direction of the display data displayed in the scroll display area 13S of the specified row address and the column address, and is output to the information processing device logic circuit 17. After performing the scroll data writing process, the process proceeds to step S45.

  In this step S45, it is determined whether or not the fixed display data displayed in the upper and lower fixed display areas 13U and 13L of the liquid crystal display 13 has been changed, and if there has been a change in the fixed display data, the process proceeds to step S46. Then, the fixed display data to be written into the upper and / or lower fixed display data storage areas 16U and / or 16L corresponding to the changed fixed display data is output to the information processing device logic circuit 17, and then the step S23 is performed. Then, if there is no change in the fixed display data, the process directly goes to step S23.

Next, the operation of the first embodiment will be described.
Now, assuming that the display data to be displayed on the liquid crystal display 13 is not formed by the information processing device 12 and a display end command is output to the display controller 18, the display controller 18 performs the display control process of FIG. Then, the process proceeds from step S12 to step S13, in which a power supply stop command is output to the display power supply 25, so that the power supply to the Y driver 14 and the X driver 20 is stopped, and the display on the liquid crystal display 13 is stopped. It has been stopped.

  In this display stop state, the display data writing completion flag FE is reset to “0” when the information processing device 12 is executing the data display process of FIG. 6, so that the process proceeds from step S21 to step S22. Then, since the display data to be displayed on the liquid crystal display 13 has not been formed, the flow shifts to step S23, and since the display end key has not been pressed, the timer interrupt processing ends as it is.

  From this display stop state, the information processing device 12 captures display data including image data of the Internet, receives an e-mail, and starts creation of document data by key operation. When the display data that needs to be displayed is created in step 13, the setting data of each of the setting devices 40 to 42 is read in the data display process of FIG. 6 (step S26).

At this time, assuming that scroll display is not selected by the scroll display setting device 40, the step amount ST is set to "0" and the scroll period SP is set to a standard value (step S28).
Then, the preset final address FUE of the upper fixed display data storage area 13U in the dual port memory 16, the start address SAL of the scroll display data storage area 16S, the end address SAE of the scroll display data storage area 16S, and the lower fixed display data Address information composed of a start address FLL of the storage area 16L, an address DSE corresponding to the end of the scroll display area 13S of the liquid crystal display 13, and scroll information composed of a display start address SAS, a step amount ST, and a scroll period SP. Is transmitted to the display controller 18 (step S30).

  Therefore, in the processing of FIG. 5, when the display control data is input from the information processing device 12, the display controller 18 stores the input display control data in the memory 18a (step S2). , The end address FUE of the upper fixed display data storage area contained in the register 32a of the display logic circuit 19, the scroll start address SAS in the register 32b, the scroll display data storage area start address SAL in the register 32c, and the scroll display data storage. The area end address SAE is written into the register 32d, the scroll display area end address DSE is written into the register 32e, and the lower fixed display data storage area start address FLL is written into the register 32f (step S3). Is entered In to wait.

  The information processing device 12 outputs the display control data to the display controller 18 and then writes the display control data to the upper fixed display data storage area 16U of the dual port memory 16. The upper fixed display data is output to the processing device logic circuit 17 (step S31), whereby the upper fixed display data is written in the upper fixed display data storage area 16U of the dual port memory 16.

  When the writing of the upper fixed display data is completed, the scroll display data to be written into the scroll display data storage area 16S of the dual port memory 16, for example, the character data represented by A to I shown in FIG. (Step S32), whereby the scroll display data is written from the row address “060” to the row address “159” of the scroll display data storage area 16S of the dual port memory 16.

When the writing of the scroll display data is completed, the lower fixed display data for displaying, for example, time information to be written in the lower fixed display data storage area 16L of the dual port memory 16 is output to the information processing device logic circuit 17 ( Step S33), whereby the lower fixed display data is written into the lower fixed display data storage area 16L of the dual port memory 16.
When the writing of the lower fixed display data is completed, a display start command is output to the display controller 18 (step S34), and the display data write flag FE is set to "1" (step S35).

  When a display start command is input from the information processing device 12, the display controller 18 outputs a power supply command to the display power supply 25 (step S5), whereby the Y driver 14 and the X driver Power is supplied to 20. Next, the reset signal RES is output to the display logic circuit 19, and the supply of the reference clock signal DCLK from the oscillation device 15 to the display logic circuit 19 is started slightly later (step S6). Next, a scroll period counting timer is started (step S7).

  In the display logic circuit 19, as shown in FIG. 8A, when a reset signal RES is input from the display controller 18, the reset signal RES is supplied as a set signal to the set terminal S of the address counter 31a. “000” set in the data input terminal D of 31a is set as a count value, and this is supplied from the output terminal O to the input terminal A of the selector 34b.

  On the other hand, when the logical sum of the reset signal RES and the frame display completion signal DE is supplied to the reset terminal R of the RS flip-flop 36b, the output of the positive output terminal Q becomes low, and this is the set terminal of the selector 34b. Since the signal is input to S, the input terminal A is selected by the selector 34b, and “000” input to the input terminal A is input to the input terminal A of the selector 34c.

  At this time, since the logical sum of the reset signal RES and the frame display completion signal DE is input to the reset terminal R of the RS flip-flop 36c, the positive output terminal Q becomes low level, and the input terminal of the selector 34c is set. A is selected, and “000” input to the input terminal A is output to the display address decoder 24 as the display address LAD.

Further, the reference clock signal DCLK output from the oscillation device 15 with a predetermined time delay from the input of the reset signal RES is started to be supplied to the address counters 31a to 31c and 33.
For this reason, the display data of the head address “000” of the upper fixed display data storage area 16U of the dual port memory 16 is read as shown in FIG. 8C, and this is read by the X driver 20 as shown in FIG. At the falling edge of the reference clock signal DCLK, it is captured as shown in FIG.

Also, as shown in FIG. 8E, the display logic circuit 19 outputs to the Y driver 14 a selection signal YDATA that goes high from the rising of the reset signal RES to the rising of the next reference clock signal DCLK. The driver 14 performs line selection when the selection signal YDATA is at a high level, and enters a line non-selection state when the selection signal YDATA is at a low level.
Then, the Y driver 14 takes in the selection signal YDATA at the fall of the reference clock signal DCLK, and transfers the selection signal YDATA by each of the internal 180-stage shift registers (not shown). Each output of the 180-stage shift register sequentially moves to the right according to the reference clock signal DCLK as shown in FIGS. 8 (e0) to (e179).

When the driver data of the X driver 20 is the data of the display address “000”, the data of the display address “000” is displayed on the first row of the liquid crystal display 13 by the selection signal Y0 of the Y driver 14 being at a high level. Is done.
Thereafter, each time the reference clock signal DCLK is sequentially input, the count value of the address counter 31a is counted up at the rising edge as shown in FIG. 8C, and is counted by the X driver 20 at the falling edge of the reference clock signal DCLK. Data acquisition is performed as shown in FIG.

  On the other hand, in the display logic circuit 19, as shown in FIG. 9C, the count value of the address counter 31a is counted up at the rise of the reference clock signal DCLK shown in FIG. 8B, and this count value is stored in the register 32a. When the end address FUE "039" of the set upper fixed display area becomes equal, the 8-bit comparison output CS of the coincidence detection circuit 35a becomes a high level as shown in FIG. The output FOS of the flip-flop DFF becomes high level as shown in FIG. 9 (e), and becomes high level from the rising and falling of the reference clock signal DCLK from the AND gate AND4 as shown in FIG. 9 (f). The detection signal CDS is output.

On the other hand, in the address counter 31b, the count value is reset to “000” when the reset signal RES is input. In this state, a high-level set signal is not input to the set terminal S. As shown in the figure, the count is incremented every time the reference clock signal DCLK is input.
In this state, when the high-level match detection signal CDSa is output from the match detection circuit 35a as described above, this is input to the reset terminal R of the RS flip-flop 36a, thereby setting the set terminal S of the selector 34a. When the level becomes low, SAS “060” set in the register 32b input to the input terminal A is selected and supplied to the data input terminal D of the address counter 31b. Therefore, when the match detection signal CDSa is input to the set terminal S of the address counter 31b via the OR gate 38, the count value of the address counter 31b is changed from "039" to "060" as shown in FIG. The count value “060” is input to the input terminal B of the selector 34b, and a high-level match detection signal CDSa is supplied from the match detection circuit 35a to the set terminal S of the RS flip-flop 36b. When this is set and the positive output becomes high level, and this is input to the selector 34b, the count value "060" of the address counter 31b supplied to the input terminal B is selected by the selector 34b, and this is selected. 34c.

For this reason, the display address LAD output from the selector 34c becomes "060" as shown in FIG. 9 (o), and the count value of the address counter 31b thereafter counts up every time the reference clock signal DCLK is input. The display address LAD output from the selector 34b is counted up as shown in FIG.
Also, as shown in FIG. 9 (k), the address counters 31c and 33 also count up each time the reference clock signal DCLK is input after being cleared to “000” by the reset signal RES.

  Thereafter, when the count value of the address counter 33 reaches the scroll display area end address DSE (= "139") set in the register 32e, the high-level match detection signal CDSc is output from the match detection circuit 35c to FIG. As shown in the figure, this is input to the set terminal S of the address counter 31c, whereby the start address FLL (= “200”) of the lower fixed display data storage area 16L set in the register 32f is set as the count value. The count value "200" is input to the input terminal B of the selector 34c.

  On the other hand, since the coincidence detection signal CDSc output from the coincidence detection circuit 35c is input to the set terminal S of the RS flip-flop 36c, the flip-flop 36c is set, and the positive output thereof becomes a high level. Since the signal is input to the set terminal S, the count value "200" of the address counter 31c input to the input terminal B is selected by the selector 34c, and this is output as the display address LAD as shown in FIG. Is done.

Thereafter, the count value of the address counter 31c is incremented every time the reference clock signal DCLK is input, and the count value is selected by the selector 34c and output as the display address LAD.
Thereafter, when the count value of the address counter 31c becomes "239", the coincidence detection circuit 35d outputs a high-level coincidence detection signal DE as shown in FIG. 9 (l).

  Therefore, the display addresses LAD output from the display logic circuit 19 are “000” to “39”, “60” to “159”, and “200” to “239”. Upper fixed display data stored in the storage area 16U, scroll display data at addresses "060" to "159" in the scroll display data storage area 16S, and lower fixed data stored in the lower fixed display data storage area 16L. The display data is sequentially read out and displayed on the liquid crystal display 13, so that the liquid crystal display 13 displays upper fixed display data represented by "O", "A" to "A", as shown in FIG. The scroll display data represented by “J” and the lower fixed display data represented by “△” are displayed.

  During this time, in the information processing apparatus 12, since the display data write flag FE is set to "1", the process shifts from step S21 to step S36 to read the setting data of each of the setting devices 40 to 42 and change them. If it is determined that there is no display, the process proceeds to step S39, and if it is determined that scroll display has not been selected, the process proceeds to step S40, where the display data write flag FE is reset to “0” and the display end is selected. Since there is no timer interrupt processing, the timer interrupt processing is terminated. For this reason, when new display data is not created in the next timer interrupt processing, the process shifts from step S22 to step S23 and ends the timer interrupt processing. Therefore, the display control process in the information processing device 12 is simplified, and the load on the display control process can be reduced.

On the other hand, the display controller 18 proceeds to step S8 to calculate a new display start address SAS by adding the step amount ST set to “0” to the current display start address SAS (= “060”). However, since the step amount ST is “0”, the display start address SAS is not changed.
Thereafter, it is determined whether or not the scroll period counting timer has timed up, and whether or not the scroll period SP has ended. If the scroll period SP has not ended, the display changed from the information processing device 12. It is determined whether or not control data has been input (step S10). Since there is no input of display control data, the process returns to step S9 as it is, and this state is repeated. When the scroll period SP ends, the process proceeds to step S12. Then, it is determined whether or not a display end command has been input from the information processing device 12, but since the display end command has not been input, the process proceeds to step S14, and since the step amount ST is "0", the process proceeds to step S7. Then, the scroll period counting timer is started again. Further, the counters 33, 31b, 31c and the flip-flops 36b, 36c are reset and the counter 31a is set by the coincidence detection signal DE, so that the display logic circuit 19 performs exactly the same operation as described above. 7, the display state of the upper fixed display area 13U, the scroll display area 13S, and the lower fixed display area 13L is continued.

  In the fixed display state of the scroll display area 13S, scroll display is selected by the scroll setting device 40 of the information processing device 12, the step amount ST is set to, for example, "020" by the step amount setting device 41, and the scroll period is set. When the scroll period SP is set by the device 42, the information processing device 12 determines that the setting data has been changed in step S37, shifts to step S38, transmits the changed data to the display controller 18, and then selects scroll display. Therefore, the process shifts from step S39 to step S41. Since the scroll display completion interrupt signal has not been input from the display controller 18, the timer interrupt process is ended via step S23 and the process returns to the predetermined main program.

When the display controller 18 receives the display control data changed in step S10 in the display control process of FIG. 5, the process proceeds to step S11 and stores the changed display control data, that is, the step amount ST and the scroll period SP in the memory 18a. After the update and storage, the process returns to step S9, and waits for the end of the scroll period SP.
Then, when the scroll period counting timer times out and the scroll period SP ends, the process shifts from step S9 to step S12, and since the display end command has not been input, the process shifts to step S14, and the step amount ST becomes “000”. Since the value is set to a value other than, the process proceeds to step S15, and the display start address SAS is written to the register 32b. Then, the process shifts to step S16 to output an interrupt signal indicating completion of scroll display to the external information processing device 12, and then returns to step S7 to start the scroll period counting timer set to the roll period SP. .

However, at this point, since the display start address SAS has not been changed, the display start address SAS maintains “060” and the display state before the scroll selection is maintained.
On the other hand, in the information processing apparatus 12, when the interrupt signal indicating the completion of the scroll display is input from the display controller 18, the scroll display is selected, and the process proceeds from the step S39 to the step S42 via the step S41 and proceeds to the step S42. It is determined whether or not there is a priority process that prioritizes the process over the display control. If there is no priority process, the process directly proceeds to step S44 to write the current scroll display data storage area 16S of the dual port memory 16. Scroll display data for writing new display data "K" and "L" in an area continuous in the scroll direction to the inserted row addresses "060" to "159", that is, row addresses "160" to "179". After performing the writing process, the timer interrupt process is terminated via step S23, and the process returns to the predetermined main program. That.

  If there is a priority process, the process proceeds to step S43, where the timer value of the scroll period counting timer is read, and the scroll display data is transferred to the dual port memory until the current scroll period SP ends. It is determined whether or not a predetermined value corresponding to a time required to complete writing to the scroll display data storage area 16S of 16 has been reached. If not, the process proceeds to step S23. Then, the flow shifts to step S44, where scroll display data writing processing for writing new display data "K" and "L" is performed.

In any case, the writing of the scroll display data into the scroll display data storage area 16S of the dual port memory 16 is completed before the next scroll period SP starts.
Then, the process proceeds to step S8 to calculate a value obtained by adding the step amount ST (= “020”) to the current display start address SAS (= “060”) as a new display start address SAS (= “080”). Then, it waits until the scroll period counting timer times out and the scroll period SP ends.

  Thereafter, when the scroll period SP ends, the process proceeds from step S9 to step S14 via step S12. Since the step amount ST is set to a value other than “000”, the process proceeds to step S15 to display the display start address SAS. Is written in the register 32b, and then the process proceeds to step S16 to output an interrupt signal indicating completion of scroll display to the external information processing device 12. The display logic circuit 19 sequentially outputs “000” to “039”, “080” to “179”, and “200” to “239” as the display address LAD, so that the liquid crystal display 13 shown in FIG. Thus, scroll display data represented by character data "C" to "L" is displayed.

As described above, during the scroll period SP where the display address LAD is output from the display logic circuit 19, the display data for the scroll corresponding to the step amount ST at the time of the next scroll is written, and then the dual port memory 16 is rewritten. Since the display data is read out and supplied to the liquid crystal display 13, scroll display is sequentially performed.
When the writing from the information processing device 12 to the end address “199” of the scroll display data storage area 16S in the dual port memory 16 is completed, and the next scroll display data is to be written, the scroll display data storage area 16S , The scroll display data is written in the start address SAL, and the row addresses to be sequentially written are increased thereafter.

  In response to this, the display start address SAS written in the register 32c of the display logic circuit 19 is also sequentially increased by the step amount ST (= "020"), so that the match detection signal CDSa is output from the match detection circuit 35a. When output, the count value set in the address counter 31b increases, and as shown in FIG. 11 (h), the count value is increased by the SAE before the count value of the address counter 33 reaches "139". When it reaches 199 ", the coincidence detection circuit 35b outputs a high-level coincidence detection signal CDSb as shown in FIG. 11 (i).

  Since the coincidence detection signal CDSb is supplied to the set terminal S of the RS flip-flop 36a, the output of the positive output terminal Q of the flip-flop 36a becomes high, and the dual port memory set in the register 32c by the selector 34a. The head address SAL (= “040”) of the scroll display data storage area in 16 is selected and input to the data input terminal D of the address counter 31b, and the match detection signal CDSb of the match detection circuit 35b is input to the address counter 31b. Therefore, the count value is set to the start address SAL (= "040") and supplied to the selector 34b. When the match detection signal CDSa is output from the match detection circuit 35a in the selector 34b, Since input terminal B is selected Start address SAL (= "040") is supplied to the selector 34c, and output to the display address decoder 24 as the display address LAD.

Therefore, scroll display data is read from the head address “040” of the scroll display data storage area 16S of the dual port memory 16, and scroll display is continued.
Thereafter, when a key or the like for ending the display process is operated in the information processing device 12, the process proceeds from step S23 to step S24 in the data display process of FIG. 6, and outputs a display end command to the display controller 18, Next, after resetting the display data write flag FE to "0", the timer interrupt process is terminated and the process returns to the predetermined main program.

  Therefore, in the display controller 18, when the display end command is input, the process shifts from step S 14 to step S 15, and the power supply stop command is output to the display power supply 25, and the Y driver 14 and the X driver 20 are output. Is stopped, the input of the reference clock signal DCLK from the oscillation device 15 to the display logic circuit 19 is stopped, and the data display on the liquid crystal display 13 ends.

  As described above, according to the above-described embodiment, at the time of scroll display, the display data reading process from the scroll display data storage area 16S of the dual port memory 16 is performed by the display controller 18 and the display logic circuit 19, and the information processing device 12 The writing of the scroll display data according to the step amount ST in the period may be performed based on the interrupt signal input from the display controller 18, and the load of the scroll display processing in the information processing device 12 can be greatly reduced. Therefore, other processes can be effectively performed, and the processing efficiency of the information processing device 12 can be significantly improved.

  In the above embodiment, the display controller 18 outputs an interrupt signal to the information processing device 12 at the end of the scroll period SP, that is, at the start of the scroll period SP, and the information processing device 12 uses the scroll period counting timer. Has been described, the present invention is not limited to this. The timing at which the writing of the scroll display data in the information processing device 12 can be completed by the end of the scroll period SP is indicated by the display controller 18. And a write interrupt signal may be output to the information processing device 12. In this case, the load of the data display processing in the information processing device 12 can be further reduced. Further, the information processing device 12 measures the timing at which the writing of the scroll display data can be completed from the reception of the interrupt signal to the end of the scroll period SP, and the measured timing corresponds to the scroll display data. Writing may be performed.

  In the above embodiment, only the display data corresponding to the scroll display area 13S of the liquid crystal display 13 is written in the initial display data writing process (step S32) in the scroll display data storage area 16S of the dual port memory 16. Although the case of writing has been described, the present invention is not limited to this, and the initial display data writing process corresponds to the display data corresponding to the scroll display area 13S of the liquid crystal display 13 and the step amount ST during scrolling. By writing and storing the display data to which the scroll display data is added, writing to the scroll display data storage area 16S in the dual port memory 16 in the information processing device 12 may not be completed before the school period SP ends. When the alarm occurs, the scroll display data being written is displayed. It is possible to reliably avoid that.

  Further, in the above-described embodiment, the case has been described where the scroll display data to be written into the scroll display data storage area 16S of the dual port memory 16 by the information processing device 12 at the time of scroll display has a data amount corresponding to the step amount ST. The present invention is not limited to this. The scroll display data corresponding to an integral multiple of the step amount ST may be written once, and the scroll display data may be written once every integer times.

  Furthermore, in the above embodiment, the case where the display controller 18 outputs the interrupt signal indicating the start point of the scroll period SP to the information processing device 12 has been described. However, the present invention is not limited to this. As shown, the display control process of FIG. 5 includes a step S51 of setting a scroll period start flag FS indicating the start of a scroll period to “1” instead of the process of step S16, and the determination result of step S9 indicates that the scroll When the period has not ended, the process proceeds to step S52 to determine whether or not the information processing device 12 has read the scroll period start flag FS. The determination result indicates that the scroll period start flag FS has been read. At this time, the process proceeds to step S53, where the scroll period After resetting the start flag FS to “0”, the process proceeds to step S10, and the same process as that of FIG. 5 is performed except that the process directly proceeds to step S10 when the scroll period start flag FS is not read. Is also good. In this case, the scroll period start flag FS is read at a predetermined timing on the information processing apparatus 12 side, and when the scroll period start flag FS is read, the scroll period start flag FS is set on the display controller 18 side. Since the information is reset to “0”, the information processing apparatus 12 can omit the processing related to the interrupt signal input from the display controller 18, and the load of the data display processing can be further reduced. However, since it is possible that the process proceeds to step S12 while FS = "1", FS is reset to "0" in step S50 before that.

6 and 12 are executed for each timer interrupt, but are implemented only when an interrupt signal indicating the start point of the scroll period SP is input from the display controller 18 to the information processing device 12. It is also possible. As a result, the number of processes can be reduced, and the load can be further reduced.
Furthermore, in the above-described embodiment, the case where scroll display is performed downward is described. However, the present invention is not limited to this case. When the address is changed from the start address SAL to the end address SAE in the scroll display data storage area 16S in the port memory 16, the scroll display data is subtracted from the row address obtained by subtracting the address corresponding to the step amount ST from the current row address. When the value obtained by subtracting the step amount ST from the current display start address SAS is equal to or greater than the start address SAL of the scroll display data storage area 16S, the display controller 18 calculates the step amount from the current display start address SAS. Start displaying a new value with ST subtracted Set as dress SAS, when the value obtained by subtracting the step amount ST from the current display start address SAS is smaller than the head address SAL calculates a new display start address SAS performs the following operation (1).

SAS = SAE- {ST- (SAS-SAL)} (1)
That is, a value obtained by subtracting the difference between the current display start address SAS and the start address SAL of the scroll display data storage area 16S from the step amount ST from the end address SAE of the scroll display data storage area 16S is newly displayed. It is calculated as the address SAS.

Then, by writing the calculated display start address SAS in the register 32b of the display logic circuit 19, scroll display can be performed upward.
Further, in the above-described embodiment, the case where the display logic circuit 19 is configured by hardware has been described. However, the present invention is not limited to this, and may be configured by software.

Further, in the above-described embodiment, the case where the scroll display is performed in the vertical direction has been described. However, the present invention is not limited to this, and the scroll display may be performed in the horizontal direction.
Furthermore, in the above-described embodiment, the case where the liquid crystal display 13 is provided with the upper fixed display area 13U, the scroll display area 13S, and the lower fixed display area 13L is described, but the present invention is not limited to this. Either one or both of the fixed display area 13U and the lower fixed display area 13L may be omitted to secure a wide scroll display area 13S.

  Furthermore, in the above-described embodiment, a case has been described in which both the scroll display step amount ST and the scroll period SP can be changed in the information processing device 12, but the present invention is not limited to this. Alternatively, only the scroll period SP can be changed, or the step amount ST and the scroll period SP can be fixed to standard values.

In the above embodiment, the case where the liquid crystal display 13 is applied as the display means has been described. However, the present invention is not limited to this, and other display devices such as an organic electroluminescence display can be applied.
Further, in the above-described embodiment, the case where the scroll period SP set in the information processing device 12 is equal to the display control period from the display start timing in the display logic circuit 19 until the frame display completion signal DE is obtained has been described. However, the present invention is not limited to this. When the scroll period SP set by the information processing device 12 is set to be equal to or longer than the display control period in the display logic circuit 19, the counter by the frame display completion signal DE on the display controller 18 side. Instead of resetting the flip-flops 33, 31b, 31c, flip-flops 36b, 36c and setting the counter 31a, the start time of the scroll period SP is read, and at this time, a reset signal RES is output, and the counters 33, 31b, 31c, Reset of flip-flops 36b and 36c It may be performed to set the fine counter 31a.

1 is a configuration diagram illustrating an image display device according to an embodiment of the present invention. FIG. 4 is an explanatory diagram showing storage contents of a dual port memory. It is a block diagram of a display logic circuit. It is a block diagram of a coincidence detection circuit. 5 is a flowchart illustrating a display process of a display controller. 9 is a flowchart illustrating a data display process of the information processing device. FIG. 4 is an explanatory diagram illustrating a display state of a liquid crystal display. 6 is a time chart for explaining the operation of the XY driver. 6 is a time chart for explaining the operation of the display logic circuit. FIG. 4 is an explanatory diagram showing a scroll state of the liquid crystal display. 6 is a time chart for explaining the operation of the display logic circuit. 11 is a flowchart of a display controller showing a modification of the present invention.

Explanation of reference numerals

Reference Signs List 10 image display device, 11 controller driver, 12 information processing device, 13 liquid crystal display, 14 Y driver, 15 oscillation device, 16 dual port memory, 17 information processing device logic circuit, 18 display controller, 19 display logic circuit, 20 X driver, 21 read / write circuit for information processing device, 22 row address decoder for information processing device, 23 column address decoder for information processing device, 24 display address decoder, 25 display power supply, 31a-31c, 33 address counter, 32a- 32f register, 34a-34c selector, 35a-35d coincidence detection circuit.

Claims (6)

  Display means for displaying display data, display data storage means for storing display data to be displayed on the display means, and a display data amount set to a display data amount larger than the display data amount of the display means; External information processing means for writing display data, and display data for sequentially reading display data of a display data amount required by the display means from display data stored in the display data storage means and outputting the display data to the display means Reading means; read start position changing means for moving a display data reading start position of the display data reading means by a set step amount for each set scroll cycle; and processing the required timing in the scroll cycle by the information processing. Means for informing the user of setting the display data write start timing. The image display device, wherein the information processing means is configured to determine a write timing of display data to the display data storage means based on a required timing notified from the scroll cycle timing notification means. .   The scroll cycle timing notifying means is configured to notify a scroll start timing to the information processing means when the read start position is changed by the read start position changing means. Image display device.   The scroll cycle timing notifying means sets a scroll start flag at a scroll start timing, detects reading of the scroll start flag of the information processing means, and resets the scroll start flag when detecting reading of the scroll start flag. The image display device according to claim 2, wherein the image display device is configured as follows.   2. The scroll cycle timing notifying unit is configured to notify the information processing unit of notification information indicating a scroll elapsed period corresponding to an elapsed time from the scroll start timing. 3. Image display device.   The image display device according to claim 2, wherein the scroll cycle timing notifying unit is configured to output the notifying information as an interrupt signal to the information processing unit.   The read start position changing means includes a scroll cycle setting means for setting a scroll cycle, and a read for determining a read start position based on a step amount set when the scroll cycle set by the scroll cycle setting means is reached. The image display device according to any one of claims 1 to 5, further comprising a start position determining unit.

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