JP2001195226A - Display method and display driver device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display method and a display driver device capable of speeding up a scroll operation independently of the capability of a CPU. SOLUTION: In the display method for transmitting display data for each vertically divided screen through upper and lower drivers 3A and 3B corresponding to the upper and lower screens to display devices 1A and 1B, a display memory corresponding to each upper and lower driver 3A and 3B is provided with a capacity capable of storing at least the display data, and upper side n/(n+1) of the display data which are (n+1) (n is real number (n>0) and the minimum value is a memory quantity per line) times of the upper and lower screens is written in the display memory corresponding to the upper driver, and the display data necessary for each upper and lower driver are read and transmitted to the display device 1A and 1B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display method for transmitting display data to various display devices such as a liquid crystal display device for display, and a display driver device. is there.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device uses a display driver IC which processes data sent from a CPU and sends out the data from the display device. This display driver IC
Has a display memory for storing display data from the CPU for one screen, and functions to decompose the display data stored in the display memory into segments and send it to each segment of the display device. In addition, when the number of display images increases, a space such as wiring to each common becomes insufficient, so that a method of dividing the screen into upper and lower parts and forming one screen with two display devices is adopted. Display driver I for each
C is used.

[0003]

In order to be mounted on such a liquid crystal display device, especially a small portable terminal, etc., a CPU is required.
However, there is a problem that scrolling of the screen takes a long time because of the power. Further, there is a problem that it takes time for image processing. In view of such circumstances, the present invention provides a CPU
It is an object of the present invention to provide a display method and a display driver device capable of performing high-speed scrolling irrespective of the capability of the device.

[0004]

According to a first aspect of the present invention for solving the above-mentioned problems, display data for each screen divided into upper and lower portions is transmitted to a display device via upper and lower drivers respectively corresponding to upper and lower portions. In the display method, a display memory corresponding to each of the upper and lower drivers has a capacity capable of storing display data or more, and is (n + 1) times (n is a real number (n> 0)) of both upper and lower screens, and a minimum value is a memory amount for one line. :) The upper side n / (n + 1) of the display data of (1) is written in the display memory corresponding to the upper driver, and each of the upper and lower drivers reads necessary display data and sends it to the display device. In the way.

According to a second aspect of the present invention, in the first aspect, the display data of any one of the upper and lower screens corresponding to one of the upper and lower scroll directions of the display memory at the time of vertical scrolling. The display method is characterized in that new data is written to the address next to the end address only when the data is missing. According to a third aspect of the present invention, there is provided the display method according to the first or second aspect, wherein data having overlapping display contents is simultaneously written into display memories corresponding to the upper and lower drivers.

According to a fourth aspect of the present invention, there is provided a display driver for transmitting display data for each screen divided into upper and lower parts to a display device. And the display memory corresponding to the upper driver of these display memories are (n + 1) times (n is a real number (n> 0)) of the upper and lower screens, and the minimum value is one line. The upper n / (n + 1) of the display data of the memory amount :) is written, and the lower n / (n + 1) is stored in the display memory corresponding to the lower driver.
A display driver device comprising: writing means for writing (n + 1); and upper and lower driver means for transmitting display data corresponding to the upper and lower screens to the display device.

According to a fifth aspect of the present invention, in the fourth aspect, the writing means is arranged such that at the time of up / down scrolling, one of the upper and lower screens corresponding to the respective upper and lower scroll directions of the display memory. A display driver device is characterized in that new data is written to the address next to the end address of the display data of the screen only when the data is missing. According to a sixth aspect of the present invention, there is provided a display driver device according to the fourth or fifth aspect, further comprising a data coder for simultaneously writing data to a display memory corresponding to each of the upper and lower drivers.

According to the display method and the display driver device of the present invention, high-speed scroll can be executed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, description will be made based on embodiments. Embodiment 1 FIG. 1 shows an example in which the display driver device according to Embodiment 1 is mounted on a display device such as a portable terminal.

As shown in FIG. 1, a liquid crystal display device (LCD) 1 as a display device comprises an upper screen LCD 1A and a lower screen LCD 1B, which are upper and lower screens. Lower driver I
C3B is connected by upper and lower common wires 4A and 4B and upper and lower segment wires 5A and 5B. An MPU 7 is connected to the upper and lower driver ICs 3A and 3B via a bus 6, and CS1 and CS2 as chip select lines for selecting the upper and lower driver ICs 3A and 3B, respectively.

FIG. 2 shows an example of the configuration of the upper and lower driver ICs 3A and 3B (hereinafter, referred to as the driver IC 3). The driver IC 3 includes a control circuit 11 including a command register, a command decoder, and the like, and controls an MPU access address generator 12, a display memory address generator 13, an address selector 14 for generating X and Y addresses, and an X and Y address. It has a memory controller 15, which controls the display memory 16.

The driver 3 has an MPU interface 18. The MPU interface 18 includes various signal lines from the MPU, for example, an address signal line (A), a data signal line (D), an enable signal line (E), a chip select signal line (CS1, CS2), and a read signal line. (RD), a write signal line (WR), and the like are connected, and various signals are input to the control circuit 11 and the like. The data signal is stored in the display memory 16 or the like via the data buffer 19.

On the other hand, the display data stored in the display memory 16 is output to the level shifter S22 and the segment driver 23 via the display data buffer 21. The timing of the output from the segment driver 23 to the display device is performed by the LCD timing generator 24, and the control signal from this is sent to the level shifter C25 and the common driver 26 together with the level shifter S22 and the segment driver 23. In addition, LCD
A power supply circuit 27 and a transmission circuit 28 for one drive are built in.

Here, the driver 3 further has a built-in decoder circuit 30. The decoder circuit 30 is for determining which of the upper and lower driver ICs 3A and 3B is a signal, and accepts only its own data and signals. An example of such a decoder circuit 30 is shown in FIG. As shown in the figure, the decoder circuit 30 includes two NAND circuits 3
1 and 32, and inverters 33 and 34 connected to different input terminals of the NAND circuits 31 and 32, respectively.
When an L signal is input to either CS1 or CS2, NA
The L signal is output from one of the ND circuits 31 and 32 to the OR circuit 35.
Is to enter. Also, an OR circuit 36 is provided,
The L signal is also output when the L signal enters both CS1 and CS2.

Here, by setting the registers of the drivers 3A and 3B, a driver that makes CS1 valid (for example,
The upper driver IC 3A) receives a NAND signal from the selection terminal 37.
The circuits 31 and 32 include an inverter 38 in the NAND circuit 32.
The driver for enabling the NAND circuit 31 by inputting the H signal through the interface and enabling the CS2 is provided with the selection terminal 3
7 to the NAND circuits 31 and 32 so that the L signal is input to the NAND circuit 32 via the inverter 38 and the NAN
The D circuit 32 is made valid. Thereby, CS1 and CS
2 when the combination of the L signal and the H signal enters N
The L signal is output from the AND circuit 31 and only the driver 3A is enabled. On the other hand, when the H and L signals are input to CS1 and CS2, the L signal is output from the NAND circuit 32 and only the driver 3B is enabled.

According to the setting of the registry, when the L signal is output from the OR circuit 36, simultaneous access to the memories of the upper and lower driver ICs is enabled, and the OR circuit 36
When the L signal is not output from the upper and lower drivers I
The operation is independent of the memory of C. Thus, when the L and L signals are input to CS1 and CS2, the L signal is output from the OR circuit, and simultaneous access to the upper and lower driver ICs 3A and 3B becomes possible.

Note that the signal from the OR circuit 35 and the signal from the OR circuit 36 may be combined by an AND circuit so that access to the memory is enabled when an L signal is output from any of them. Here, each display memory 16 of the upper and lower driver ICs 3A and 3B is
A and has a capacity that can store more than the capacity of the display data displayed on both the lower screen LCD 1B. The upper side n / (n + 1) of the display data of (n + 1) times (n is a real number (n> 1) and the memory amount for one minimum line :) of both upper and lower screens
Is stored in the display memory 16 corresponding to the upper driver IC 3A, and the lower n / (n + 1) of the display data is stored in the lower driver IC 3A.
It is stored in the display memory 16 corresponding to 3B.
In the present embodiment, for example, each display memory 16 has a capacity of 1.5 screens of the LCD 1 and has a capacity of 1.5 screens.
The upper 2/3 of the display data for the screen is stored in the display memory 16 corresponding to the upper driver, and the lower 2/3 of the display data for 1.5 screens is stored in the display memory 16 corresponding to the lower driver. I made it. At this time, writing to the display memory 16 can be simultaneously performed to the upper and lower driver ICs 3A and 3B by using the above-described decoder circuit 30, and is limited to a range permitted by the memory, for example, 1.5 screens. Although it is a range, high-speed scrolling can be performed. Further, the display memory 16 can set a display start address.

Such upper and lower driver ICs 3A and 3B
FIG. 4 shows an image displayed on the LCD 1 using the LCD.
It is. As shown in FIG. 4, the display data of the upper screen image 1 and the lower screen image 2 are written into the display memory 16 of the upper driver IC 3A, and the lower screen image 2 and the lower image 2 are stored in the display memory 16 of the lower driver IC 3B. It is assumed that the image 3 following the image 2 has been written, and the display memory 1 of the upper driver IC 3A is written.
6 to the upper screen LCD 1A, and the image 2 from the display memory 16 of the lower driver IC 3B to the lower screen LCD 1A.
1B. In addition, the start address is managed so as to be continuous after the last address of the display data composed of the image 1 and the image 2 or the image 2 and the image 3, and the upper and lower driver ICs 3A and 3B respectively
Output display data for one continuous screen.

Here, control when the screen is scrolled down will be described. In this case, the display data to be transmitted by the upper driver IC 3A and the lower driver IC 3B exists in the display memory 16 until scrolling to the end of the image 3, so that high-speed scrolling can be performed without rewriting the data in the display memory 16. . When scrolling is performed to a range where no data exists, the same data update as in the related art is required.

The addresses written to the display memory 16 of each of the upper and lower driver ICs 3A and 3B may be different, or the display memory 16 may be two memories whose addresses are separately controlled. In FIG. 5, the display memory 16 is composed of a display memory 16A and a display memory 16B whose addresses are independently controlled, and the display data of the image 1, image 2 and image 3 to be written first are stored in the upper and lower driver ICs 3A and 3B. This is different in the display memory 16. In this case, the lower driver I
The display memory 16 for C3B can be realized by writing addresses offset by a predetermined amount. The same applies to the subsequent scrolling process.

In the above example, the display memory 16A
And 16B, extra data is provided for each half screen. However, if extra data of at least one line is retained, scrolling can be speeded up accordingly. It goes without saying that whether the driver IC and the LCD described in the second embodiment are monochrome or color is not particularly limited.

(Embodiment 2) FIG. 6 shows an example in which a display driver device according to Embodiment 2 is mounted on a display device such as a portable terminal, and FIG. 7 is a block diagram showing the configuration of a driver IC. As shown, in the present embodiment, the decoder circuit 30A is connected to the outside of the upper and lower driver ICs 16A and 16B,
That is, the MPU 7 and the upper and lower driver ICs 53 and 53B
And upper and lower driver ICs 16A and 16B except that they do not include the decoder circuit 30A.
The configuration is the same as that of the first embodiment described above.

FIG. 8 shows control of screen scrolling by the driver ICs 16A and 16B. In the present embodiment, as shown in FIG. 8, the decoder circuit 30A includes two NAND circuits 31, 32 similarly to the decoder circuit 30.
And inverters 33 and 34 connected to different input terminals of the NAND circuits 31 and 32. When the L signal is input to CS1, the L signal is output from the NAND circuit 31 to A.
When the L signal is output from the AND circuit 41 and the L signal is input to CS2, the NAND circuit 32
, The L signal enters the AND circuit 42, and the L signal is output from the AND circuit 42. Also, an OR circuit 36 is provided so that when an L signal is input to both CS1 and CS2, the L signal is input to both AND circuits 41 and 42, and an L signal is output from both AND circuits 41 and 42. It has become. Here, the AND circuit 41 is connected to the CS line of the upper driver IC 53A, and the AND circuit 42
Since the lower driver IC 53B is connected to the CS line of the lower driver IC, the driver ICs 53A and 53B are selected by the signals of CS1 and CS2. When the driver ICs 53A and 53B have two CS lines, one of them may be fixed to an H signal or the configuration of the decoder circuit may be changed as appropriate.

In this embodiment as well, high-speed scrolling can be realized as in the first embodiment. It goes without saying that whether the driver IC and LCD of the second embodiment described above are monochrome or color is not particularly limited.

[0025]

As described above, according to the present invention, the display memory corresponding to each of the upper and lower drivers has a capacity capable of storing display data or more, and is (n + 1) times (n is a real number (n> 0)) of the upper and lower screens. , The minimum value is the amount of memory for one line :) The upper n / (n + 1) of the display data is written into the display memory corresponding to the upper driver, and the upper and lower drivers read out the necessary display data and send it to the display device. By doing so, high-speed scrolling can be performed within the range allowed by the display memory, irrespective of the capacity of the CPU.

[Brief description of the drawings]

FIG. 1 shows a display driver device according to an embodiment of the present invention.
It is a figure showing the example installed in the display devices, such as a personal digital assistant.

FIG. 2 is a block diagram illustrating a configuration of a display driver IC according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an example of a decoder circuit of the driver IC according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a control example of screen scrolling by the driver IC according to the first embodiment of the present invention.

FIG. 5 is a diagram showing another control example of screen scrolling by the driver IC according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating an example in which a display driver device according to a second embodiment of the present invention is mounted on a display device such as a mobile terminal.

FIG. 7 is a block diagram illustrating a configuration of a driver IC according to the embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating an example of a decoder circuit according to a second embodiment of the present invention.

[Explanation of symbols]

1,1A, 1B LCD 3,3A, 3B, 53,53A, 53B Display driver IC 16,16A, 16B Display memory 30,30A Decoder circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Haruyoshi Fujii 1-8-8 Nakase, Mihama-ku, Chiba-shi, Chiba F-term (reference) in Seiko Instruments Co., Ltd.

Claims (6)

[Claims] 1. A display method for transmitting display data for each screen divided into upper and lower parts to a display device via upper and lower drivers respectively corresponding to upper and lower parts, wherein a display memory corresponding to each of the upper and lower drivers is stored more than display data. (N + 1) times (n is a real number (n
> 0), the minimum value is to write the upper side n / (n + 1) of the display data of the memory amount for one line :) into the display memory corresponding to the upper driver, and read the display data required by each of the upper and lower drivers. A display method, characterized in that the display is transmitted to a display device. 2. The display device according to claim 1, wherein, when the display data of any one of the upper and lower screens corresponding to one of the upper and lower scroll directions of the display memory during the up and down scrolling is lacking, the end portion of the display memory is lost. A display method characterized by writing new data to an address following an address. 3. The display method according to claim 1, wherein data having overlapping display contents is simultaneously written into display memories respectively corresponding to the upper and lower drivers. 4. A display driver device for transmitting display data for each screen divided into upper and lower screens to a display device, the display driver having a capacity corresponding to the display of each of the upper and lower screens and having a capacity capable of storing more than the display data. Memory and
The display memory corresponding to the upper driver of these display memories has (n + 1) times the upper and lower screens (n is a real number (n> 0)).
Writing means for writing the upper n / (n + 1) of the display data of the memory amount for one line :) and writing the lower n / (n + 1) in the display memory corresponding to the lower driver; A display driver device comprising: upper and lower driver means for transmitting display data corresponding to the upper and lower screens to the display device. 5. The display device according to claim 4, wherein said writing means displays a screen only when one of upper and lower screens corresponding to one of upper and lower scroll directions of said display memory is missing during vertical scrolling. A display driver device for writing new data to an address next to an address at the end of the data. 6. The display driver device according to claim 4, further comprising a data coder for simultaneously writing data to display memories respectively corresponding to the upper and lower drivers.