JP2011039302A - Buffer control circuit, display controller and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a buffer control circuit that can prevent the transfer of stream image data from being interrupted, a display controller and an electronic apparatus. <P>SOLUTION: The buffer control circuit includes a writing circuit 220 for writing the stream image data SD on a line buffer 200, and a reading circuit 230 for reading the image data written on the line buffer 200. When the number of pixels in a horizontal direction of the stream image data SD is H, and the number of threshold pixels for mode switching is N, in a first mode of H>N, the writing circuit 220 writes the image data SD on the line buffer 200 set in a double buffer, having first and second buffer regions BA1 and BA2; and in a second mode of H≤N, the writing circuit writes the image data SD on the line buffer 200 set in a single buffer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a buffer control circuit, a display controller, an electronic device, and the like.

  A display controller that performs display control is generally used for a display device that displays various images (for example, a display controller disclosed in Patent Document 1). The display controller buffers stream image data (image data in a broad sense) input from a host or the like with a line buffer or the like and stores it in a video memory, and performs display control based on the image data. At this time, there is a problem that the transfer of the stream image data from the host or the like to the display controller may be interrupted depending on conditions such as the transfer speed to the video memory.

  For example, as a technique for buffering stream image data, a double buffer technique in which a line buffer is divided into two buffer areas, writing to one of the two buffer areas, and reading from the other is alternately performed can be considered. However, with this double buffer method, stream image data cannot be written to the buffer area until the transfer from one buffer area to the video memory is completed. Therefore, when the transfer rate of data transfer from the line buffer to the video memory is slow, transfer of stream image data from the host or the like to the display controller may be interrupted.

JP 2006-18002 A

  According to some aspects of the present invention, it is possible to provide a buffer control circuit, a display controller, an electronic device, and the like that can prevent interruption of transfer of stream image data.

  One aspect of the present invention is a write circuit that receives stream image data and writes the stream image data to a line buffer; a read circuit that reads image data written in the line buffer; And the stream circuit data has a horizontal pixel count of H (H is a natural number) and a mode switching threshold pixel count of N (N is a natural number), the write circuit satisfies H> N In the first mode, the writing process is performed on the line buffer set as a double buffer having a first buffer area and a second buffer area. In the second mode where H ≦ N, a single buffer is used. The present invention relates to a buffer control circuit that performs the writing process on the set line buffer.

  According to one aspect of the present invention, in the first mode where H> N, the line buffer is set to a double buffer having first and second buffer areas, and the line buffer set to the double buffer is set to the double buffer. On the other hand, a writing process is performed. On the other hand, in the second mode in which H ≦ N, the line buffer is set as a single buffer, and writing processing is performed on the line buffer set as the single buffer. As a result, it is possible to suppress the interruption of the transfer of stream image data from the host or the like.

  In one embodiment of the present invention, when the number of pixels in the vertical direction of the stream image data is V (V is a natural number), in the first mode, the writing circuit has a horizontal number of pixels of H. And the image data with the number of pixels in the vertical direction j (j is a natural number where j ≦ V) is written in one of the first buffer area and the second buffer area, and the readout circuit has the number of pixels in the horizontal direction Is read out from the other of the first buffer area and the second buffer area, and in the second mode, the writing circuit counts the number of pixels in the horizontal direction. Is written to the line buffer set as a single buffer, and the readout circuit has a horizontal pixel count of H and a vertical pixel count of V. The image data may be read out from the line buffer is set to a single buffer.

  In this way, in the first mode, it is possible to perform the writing process and the reading process for the line buffer set as the double buffer. In the second mode, it is possible to perform a writing process and a reading process for a line buffer set as a single buffer.

  In one aspect of the present invention, the threshold pixel number N may be decreased as the vertical pixel number V of the stream image data is increased.

  In one embodiment of the present invention, the storage capacity of the first buffer area is a storage capacity corresponding to i × j pixels (i is a natural number of i ≧ H), and the storage capacity of the second buffer area is If the storage capacity corresponds to i × j pixels, N × V ≦ i × 2j may be satisfied.

  According to these aspects of the present invention, it is possible to set the threshold pixel number N, set the first mode when H> N based on the set N, and set the second mode when H ≦ N. In the second mode, it is possible to write image data in which the number of pixels in the horizontal direction is H and the number of pixels in the vertical direction is V in a line buffer set as a single buffer.

  In one aspect of the present invention, a register that sets a horizontal pixel count H and a vertical pixel count V of the stream image data is included. Based on the setting value of the register, the first mode and the The second mode may be switched.

  In this way, the threshold pixel number N is set based on the set value of the register, and the first mode of H> N and the second mode of H ≦ N are switched based on the set N. it can.

  Another embodiment of the present invention relates to a display controller including any of the buffer control circuits described above.

  Another aspect of the present invention may include a host interface circuit that receives the stream image data from the host, and a memory controller that writes the image data read by the read circuit to an image memory.

  In another aspect of the present invention, in the first mode, the read circuit reads image data from the line buffer in a burst mode, and the memory controller reads image data from the read circuit in the image memory. May be written in burst mode.

  Another aspect of the invention relates to an electronic device including any of the display controllers described above.

Configuration example of display controller. 2A and 2B are explanatory diagrams of a comparative example. The timing chart of a comparative example. 2 is a configuration example of a buffer control circuit according to the present embodiment. 5A and 5B are explanatory diagrams of an operation example of the buffer control circuit in the double buffer mode. The timing chart example in double buffer mode. 7A and 7B are explanatory diagrams of an operation example of the buffer control circuit in the single buffer mode. Timing chart example in single buffer mode. An example of setting the threshold pixel number N. 3 shows a detailed configuration example of a buffer control circuit. The operation example of the detailed structural example of a buffer control circuit. 6 is a timing chart example in a double buffer mode of a detailed configuration example of a buffer control circuit. 9 is a timing chart example in a single buffer mode of a detailed configuration example of a buffer control circuit. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration Example of Display Controller FIG. 1 shows a configuration example of a display controller (integrated circuit device). The display controller 100 illustrated in FIG. 1 includes a host I / F circuit 110 (host interface circuit), a bus controller 130, a memory controller 140, a display control unit 150, a line buffer 200, and a buffer control circuit 210.

  The host I / F circuit 110 performs various interface processes with the host 10. For example, an interface signal such as a data signal, an address signal, or a write / read signal is exchanged with the host 10 to realize an interface with the host 10. The host I / F circuit 110 receives stream image data (image data in a broad sense) from the host 10.

  The line buffer 200 (buffer, memory) is configured by an SRAM, for example, and buffers (temporarily stores) stream image data. The buffer control circuit 210 performs read / write control of the line buffer 200. Specifically, the stream image data input via the host I / F circuit 110 is written into the line buffer 200. Further, the buffer control circuit 210 reads the image data written in the line buffer 200 and transfers the read image data to the bus controller 130.

  The bus controller 130 controls data transfer (data communication) between components via the internal bus. The bus controller 130 includes, for example, a FIFO, and transfers image data read from the line buffer 200 to the memory controller 140 via the FIFO.

  The memory controller 140 performs read / write control on the image memory 20 (video memory, VRAM, for example, SDRAM). Specifically, the image data from the bus controller 130 is written into the image memory 20. Further, the image data stored in the image memory 20 is read, and the read data is transferred to the display control unit 150.

  The display control unit 150 performs display control of the electro-optical device 30 (for example, a liquid crystal display or an electrophoretic display) based on the image data from the memory controller 140. For example, the display control unit 150 outputs a display data signal and a control signal (such as a synchronization signal) to the electro-optical device 30. The electro-optical device 30 includes, for example, an electro-optical panel such as a liquid crystal panel or an electrophoretic panel, a data driver (source driver) that drives a data line (source line) of the electro-optical panel, and a scanning line (gate line) of the electro-optical panel. ) May be included.

  The display controller according to the present embodiment is not limited to the configuration shown in FIG. 1, and various components such as omitting some of the components (for example, a bus controller and a memory controller) and adding other components. Variations are possible. For example, the display controller 100 and the image memory 20 may be configured by separate IC chips, and the image memory 20 may be built in the display controller 100. The display controller 100 may include an image processing circuit that performs image rotation processing and the like.

2. Comparative Example First, a comparative example of this embodiment will be described with reference to FIGS. 2 (A), 2 (B), and 3. FIG. As shown in FIG. 2A, it is assumed that stream image data SD of an image of 64 pixels × 600 lines is input. The stream image data SD is composed of data of the first to 600th lines L1 to L600.

  As shown in FIG. 2B, first and second buffer areas BA1 and BA2 each having a storage capacity of 4096 pixels × 32 lines are set in the address space LB of the line buffer. That is, the line buffer has a double buffer configuration. Then, the data of the lines L1 to L32 is written in the buffer area BA1. In addition, the data of the lines L33 to L64 is written in the second buffer area BA2 of the address space LB.

  FIG. 3 schematically shows a timing chart of the comparative example. In FIG. 3, data L1 to L600 are sequentially received as stream image data. As shown in C1, the data of L1 to L32 written to the buffer area BA1 is burst to the image memory as shown in C3 when the data of L33 to L64 is written to the buffer area BA2 as shown in C2. Transferred. For example, in burst transfer, data at all addresses of BA1 is transferred to the image memory.

  At this time, the data transfer period TS of the stream image data L33 to L64 becomes shorter as the number of pixels in the horizontal direction of the image decreases. For this reason, depending on the number of pixels in the horizontal direction of the image, the data transfer period TS of L33 to L64 may be shorter than the transfer period TB of burst transfer (the burst transfer of L1 to L32 is shortened, resulting in burst transfer). Data transfer speed will be reduced). In this case, since the data of L65 to L96 indicated by C4 cannot be written in the buffer area BA1 until the burst transfer is completed, the transfer of the stream image data is interrupted. In order to prevent the interruption, it becomes necessary to reduce the transfer speed of the stream image data.

3. Configuration Example FIG. 4 shows a configuration example of a buffer control circuit that can solve the above problem. The buffer control circuit 210 shown in FIG. 4 includes a write circuit 220 (write circuit), a read circuit 230 (read circuit), and a mode control unit 240. The buffer control circuit 210 performs buffer control in accordance with the number of pixels in the horizontal direction of the stream image data SD (image data in a broad sense) to prevent the transfer of the stream image data SD from being interrupted. Circuit.

  The mode control unit 240 switches between a double buffer mode (first mode in a broad sense) and a single buffer mode (second mode in a broad sense). Specifically, when the horizontal pixel count H of the stream image data SD is larger than the threshold pixel count N (H> N), the first mode is set. When the horizontal pixel count H of the stream image data SD is equal to or smaller than the threshold pixel count N (H ≦ N), the second mode is set (H and N are natural numbers). For example, the mode control unit 240 performs mode switching by outputting a mode switching signal MOD to the writing circuit 220 and the reading circuit 230. Alternatively, the mode control unit 240 may output a buffer selection signal WSB for switching the first and second buffer areas BA1 and BA2 of the line buffer 200, and mode switching is performed by controlling the WSB according to the mode. May be performed.

  The writing circuit 220 receives the stream image data SD and performs processing (writing processing and writing processing) for writing the SD into the line buffer 200. Specifically, the writing circuit 220 generates an address WAD (write address) and data WD (image data) based on the stream image data SD, and writes the data WD to the address WAD of the line buffer 200. In the double buffer mode, the line buffer 200 is set as a double buffer, and the first and second buffer areas BA1 and BA2 are set in the line buffer 200. The writing circuit 220 alternately writes the stream image data SD to the buffer areas BA1 and BA2. In the single buffer mode, the writing circuit 220 writes SD to the line buffer 200 set as a single buffer.

  The read circuit 230 performs processing (read processing, read processing) for reading image data written in the line buffer 200. Specifically, the read circuit 230 generates an address RAD, reads data RD (image data) stored in the address RAD of the line buffer 200, and outputs the read data RD to a bus controller or the like. In the double buffer mode, the read circuit 230 reads image data from the line buffer 200 set as a double buffer. In the single buffer mode, image data is read from the line buffer 200 set as a single buffer.

  For example, the line buffer 200 has an address space LB specified by consecutive addresses 0H to 3FFFH (addresses 0 to 16383, for example, 16 bits for each address). In the double buffer mode, the writing circuit 220 writes the image data by designating the addresses 0H to 1FFFH, and the reading circuit 230 reads the image data by designating the addresses 2000H to 3FFFH. Alternatively, the writing circuit 220 designates addresses 2000H to 3FFFH and writes image data, and the reading circuit 230 designates addresses 0H to 1FFFH and reads image data. With these processes, addresses 0H to 1FFFH are set in the first buffer area BA1, addresses 2000H to 3FFFH are set in the second buffer area BA2, and the line buffer 200 is set in the double buffer. In the single buffer mode, the writing circuit 220 writes the image data by designating the addresses 0H to 3FFFH, and the reading circuit 230 reads the image data by designating the addresses 0H to 3FFFH. With this process, the line buffer 200 is set to a single buffer.

  Note that the buffer control circuit according to the present embodiment is not limited to the configuration shown in FIG. 4, and various modifications such as omitting some of the components or adding other components are possible. For example, the mode switching circuit 240 may be omitted, and the function of the mode switching circuit 240 may be realized by the writing circuit 220.

4). Operation Example An operation example of the buffer control circuit in the double buffer mode will be described with reference to FIGS. 5A, 5B, and 6. FIG. In the following, a case where burst transfer (data transfer in burst mode) is performed from the line buffer to the image memory will be described as an example. However, in this embodiment, data transfer in another mode may be performed from the line buffer to the image memory.

  As shown in FIG. 5A, stream image data of an image in which the number of pixels in the horizontal direction (scanning direction) is H = 512 and the number of pixels in the vertical direction (number of lines, number of scanning lines) is V = 1200. Assume that SD is supplied. This stream image data SD is composed of data of the first to 1200th lines L1 to L1200, and the data of each line of L1 to L1200 is composed of data of H = 512 pixels. Here, it is assumed that the threshold pixel number (threshold bit number) is N = 128. At this time, since H = 512> N = 128, this embodiment is set to the double buffer mode.

  As shown in FIG. 5B, buffer areas BA1 and BA2 are set in the address space LB of the line buffer. Each of the buffer areas BA1 and BA2 has a storage capacity corresponding to image data in which the number of pixels in the horizontal direction is i and the number of pixels in the vertical direction is j (i is a natural number where i ≧ H, j is j ≦ j). Natural number of V). For example, BA1 and BA2 each have a storage capacity of 4096 bits × 32 bits. When the data length of each pixel is 1 bit, the storage capacity of BA1 and BA2 corresponds to the capacity of image data of i × j = 4096 pixels × 32 lines. At this time, image data for j = 32 lines is alternately written in the buffer areas BA1 and BA2. For example, the data of the lines L1 to L32 are sequentially written in BA1 from the head address of BA1. In BA2, the data of lines L33 to L64 are sequentially written from the head address of BA2.

  FIG. 6 schematically shows an example of a timing chart in the double buffer mode. As shown in FIG. 6, when the stream image data of lines L33 to L64 is written into the buffer area BA2, burst transfer is performed from the buffer area BA1 to the image memory. At this time, the data transfer period TS (reception period) for 32 lines becomes longer as the number of pixels H in the horizontal direction of the stream image data is larger. In the present embodiment, when the condition of H> N is satisfied, the double buffer mode is set so that (transfer period TS of L33 to L64)> (transfer period TB of burst transfer of BA1) can be achieved.

  An operation example of the buffer control circuit in the single buffer mode will be described with reference to FIGS. 7A, 7B, and 8. FIG. As shown in FIG. 7A, it is assumed that stream image data SD with H = 64 pixels and V = 1200 pixels is supplied. The data of each line is composed of H = 64 pixel data. If the threshold pixel number is N = 128, since H ≦ N, this embodiment is set to the single buffer mode.

  As shown in FIG. 7B, the address space LB of the line buffer is set to a single buffer. That is, the line buffer is controlled as one buffer having a storage capacity corresponding to image data of i × 2j = 4096 pixels × 64 lines. Then, the data of the lines L1 to L1200 are sequentially written in the line buffer from the head address, and the entire stream image data is written in the line buffer.

  FIG. 8 schematically shows an example of a timing chart in the single buffer mode. As shown in FIG. 8, after the data of the lines L1 to L1200 is written into the line buffer, burst transfer is performed from the line buffer to the image memory. Thus, since the entire stream image data is written in the line buffer set as the single buffer, the stream image data can be received without interruption.

  In the above description, the case where the data length of each pixel is 1 bit (1 bpp: 1 bit per pixel) has been described as an example. However, in this embodiment, the data length of each pixel is another number of bits. Also good. For example, the data length of each pixel may be 2 bits (2 bpp) and 4 bits (4 bpp). At this time, the number of pixels in each line of the buffer area may be i = 1024 pixels, 512 pixels, and the threshold pixel number may be N = 64 pixels, 32 pixels.

  Here, as described in the above comparative example, when a double buffer is used, transfer of stream image data from the host or the like may be interrupted depending on the number of pixels in the horizontal direction of the stream image data. For this reason, there is a problem that the transfer rate is reduced due to the interruption or the transfer rate needs to be reduced in order to prevent the interruption.

  In this regard, according to the present embodiment, in the H> N double buffer mode, the writing process is performed on the line buffer 200 set as a double buffer having the buffer areas BA1 and BA2. On the other hand, in the single buffer mode with H ≦ N, a write process is performed on the line buffer 200 set as a single buffer.

  Thereby, it becomes possible to prevent the transfer of stream image data from the host or the like from being interrupted. That is, in the double buffer mode, since the horizontal pixel count H is larger than the threshold pixel count N, burst transfer of the other buffer area can be completed during writing of one buffer area. Further, when the horizontal pixel count H is equal to or smaller than the threshold pixel count N, the entire stream image data can be written to the line buffer by setting the single buffer mode. In this way, by switching the mode with the threshold pixel number N as a boundary, it is possible to prevent the transfer of stream image data from being interrupted and to improve the transfer speed.

  Specifically, in the double buffer mode, H × j pixel image data is written to one of the buffer areas BA1 and BA2 of the line buffer 200, and H × j pixel image data is read from the other of the buffer areas BA1 and BA2. It is. On the other hand, in the single buffer mode, H × V pixel image data is written to the line buffer 200, and H × V pixel image data is read from the line buffer 200.

  In this way, in the double buffer mode, the line buffer 200 can be set as a double buffer, and a write process and a read process can be performed on the line buffer 200 set as a double buffer. On the other hand, in the single buffer mode, the line buffer 200 can be set as a single buffer, and write processing and read processing can be performed on the line buffer 200 set as a single buffer.

  Here, in the present embodiment, the threshold pixel number N may be reduced as the vertical pixel number V of the stream image data is increased. Specifically, when the storage capacities of the buffer areas BA1 and BA2 are storage capacities corresponding to i × j pixels, N satisfying N × V ≦ i × 2j may be set.

  For example, as shown in FIG. 9, if the data length of each pixel is 1 bit, N = 256 when 1 ≦ V ≦ 1024, and N = 128 and 2048 <V when 1024 <V ≦ 2048. If ≦ 4096, N = 64 may be set. In either case, N × V ≦ i × 2j is satisfied.

  In this way, it is possible to set the threshold pixel number N, set the double buffer mode when H> N based on the set N, and set the single buffer mode when H ≦ N. Specifically, by satisfying N × V ≦ i × 2j, H × V stream image data can be stored in the i × 2j line buffer 200 in the single buffer mode of H ≦ N.

  In the present embodiment, the above-described mode control unit 240 shown in FIG. 4 may include a register, and the number of pixels H and V may be set as a register value from the host or the like to the register. Then, the threshold pixel number N may be set based on the set register values H and V.

  In the present embodiment, the mode control unit 240 may acquire information on the number of pixels H and V based on the stream image data, and set N based on the acquired H and V. Alternatively, N may be directly set in the mode control unit 240 from a host or the like, or a predetermined N may be set in advance at the time of design or the like.

5). Detailed Configuration Example FIG. 10 shows a detailed configuration example of the buffer control circuit of this embodiment. The buffer control circuit includes a sequencer 300, a write control circuit 310, a read control circuit 320, an unpack circuit 330, first to third selectors MUX1 to MUX3, and first and second read / write circuits RW1 and RW2. Note that the buffer control circuit of the present embodiment is not limited to this configuration, and some of the components are omitted (for example, a sequencer, first to third selectors), or other components are added. Various modifications such as these are possible.

  The sequencer 300 is for switching modes and controlling each component of the buffer control circuit. Specifically, the sequencer 300 includes a register 302, a horizontal counter 304, and a vertical counter 306. The sequencer 300 outputs the mode switching signal MOD and the buffer switching signal WBS based on the register value of the register 302 and the count values of the horizontal counter 304 and the vertical counter 306, and controls the operation timing of each component. Or

  The number of pixels H and V of the stream image data SD is set in the register 302 from the host or the like. The horizontal counter 304 (pixel counter) counts the number of pixels in each line of the stream image data SD. The vertical counter 306 (line number counter) counts the number of lines of the stream image data SD. These counters count based on the dot clock CLK, for example. The count is performed during the period (SD reception state) in which the enable signal DATAEN of the stream image data SD is active (first logic level).

  The write control circuit 310 controls a write process to the line buffer 200. Specifically, the write control circuit 310 includes an address generation circuit 312 that outputs a write address WAD. The write control circuit 310 outputs select signals SEL1, SEL2 and write request signals WRQ1, WRQ2.

  The read control circuit 320 controls read processing from the line buffer 200. Specifically, the read control circuit 320 includes an address generation circuit 322 that outputs a read address RAD. Further, the read control circuit 320 outputs a select signal SEL3 and read request signals RRQ1 and RRQ2.

  Upon receiving SEL1, the selector MUX1 selects either the address WAD or RAD, and outputs the selected address as AD1. The selector MUX2 receives SEL2, selects one of the addresses WAD and RAD, and outputs the selected address as AD2.

  The unpack circuit 330 unpacks (divides) the stream image data SD into data corresponding to each address of the line buffer 200, and outputs the unpacked data as write data WD. For example, when the data length of each address is 16 bits and the data length of each pixel is 1 bit, the stream image data SD is unpacked every 16 pixels of data.

  The read / write circuits RW1 and RW2 perform writing to the buffer areas RA1 and RA2 and reading from the RA1 and RA2. RW1 writes data WD to address AD1 when write request signal WRQ1 is active. RW1 reads data RD1 from address AD1 when read request signal RRQ1 is active. RW2 writes data WD to address AD2 when write request signal WRQ2 is active. RW2 reads data RD2 from address AD2 when read request signal RRQ2 is active.

  The selector MUX3 receives SEL3, selects either data RD1 or RD2, and outputs the selected data as read data RD.

  The function of the mode control unit is realized, for example, when the sequencer 300 outputs signals WBS and MOD. For example, the write control circuit 310 outputs the address WAD and signals WRQ1 and WRQ2, the selectors MUX1 and MUX2 select the address WAD, and the read / write circuits RW1 and RW2 write the data WD to the address WAD. It is realized with. For example, the read control circuit 320 outputs the address RAD and signals WRQ1 and WRQ2, the selectors MUX1 and MUX2 select the address RAD, and the read / write circuits RW1 and RW2 receive the data RD1 and RD2 from the address RAD. Realized by reading.

  FIG. 11 shows an operation example of the buffer control circuit having a detailed configuration example. As shown in FIG. 11, in the double buffer mode (first mode), MOD = 0 is output and WBS = 0 or 1 is output. When WBS = 0, AD1 = WAD, AD2 = RAD, and RD = RD2 are selected. Then, WRQ1 = RRQ2 = 1 and WRQ2 = RRQ1 = 0 are output, data is written to the buffer area BA1, and data is read from the buffer area BA2. On the other hand, when WSB = 1, AD1 = RAD, AD2 = WAD, and RD = RD1 are selected. Then, WRQ1 = RRQ2 = 0 and WRQ2 = RRQ1 = 1 are output, read from the buffer area BA1, and write to the buffer area BA1.

  In the single buffer mode (second mode), MOD = 0 is output and WBS = 0 is output. At the time of writing, AD1 = AD2 = WAD is selected. Then, WRQ1 = WRQ2 = 1 and RRQ1 = RRQ2 = 0 are output, and writing is performed to the buffer areas BA1 and BA2. On the other hand, at the time of reading, AD1 = AD2 = RAD is selected, and RD1 or RD2 is selected as RD. Then, WRQ1 = WRQ2 = 0 and RRQ1 = RRQ2 = 1 are output, and reading is performed from the buffer areas BA1 and BA2.

  FIG. 12 shows an example of a timing chart in the double buffer mode. In FIG. 12, a case where N = 64, H = 100 (> N), 1 bpp (bit per pixel), and 1 address = 16 bits will be described as an example.

  As indicated by A1 in FIG. 12, the count value VC of the vertical counter (V counter) is counted up in accordance with the number of scanning lines of stream image data. Further, the count value HC of the horizontal counter (H counter) is counted up according to the number of pixels in each line. As shown in A2, when VC = 0 to 31, a buffer selection signal WBS = 0 is output, and writing to addresses 0 to 8191 in the buffer area BA1 is selected. For example, pixel data corresponding to HC = 96 to 107 (abbreviated as 96 etc. in FIG. 12) as shown at A3 is written to address 5 of BA1 as shown at A4. Since H = 100, for example, 0 (zero) is written as pixel data corresponding to HC = 100 to 107.

  As shown in A5, when VC = 32 to 64, WBS = 1 is output, and writing to addresses 8192 to 16383 in the buffer area BA2 is selected. Further, as indicated by A6, the read request signal RRQ = 1 is output, and the data at addresses 0-8191 of BA1 are sequentially burst transferred.

  FIG. 13 shows an example of a timing chart in the single buffer mode. In FIG. 13, a case where N = 64, H = 32 (≦ N), V = 100, 1 bpp (bit per pixel), and 1 address = 16 bits will be described as an example.

  As shown in B1 of FIG. 13, WBS = 0 is output, and writing to addresses 0-16383 of the line buffer is performed. Specifically, as shown in B2, stream image data of one screen (one frame) with VC = 0 to 99 is written to addresses 0 to 299 of the line buffer set as a single buffer. Then, as indicated by B3, RRQ = 1 is output, and data at addresses 0 to 16383 of the single buffer are sequentially burst transferred.

  The stream image data of the next screen is received after the burst transfer is completed. For example, the host I / F circuit outputs a busy signal to the host during burst transfer, and outputs a polling signal for prompting the host to start transfer of stream image data after the burst transfer ends. Then, the host receives the polling signal and starts transferring the stream image data.

6). Electronic Device FIG. 14 shows a configuration example of an electronic device including the display controller of this embodiment. The electronic apparatus includes a host 10, a display controller 100, an electro-optical device 30, a storage unit 60, an operation unit 70, and a communication unit 80. The present embodiment is not limited to this configuration example, and various modifications may be made such as omitting some of the components (for example, a communication unit) or adding other components. .

  As the electronic device of this embodiment, application to a mobile phone terminal, a portable information terminal, an electronic book terminal, a portable game terminal, a digital photo frame, etc. can be assumed, for example.

  The host 10 is realized by a CPU, for example, and supplies stream image data to the display controller 100 and controls each component. The display controller 100 is realized by, for example, an ASIC, and supplies display data to the electro-optical device 30 or performs display control of the electro-optical device 30. The electro-optical device 30 includes a driver 32 and an electro-optical panel 34. The driver 32 drives the electro-optical panel 34 by outputting a data voltage and a scanning signal. The electro-optical panel 34 is realized by, for example, a liquid crystal panel or an electrophoretic panel (EPD). The storage unit 60 is realized by, for example, a memory such as a ROM or a RAM, or a hard disk drive, and stores a host program, functions as a host working memory, or functions as a video memory. The operation unit 70 includes, for example, various buttons and a touch panel, and operation information is input thereto. The communication unit 80 acquires image data and moving image data by wireless communication or wired communication.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (scanning direction, double buffer mode, single buffer mode, etc.) described at least once together with different terms (horizontal direction, first mode, second mode, etc.) having a broader meaning or the same meaning ) May be replaced by the different terms anywhere in the specification or drawings. Further, the configurations and operations of the buffer control circuit, the display controller, the electronic device, and the like are not limited to those described in this embodiment, and various modifications can be made.

10 hosts, 20 image memories, 30 electro-optic devices, 32 drivers,
34 electro-optical panel, 60 storage unit, 70 operation unit, 80 communication unit,
100 display controller, 110 host interface circuit,
130 bus controller, 140 memory controller,
150 display control unit, 200 line buffer, 210 buffer control circuit,
220 writing circuit, 230 reading circuit, 240 mode control unit,
300 sequencers, 302 registers, 304 horizontal counters,
306 vertical counter, 310 write control circuit, 312 address generation circuit,
320 read control circuit, 322 address generation circuit, 330 unpack circuit,
BA1 first buffer area, BA2 second buffer area,
H The number of pixels in the horizontal direction of the stream image data,
V stream image data vertical pixel count, N threshold pixel count,
MUX1 to MUX3 1st to 3rd selector

Claims (9)

A writing circuit that receives the stream image data and writes the stream image data to the line buffer;
A readout circuit for performing readout processing of image data written in the line buffer;
Including
When the number of pixels in the horizontal direction of the stream image data is H (H is a natural number) and the threshold number of pixels for mode switching is N (N is a natural number),
The writing circuit includes:
In the first mode where H> N, the writing process is performed on the line buffer set in a double buffer having a first buffer area and a second buffer area,
In the second mode in which H ≦ N, the buffer control circuit performs the writing process on the line buffer set as a single buffer. In claim 1,
When the number of pixels in the vertical direction of the stream image data is V (V is a natural number),
In the first mode,
The writing circuit uses the first buffer area of the line buffer set as a double buffer for image data having a horizontal pixel count of H and a vertical pixel count of j (j is a natural number where j ≦ V). And the reading circuit writes image data having a horizontal pixel count of H and a vertical pixel count of j to the first buffer region and the second buffer region. Read from the other of
In the second mode,
The writing circuit writes image data having a horizontal pixel count of H and a vertical pixel count of V to the line buffer set as a single buffer, and the readout circuit has a horizontal pixel count of H. A buffer control circuit, wherein image data having a vertical number of pixels of V is read from the line buffer set as a single buffer. In claim 1 or 2,
The buffer control circuit characterized in that the threshold pixel number N is reduced as the vertical pixel number V of the stream image data is increased. In claim 1 or 2,
The storage capacity of the first buffer area is a storage capacity corresponding to i × j pixels (i is a natural number of i ≧ H), and the storage capacity of the second buffer area is a storage capacity corresponding to i × j pixels. In this case, the buffer control circuit satisfies N × V ≦ i × 2j. In any one of Claims 1 thru | or 4,
A register for setting a horizontal pixel number H and a vertical pixel number V of the stream image data;
A buffer control circuit that switches between the first mode and the second mode based on a set value of the register.   A display controller comprising the buffer control circuit according to claim 1. In claim 6,
A host interface circuit for receiving the stream image data from the host;
A memory controller that writes image data read by the read circuit to an image memory;
A display controller characterized by including. In claim 7,
In the first mode,
The display controller reads image data from the line buffer in a burst mode, and the memory controller writes image data from the read circuit to the image memory in a burst mode.   An electronic device comprising the display controller according to claim 6.

Images