JPH0695651A - Crt controller - Google Patents

Abstract

PURPOSE:To provide a CRT controller capable of highspeed scrolling in an optional direction without necessity of moving a displayed image into a block by a software for preventing the passing of the range of a block area at the time of a scrolling in a Y direction. CONSTITUTION:This controller is provided with a CPU 1 for outputting the display control command of the CRT, a GC 2 for controlling plotting and display on a VRAM 3 via a conversion circuit 6 by the instruction of the CPU 1, the VRAM 3 with addresses alotted to respective area blocks so as to provide the image address space of the same-sized area whose addresses are serial next to the area block for scrolling and the conversion circuit 6 for converting an image address value nonexistent in the VRAM 3 outputted by the CG 2 into an existent address value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a CRT control device that performs directional scrolling.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the configuration of a conventional CRT control device. In the figure, 1 is a microprocessor that controls the entire system (hereinafter referred to as CPU), and 2 is a CRT based on a command from the CPU 1.
A graphic controller (hereinafter referred to as "GC") 3 for controlling drawing and display on the display unit, and 3 by the GC2, CR
7 is a video RAM (hereinafter referred to as VRAM) for drawing and displaying image data to be displayed on the T display.
It includes the screen area of multiple blocks shown in. 4 is G
According to the display address of C2, the shifter 5 which converts the parallel data output from the VRAM 3 into serial data according to the display timing and outputs the serial data is registered in the internal look-up table in accordance with the output of the shifter 4. , G, B (red, green, blue) values are output from the D / A converter. Also 1A,
1B and 1C are an address bus, a data bus and a control bus of the system, respectively, and 2A, 2B and 2C are an address bus, a data bus and a control bus which are supplied from the GC 2 to the VRAM 3, respectively.

FIG. 7 is a diagram showing an example of a conventional multi-block screen area. In the figure, block 1 is 512
As a scroll screen area (1) composed of × 512 pixels, addresses 00000 to 07FFF (16
The address 08000 to 0FFFF is assigned to the block 2 as a scroll screen area (2) made up of 512 × 512 pixels.
The scroll screen refers to a screen in which the display area sequentially moves in the X direction or the Y direction in the drawing area so that the scroll images are sequentially viewed. Similarly, blocks 3, 4, and 5
Fixed screen erluas (1), (2), and (3) each consisting of 320 × 240 pixels have an address of 10000.
~ 1257F address, 12580 ~ 14AFF address, 14
Addresses B00 to 1707F and addresses 17080 to 17FFF are assigned respectively. As the work area, addresses 17080 to 17FFF are assigned.

As shown in the screen area example of FIG. 7, the GC 2 first writes (draws) image data in a drawing area starting from a specified address in the VRAM 3 to which an address is assigned, and then performs the writing. An image is displayed in the display area which is determined by designating the display start address, the width in the X direction, and the length in the Y direction.

When the drawing and display VRAM 3 is divided into some blocks and the display is started from an arbitrary area of these arbitrary blocks for scrolling, even in the conventional CRT control device, the X direction is also concerned. Was automatically wrapped in drawing and displaying. This is because the address of the VRAM 3 is given in the horizontal and vertical scanning order of the CRT display. That is, the lower address of VRAM3 is the X-direction address,
The upper address is the Y direction address. For example, when the X-direction address changes in the range of addresses 0 to 511 in one horizontal scan, the Y-direction address increases by 1, and the X-direction address changes from 0 to 511 again. Addresses that include are consecutive.

FIG. 8 is a diagram for explaining an example of a conventional X-direction scroll. In the figure, the drawing area is 512 ×
It has a size of 512 pixels and 3 display areas.
1 each in a system that is 20x240 pixels
An example of scrolling and displaying a plurality of map data composed of 00 × 100 pixels in the X direction is shown. First, in (a) of FIG. 8, (1) is placed in the drawing area.
Draw 12 maps divided into (12). When the drawing is completed, the display of an appropriate address in the map (1), for example, the display area indicated by the broken line from the point A is started.

When scrolling in the X direction, first, the maps (17), (18) and (19) adjacent to the right side of the maps (4), (8) and (12) are drawn, and then, The instruction to update the display start address to the address slightly moved in the X direction is repeated. For example, by smoothly repeating the movement of the display start address until the point B in FIG. 8B is reached, smooth X-direction scrolling can be realized. In this case, the maps (17), (18),
The right side of (19) exceeds the display area of VRAM3,
As described above, when viewed from the GC 2, the addresses in the X direction are continuous, so if the application instructing the drawing manages them, the map (1
7), (18), and (19) on the right side are drawn in the drawing areas adjacent to the left of the maps (1), (5), and (9), and the maps (1), (2), and 3), (4), (1
7) is a display area continuous in the X direction.

When the scrolling is further repeated in the X direction, the maps (1), (5), and (9) which are no longer needed for display are displayed from the application management target as shown in FIG. 8B. The map data adjacent to the right side of the maps (17), (18), and (19) is drawn, and the display start address is updated. By repeating this process, it is possible to scroll in the X direction without paying attention to the boundary line of the VRAM. However, in the display area of the VRAM, the address next to the right end in the X direction is connected to the left end one line below in the Y direction. Therefore, when the rightward scroll is repeated, the lower limit of the VRAM area, When the leftward scroll is repeated, the upper limit of the VRAM area may be exceeded. Therefore, it is necessary to correct the position of the drawing data in the Y-direction scroll described below.

FIG. 9 is a diagram for explaining an example of a conventional Y-direction scroll. In (a) of the figure, when scrolling in the Y direction, first, the maps (9), (10), (1
Maps (1) and (12) adjacent to the bottom of each (1)
3), (14), (15), and (16) are drawn, and then the display start address is designated again in the Y direction. By repeating this periodically until reaching the point C, smooth scrolling can be realized. When repeating this scroll, if an attempt is made to draw a map adjacent to the lower part of the maps (13), (14), (15) and (16), the range of this block area will be exceeded and other block areas will be destroyed. Therefore, the memory areas from the maps (5) to (16) are block-copied upward, and the maps (13), (14),
An area for drawing a map adjacent to (15) and (16) is secured.

In this case, in order to prevent the display from being disturbed due to the contents of the area designated as the display start being rewritten one after another during the execution of the block copy, this block copy is made in advance. Before execution, copy the contents of the display area that is to be displayed now or next to the temporary display area (320 x 240 pixels) shown in a separate frame at the bottom of Fig. 9A, and then display start address. The point D which is the start address of this temporary display area is designated. In this way, FIG.
When the block copy of the memory is completed, the display start address is changed to the point E which is the address after the block copy of the display area which is currently or next to be displayed, as shown in (b) of FIG.

[0011]

However, in the conventional CRT control device as described above, the drawing VRA is used.
When M is divided into several blocks and displayed from any area of these arbitrary blocks, wrapping is automatically performed in drawing and display in the X direction, but wrapping is automatically performed in the Y direction. Therefore, the user manages the address by software processing so that the drawing and display area in the Y direction does not exceed the range of the corresponding block area. It is necessary to move the displayed image data and then draw the subsequent images.
Software processing is complicated for Y-direction scrolling,
There was a problem that high speed processing was not possible.

The present invention has been made to solve the problems of the present invention, and exceeds the range of the block area in the Y direction during continuous scrolling in the X direction, or blocks in drawing and display during scrolling in the Y direction. A CRT that can perform scrolling in any direction at high speed, such as map display, without the need to move the display image into the block by software to avoid exceeding the area range
The purpose is to obtain a control device.

[0013]

A CRT control device according to the invention of claim 1 comprises a CPU for outputting a display control command for a CRT display device, and a conversion means based on the display control command output by the CPU. A graphic controller that controls drawing and display of image data in the drawing and display RAM via the drawing RAM and a plurality of divided drawing area blocks, and next to the drawing area block that scrolls among the divided drawing area blocks. Has
An image address space, which does not actually exist in the RAM and has continuous addresses in the same size as the drawing area block for scrolling, is provided so that an address for each drawing area block can be allocated. The drawing and display RAM for drawing and displaying the image data to be displayed and the address value supplied from the graphic controller are
It is determined whether the address value that actually exists in the drawing and display RAM or the image address value that does not exist. If it does exist, the address value remains as it is. If it does not exist, the image address value does not exist. And the converting means for supplying the drawing and display RAM to the drawing and display RAM.

According to a second aspect of the present invention, there is provided a CRT control device according to the first aspect, wherein the graphic controller is a drawing area which is an image address space which does not actually exist in the drawing and display RAM. A restoring means for restoring the address value supplied to the converting means to the address value which actually exists in the drawing and display RAM, based on a restoring command from the CPU, when the display is started from the display start address in the block. It is provided with the graphic controller including.

[0015]

In the invention of claim 1, the CPU in the CRT control device outputs a display control command for the CRT display device, and the graphic controller is the CP controller.
Based on the display control command output by U, the drawing and display control of the image data is performed in the drawing and display RAM through the conversion means. The drawing and display RAM includes a plurality of divided drawing area blocks, and next to the drawing area block to be scrolled among the divided drawing area blocks, an area of the same size as the scroll drawing area block. An image address space that does not actually exist is provided in the RAM whose addresses are continuous with each other so that addresses for respective drawing area blocks are allocated, and drawing and display of image data to be displayed on the CRT display is performed. . The conversion unit determines whether the address value supplied from the graphic controller is an address value that actually exists in the drawing and display RAM or an image address value that does not exist, and if it does exist, the address value remains unchanged. If it does not exist, the image address value is converted into an existing address value and supplied to the drawing and display RAM.

According to the second aspect of the present invention, the graphic controller in the CRT control device according to the first aspect of the present invention includes a restoring means, and the restoring means does not actually exist in the drawing and display RAM. When the display is started from the display start address in the drawing area block which is the image address space, the address value supplied to the converting means is the address which actually exists in the drawing and display RAM based on the return command from the CPU. Restores the value.

[0017]

1 is a block diagram showing the configuration of a CRT control device according to the present invention. In the figure, 1 to 5
Is the same as in FIG. Reference numeral 6 denotes a conversion circuit according to the present invention, which is an area of the same size (in the VRAM3, which is continuous in an arbitrary block to be scrolled in the Y direction, among the plurality of divided drawing and display area blocks included in the VRAM3. An address of a non-existent image address space) is converted from the non-existent image address value into a real address value when supplied from the GC 2. 1A in FIG. 1 is the system address bus,
1B is a data bus of the system, each of which is a CPU 1
And GC2, and is connected to RAM, ROM, etc. of the system not shown in FIG. 1C is a control bus of the system and is connected to peripheral circuits such as the CPU 1 and the GC 2. Reference numerals 2A, 2B, and 2C denote local address buses, data buses, and control buses output by GC2, respectively, which are connected to the input side of the conversion circuit 6. 3A, 3B and 3C are conversion circuits 6 respectively.
An address bus, a data bus, and a control bus connected to the VRAM 3 from the output side of the.

FIG. 2 is a view showing an example of a screen area of a plurality of blocks according to the present invention, showing blocks 1 to 5 and work areas which actually exist in the VRAM 3 and blocks 1'and 2'which do not exist. In FIG. 2, block 1 and block 2 are drawing and display areas for Y-direction scroll, respectively, as in FIG.
Has a drawing area of pixels. Also, these two areas actually exist in the VRAM 3. Blocks 1'and 2'are the image screen areas of blocks 1 and 2, respectively, and although this memory does not actually exist in the VRAM 3, addresses of the same size area consecutive to the existing blocks 1 and 2 are assigned respectively. Has been. In block 1 of FIG. 2, addresses 00000-07
Address FFF (hexadecimal), addresses 08000 to 0FFFF of consecutive same size areas in block 1 ', and addresses 1000 to 17FF in block 2.
Similarly, addresses 18000 to 1FFFF, which are addresses of the same continuous size area, are allocated to the block 2'of the address F, respectively.

Blocks 3 to 5 in FIG. 2 are fixed drawing and display areas not intended for scrolling, each having an area of 320 × 240 pixels. Block 3 has address 20000 to 2257F, and block 4 has address 22580 to 24AFF.
The address is 24B00 to 270 of the address in block 5.
Addresses 7F are assigned respectively. 2708
The memory of addresses 0 to 27 FFF is prepared as a work area of GC2.

FIG. 3 is an explanatory diagram of address conversion by the conversion circuit 6 of FIG. 1. In FIG. 3, the left side is the address output by the GC 2 and the right side is the address of the VRAM 3. As described in FIG. 2, the block 1'and the block 2 '
Does not actually exist in the VRAM 3, but addresses of the same size area in which the addresses are continuous are provided after the block 1 and the block 2. Then, GC2 has an address of 000 so that there is a block 1'which is continuous with block 1 and a block 2'which is continuous with block 2.
From 00 to 0FFFF (hexadecimal) and from 1000 to 1000
Up to 1FFFF address can be used freely.

The conversion circuit 6 shown in FIG. 1 is a circuit for converting the addresses of the blocks 1'and 2'in which no memory exists in the VRAM 3 into the addresses of the existing blocks 1'and 2 '. In this example, the areas of block 1 and block 2 have the same size of 512 × 512, and the memory capacity is 8000H (H is a digit of 0 to F.
It means the hexadecimal display). Therefore, block 1 '
The address of block 1 can be converted to the address of block 1 by subtracting 8000H.

In the embodiment shown in FIG. 1, the address value output from the GC 2 is 18-bit data D _{17 to} D ₀ , and the above 8000H corresponds to D ₁₅ among them. Therefore GC2
D _{14 to} D ₀ of the address data 2A outputted by the above are directly supplied as the address data D _{14 to} D ₀ of the VRAM 3 via the conversion circuit 6. When the value of the address data D ₁₅ D _{14 to} D ₀ is 10 to ₀ , the above-mentioned 8000H
Since the conversion circuit 6 does not supply the address data D ₁₅ supplied from the GC 2 to the VRAM 3,
Address data D ₁₇ and D ₁₆ supplied from the VRAM 3
By supplying the address data D ₁₆ and D ₁₅ of the above, it is substantially the same processing as subtracting 8000H.

When the above address conversion is performed between the GC2 and the VRAM3 by the conversion circuit 6, the address data is supplied so that the GC2 continuously draws from the lower part of the block 1 to the upper part of the block 1 '. When output,
Actually, when viewed from the VRAM 3, drawing is started in the lower part of the block 1 and the final address (07
After the drawing up to the address FFFH, the operation is continuously replaced with the operation for starting the drawing from the top address (address 00000H) of the top line of the block 1.

FIG. 4 is a diagram for explaining scrolling from block 1 to block 1'according to the present invention. In the figure, the drawing area is 512 × 512 pixels (pixels).
An example in which the map data composed of 100 × 100 pixels is scrolled and displayed in the Y direction in a system having a display area of 320 × 240 pixels of size First, in FIG. 4A, a map divided into (1) to (12) is drawn in the drawing area. When the drawing is completed, the display of an appropriate address in the map (1), for example, the display area indicated by the broken line from the point A is started.

Next, since the map in the Y direction runs short by scrolling downward in the Y direction, the maps (13) to (16) located below the maps (9) to (12) are drawn. . Here, from the map (13) (1
Regarding the lower half of 6), in the conventional CRT control device, if the write address is increased by the GC 2 as it is, the next block for drawing and display is written. However, in the CRT control device of the present invention, G
Even if C2 increases the write address as it is, since the drawing is commanded to the upper part of the block 1'where no memory actually exists, the writing for the next drawing and displaying block is not performed, and the conversion is performed. The circuit 6 actually performs the write operation on the upper portion of the block 1.

When the start address of the display area is moved from point A to point B for scrolling, the lower part of the display area is lowered from the area of block 1 to the area of block 1 '. At this time as well, like the conversion at the time of drawing, the upper part of the area of the block 1'continuing from the block 1 is displayed when viewed from the GC2, and when viewed from the address for accessing the actual VRAM3. Displays up to the bottom of block 1, then block 1
Will be displayed continuously from the top of. When the scroll in the Y direction is further continued, as shown in FIG. 4B, the maps (17) to (20) following the lower parts of the maps (13) to (16) are drawn and the display start address is set. Y
Update to the direction. By repeating this processing, it is possible to smoothly scroll downward in the Y direction within the area of the block 1 '.

By scrolling downward in the Y direction, the display start address is within the block 1 ', and when the scroll is continued further downward, if the address is updated as it is, the drawing and display area of block 2 is displayed. Will end up destroying the contents of this block. In order to avoid this, the CPU 1 is set at an appropriate timing after the display start address is moved into the block 1 '.
Issues a command to the GC2 to restore the address data output from the GC2 from the block 1'to the block 1. In accordance with the return command of the CPU 1, the GC 2 subtracts 8000H from the address value that has been output until then and outputs it, thereby returning the drawing and display area viewed from the GC 2 from the block 1 ′ to the block 1. After this restoration process,
Naturally, the conversion operation of the conversion circuit 6 becomes unnecessary.

FIG. 5 is a diagram for explaining the movement from block 1'to block 1 according to the present invention. In (a) of the figure, maps starting from the bottom of block 1 whose display start address is point A are (1) to (12) are VR
From the address space on AM3, the upper part of maps (1) to (4) is written in the lower part of block 1,
The bottom of maps (1) to (4) and maps (5) to (12)
Is written from the top of block 1. Further, in order to scroll the display start address from the point A to the point B, first, the map (1) following the maps (9) to (12)
Drawing (3) to (16). Next, the display start address is periodically updated from point A of block 1 to point B of block 1 '. Then, at an appropriate timing after the display start address is moved into the block 1 ', in this embodiment, when the display start address is moved to the point B in the block 1', the CPU 1 sends a block to the GC2. Command to return to address 1 and
2 makes a change to return to the address corresponding to block 1'in block 1.

FIG. 5B shows a state in which the GC 2 moves the display start address from point B to point C.
In this embodiment, since the address translation to the block 1 from the block 1 'is to subtract 8000H, the value of D ₁₅ of the address data output from GC2 may only be changed from 1 to 0. However, the movement of the address viewed from GC2 is the movement from the virtual address to the real address. In actual VRAM3, block 1
After the last address of 07FFFH, which is used as a starting address of 00000H as a ring-connected address, there is no actual movement, but new data is written on the old data storage address. The image data is updated.

In the above embodiment, the address conversion from the block 1'to the block 1 facilitates the conversion process of the conversion circuit 6, that is, D ₁₅ which is one bit of the address data D _{17 to} D _0. Although the subtraction processing of 8000H is performed so that only the conversion of 1 and 0 of 1 is sufficient, the present invention is not limited to this. Further, conversion of a plurality of bits and calculation of upper bits may be performed.

[0031]

As described above, according to the present invention, the VRAM
Next to the drawing area block to be scrolled among the plurality of divided drawing area blocks included in, an image address space where the memory does not exist, which is an area of the same size with continuous addresses, is provided, and the graphic controller is as if Even when the address is sequentially updated so that the memory actually exists in the image address space and scrolling is performed, the conversion means converts the non-existing image address value of the memory into the existing address value and supplies it to the drawing area block for scrolling. As a result, it is not necessary to move the display image into the block by software to avoid exceeding the block area range, which was required in the past, and it is possible to perform scrolling in any direction at high speed like map display. The effect is obtained.

Further, according to the present invention, when the graphic controller is displaying from the display start address in the image address space which does not actually exist in the VRAM, the image address value is changed to the real address value based on the return command from the CPU. Since the end address and the start address of the drawing area block to be scrolled can be used as the addresses connected in a ring shape, the scroll range is not limited.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a CRT control device according to the present invention.

FIG. 2 is a diagram showing an example of a screen area of a plurality of blocks according to the present invention.

3 is an explanatory diagram of address conversion by a conversion circuit 6 of FIG.

FIG. 4 is a diagram illustrating scrolling from block 1 to block 1 ′ according to the present invention.

FIG. 5 is a diagram for explaining the movement from block 1 ′ to block 1 according to the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional CRT control device.

FIG. 7 is a diagram showing an example of a conventional multi-block screen area.

FIG. 8 is a diagram illustrating an example of a conventional X-direction scroll.

FIG. 9 is a diagram illustrating a conventional Y-direction scroll example.

[Explanation of symbols]

 1 CPU 2 GC (graphic controller) 3 VRAM (video RAM) 4 shifter 5 D / A converter 6 conversion circuit

Claims (2)

[Claims] 1. A CPU that outputs a display control command for a CRT display device, and drawing and display control of image data in a drawing and display RAM via a conversion means based on the display control command output by the CPU. The drawing controller includes a graphic controller and a plurality of divided drawing area blocks. Of the divided drawing area blocks, the drawing area block to be scrolled is followed by an address of the same size as the scroll drawing area block. An image address space that does not actually exist is provided in the continuous RAM, and an address for each drawing area block is configured to be allocated. Drawing and display of image data to be displayed on the CRT display are performed. Display RAM and supplied from the graphic controller The determined address value is an actual address value in the drawing and display RAM or a non-existent image address value,
When the address value actually exists, the address value remains unchanged, and when the address value does not exist, the image address value is converted into an existing address value and is supplied to the drawing and display RAM. CRT control device to do. 2. When the graphic controller is displaying from a display start address in a drawing area block which is an image address space that does not actually exist in the drawing and display RAM, based on a return command from the CPU, 2. The CRT control device according to claim 1, further comprising the graphic controller including a restoring unit that restores an address value supplied to the converting unit to an address value that actually exists in the drawing and displaying RAM.