JPH0814753B2 - Display information processing method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a display information processing apparatus for displaying display data in a video memory in an arbitrary form.

[Conventional technology]

When displaying characters and graphics on a raster scan type display device, the display data stored in the video memory (hereinafter referred to as video RAM) is sequentially read out and sent to a CRT (cathode ray tube), etc. for display data. It is common to perform scanning while creating a beam spot of the brightness and color as if the display is allocated to the display in the video memory (called a bitmap method).

 A block diagram of such a display device is shown in FIG.

FIG. 4 constitutes a conventional display information processing apparatus together with FIG. 1 is a central processing unit (CPU), 2 is a video R
AM, 3 is a bus switcher, 4 is a bus switch control circuit, 5 is a display address generation circuit, 6 is a timing signal generation circuit, 7 is a digital-analog converter, 8 is a display device, 9 is an address bus, and 10 is a data bus. , 11 is CPU stop signal, 12 is video R
AM data bus, 13 video RAM address bus, 14 bus switching signal, 15 display data bus, 16 display address bus, 17 bus switching timing signal, 18 display clock signal, 19 horizontal blanking period signal, 20 is a vertical blanking period signal, 21
Is a display signal.

Further, FIG. 5 is an internal configuration diagram of the display address generating circuit 5 in FIG.

5-1 is a display start address register, 5-2 is a frame buffer width register, 5-3 is an adder, 5-4 is a multiplexer, 5-5 is a register, and 5-6 is a display address counter.

 The above circuit operates as follows.

The central processing unit 1 (hereinafter referred to as CPU) has an address bus 9,
The display data is written to the video RAM 2 by the data bus 10. At this time, the bus switching control circuit 4 monitors the operation of the CPU 1 by the address bus 9, sends the bus switching signal 14 to the bus switching device 3, and sends the video RAM 2 to the video RAM data bus 1 of the video RAM 2.
2 and video RAM address bus 13 and data bus 10 respectively
And the address bus 9 are connected.

The display address generation circuit 5 receives the display clock signal 18, the horizontal blanking period signal 19, and the vertical blanking period signal 20 from the timing signal generation circuit 6, and reads the display data from the video RAM 2 by the display address bus 16. It is input to the digital / analog converter 7 through the display data bus 15 and is output as the display signal 21 to the display device 8 to display it.

Further, the timing signal generation circuit 6 sends the bus switching timing signal 17 to the bus switching control circuit 4 and the bus switching device 3
The display address is changed to video RAM2 by switching
Display data supplied to the digital / analog converter 7
To be supplied to. At this timing, if the CPU1 attempts to read or write to the video RAM2, the bus switching control circuit 4 sends a CPU stop signal 11 to the CPU1.
Is sent to stop the CPU1 and read the display data, and then the CPU reads and writes.

The display address generating circuit 5 shown in FIG. 5 operates as follows.

When the display timing is the vertical blanking period, the contents of the display start address register 5-1 are the contents of the multiplexer 5-
It is supplied to the register 5-5 by 4 and is written in the register 5-5 by the horizontal blanking period signal 19. The contents of the registers 5-5 at this time, the contents of display start address registers 5-1 value DSA (D isplay S tart A ddr
ess) is set.

The output of the register 5-5 is connected to the display address counter 5-6, and the value of the register 5-5 is loaded by the horizontal blanking period signal 19. Therefore, like the register 5-5, it is the value of DSA during the vertical blanking period.

In the next display period, the display clock 18 is input to the display address counter 5-6 and according to the display clock 18.
Incremented as DSA, DSA + 1, DSA + 2, .... The output of the display address counter 5-6 is the display address bus.
It is input to the video RAM 2 by 16 and the display data of this display address is read and sent to the display device. In this way, the display of the first horizontal display period is continued, and then the horizontal blanking period is started. At this time, the multiplexer 5-
4 has already been switched by the vertical blanking period signal 20 and the output of the adder 5-3 is input to the register 5-5.
And content DSA of, FBW is the contents of the frame buffer width register 5-2 (F rame B ufter W idth ) is added value "DSA + FBW" is loaded in the display address counter 5-6 via register 5-5 It In this way, when the next horizontal display period is started, the display address counter 5-6 displays DSA + F.
The contents of video RAM2 are displayed by incrementing BW, DSA + FBW + 1, .... This situation is shown in FIG. That is, the display address sequentially increases in the horizontal direction of the display, and increases in the horizontal width (FBW) of the frame buffer in the vertical direction. In this way, the contents of the video RAM 2 can be displayed on the display device 8.

The contents of the display start address register 5-1 are CP
Since it can be rewritten by U1, any area of the video RAM2 can be displayed. By moving (scrolling) the displayed contents horizontally or vertically, or by setting the frame buffer width register 5-2 to any value, By preparing screens corresponding to several pages on the display screen and rewriting the contents of the display start address register 5-1, the display contents can be switched in an instant.

[Problems to be solved by the invention]

In the display device described above, when the contents of the display screen are scrolled in the horizontal direction or the vertical direction, the following problems occur.

In FIG. 7 (a), the width of the frame buffer is set larger than the area displayed by the display device, the display start address register 5-1 is set appropriately, and the display area in the video RAM 2 is displayed on the left side. It shows the state of performing.

Next, display data to be shown on the display device 8 after scrolling is written in advance in the area A not displayed by the display device 8. Next, FIG. 7 (b)
When the contents of the display address start register 5-1 are set and the value of DSA is increased as shown in, the display 8 looks as if the screen had moved to the left.

When DSA is set as shown in FIG. 7 (c) by the same means, the screen appears to move further to the left, but DSA cannot be further increased from this state.

If set, the display address during the horizontal display period continuously increases as shown in FIG.
After the X address, the contents of the Z address are displayed instead of the contents of the Y address. That is, when the display area is set to extend beyond the frame buffer of the video RAM 2, the display of the extended portion is the content of the area where the address for FBW has increased. Therefore, (I) display data is written in the non-display area at the scroll destination.

(II) Increase the display start address (DSA) and display.

Repeatedly, if the horizontal scrolling is continued, the display area moves vertically in the frame buffer, and finally the display area goes out of the video RAM2.

Therefore, after scrolling in FIG. 7 (a) → (b) → (c), the contents of the display area of (c) are transferred to the display area of (a), and the same operation is repeated.

This is because the amount of work required for the scroll operation performed in FIGS. 7 (a) and (b) is (c) when compared with the work of writing display data in the frame buffer area appearing after scrolling and increasing the DSA value. In order to scroll from (a) to (a), it takes a lot of time to transfer display data for almost one display screen, and the scrolling operation of the screen becomes slow only at this time. Therefore, since the scroll operation is not smooth and difficult to see, from (a) to (b),
Even when scrolling from (b) to (c), it is necessary to provide a waiting time and set the same time as the scroll from (c) to (a). In the end, the DSA value is fixed and the display data of the full screen is displayed. There is no difference in performance from the case of transferring and scrolling. This also happens when scrolling vertically.

Even more problematic is that when the contents of the video RAM being displayed are transferred, part of the screen appears to be scrolled during the vertical display period, so the display screen moves smoothly because it appears as waviness or flickering in the picture. The impression fades, so in order to scroll without flicker,
As shown in FIG. 8, display data for two screens is created in the video RAM, the area 1 is set as the display area, the display data in the area 2 is transferred by the CPU, and the display data is moved. Switch the display area to the area 2 side as in b),
This time, the display data on the side of the area 1 is transferred. By repeating this work, it is possible to perform scrolling without flicker, but a video RAM for an area for two screens is required.

That is, when scrolling with a conventional display device, there are drawbacks that an extra video RAM area is required and scroll performance is low.

This is because the display addresses are continuously generated, so that the display area cannot be rotated and operated at the same place like a belt of a belt conveyor.

Even in a conventional display device capable of performing wraparound in the horizontal and vertical directions, since the size of the frame buffer in the horizontal and vertical directions is actually fixed, it is optimal depending on the display state. Cannot set the minimum framebuffer.

That is, there is a drawback that it lacks flexibility in use.

An object of the present invention is to provide a low-cost display device with high flexibility in display settings that enables scrolling at high speed even when the amount of video RAM used is small.

[Means for solving problems]

The control method of the present invention includes a central processing unit that creates display data, a memory that stores the created display data,
In a display information processing apparatus including at least a circuit for reading display data from the memory, a frame buffer in which a storage area for the display data generated by the central processing unit or the memory is defined as a two-dimensional area, and a frame buffer of the frame buffer A frame buffer width register storing a width, a frame buffer height register storing a height of the frame buffer, a two-dimensional display start address register storing a start address of a display area in the frame buffer area, An X offset register that sets a horizontal offset of the start address of the display area with respect to the start point position of the frame buffer area, and a Y offset that sets a vertical offset of the start address of the display area with respect to the start point position of the frame buffer area.
An offset register is provided, and display is first started from an address held by the display start address register, and then, for a display area that does not extend from the frame buffer area in either the horizontal direction or the vertical direction, The value obtained by subtracting (value of X offset register) from (value of frame buffer width register) is larger than (increase value of display address in horizontal direction), and (value of frame buffer width register) to (value of Y offset register). The value obtained by subtracting (value) is larger than the (increase value in the vertical direction of the display address), and the value in the display start address register is set as the start point of the display address of the display area. For the display area that extends only to the area, (the value of the frame buffer width register) The value obtained by subtracting (the value of the X offset register) is smaller than (the increase amount of the display address in the horizontal direction), and the value obtained by subtracting the (value of the Y offset register) from the value of the (frame buffer vertical width register) is ( The value obtained by subtracting the value of the X-direction offset register from the value of the display start address register is set as the start point of the display address of the display area. However, for a display area that extends only vertically from the frame buffer area, the value obtained by subtracting the value of the X offset register from the value of the frame buffer width register is the amount of increase in the display address in the horizontal direction. ), And the value obtained by subtracting (value of Y offset register) from (value of frame buffer height register) is (display It detected from less than vertical increment) dress, the the value of the (display start address register) (X
The value obtained by adding the (direction offset register value) is set as the start point of the display address of the display area, and if the display area overflows from the frame buffer area in both the horizontal and vertical directions at the same time, (frame buffer width The value obtained by subtracting the value of the X offset register from the value of the register is smaller than the value of the horizontal increase of the display address, and the value of the Y offset register is subtracted from the value of the frame buffer height register. Detected value is smaller than (increase value in vertical direction of display address), and by setting the value of (frame buffer start address register) as the start point of display address of the display area, both horizontal and vertical directions are detected. Wrap around scrolling is possible.

[Action]

The present invention uses a frame buffer start address (FSA: F
rame Buffer S tart A ddress) and frame width of the buffer and (FBW), the vertical width of the frame buffer (FBL: F rame
By B uffer L ength) the CPU is capable of varying the set value register, a 2-dimensional region separately from the video RAM to the display area designated as a frame buffer, a display start address in the frame buffer (DSA), a frame buffer Offset from the first address (FSA) of the file (OFX: OF fs
et- X ) and Y offset (OFY: OF fset- Y ), each of which can change the setting value by the CPU, specifies the area to be displayed on the display device, and the display area outside the area of this frame buffer is specified. Horizontally "FBW-OFX"
The vertical direction is detected from the set value of "FBL-OFY", the start address of the display area that extends horizontally from the frame buffer area is set to "DSA-OFX", and the start address of the display area that also extends vertically is set to "DSA-OFX". FSA + OFX "and means for setting the start address of the display area that overflows in the horizontal and vertical directions to" FSA "at the same time.

With the above configuration, wrap-around scrolling is possible, scrolling can be done by rewriting the minimum display memory, and the frame buffer state can be set according to the display state, so it is low cost, high performance, and flexible. It is possible to realize a high display information processing apparatus.

〔Example〕

 1 and 2 show an embodiment of the present invention.

FIG. 1 is a circuit diagram showing a display address generation circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a main part of the display address generation circuit according to the embodiment.

FIGS. 1 and 2 are detailed diagrams of the display address generation circuit 5, and 2-1 is the width register (FB of the frame buffer).
W) 2-2 is the display start address register (DSA), 2-
3 is an X offset register (OFX), 2-4 is a frame buffer start address register (FSA), 2-5 is a subtracter, 2-6, 2-7, 2-8, 2-9, 2-10 are Adder, 2-11,2
-12, 2-13, 2-14 are multiplexers, 2-15 are registers 1, 2-16 are registers 2, 2-17 are registers 3, 2-18
Is register 4.

Figure 3-1 shows the width register (FB
W), 3-2 is an X offset register (OFX), 3-3 is a vertical width register (FBL) of the frame buffer, and 3-4 is Y.
Offset register (OFY), 3-6, 3-7 are subtractors, 3
-8 is a horizontal counter, 3-9 is a vertical counter, 3-10 is a multiplexer, and 3-11 is a display address counter.

 These perform the following operations.

First, during the vertical blanking period, the multiplexers 2-11 and 2-12 in FIG.
A), (Display start address)-(X offset) =
The display address of (DSA-OFX) is selected, and the respective addresses are loaded in registers 1, 2-15 and registers 2, 2-16.

In addition, the frame buffer width register (FB
The content of the X offset register (OFX) 3-2 is subtracted from W) 3-1 by the subtractor 3-6 and loaded into the horizontal counter 3-8 by the horizontal retrace signal 19. The horizontal counter 3-8 is decremented every time the display clock 18 is input. When the content is other than "0", the signal A is "0" and the content is "0".
At the time of, the signal A is output as "1".

Also, the frame buffer vertical width register (FBL) 3-
3, the content of the Y offset register (OFY) 3-4 is subtracted by the subtractor 3-7, and the vertical counter 3-9 is loaded with the vertical blanking period signal 20. Like the horizontal counter 3-8, the vertical counter 3-9 is configured to be decremented by the horizontal blanking period signal 19 and output "1" to the signal B when the content is "0".

Next, in the display period, since the contents of the horizontal counter 3-8 and the vertical counter 3-9 are not "0", the signals A and B input to the multiplexer 3-10 are respectively set to "0". Suppose that In this case, the multiplexer 3-10 selects the signal 1, that is, the display start address (DSA) set in the registers 1 and 2-15, is loaded into the display address counter 3-11, and the display clock 18
In accordance with, the display address is output as DSA, DSA + 1, DSA + 2, ....

If the display area setting is such that the display area does not extend horizontally from the frame buffer width (FBW) and frame buffer height (FBL) areas as shown in Fig. 3 (a), the horizontal display period In the middle, the content of the horizontal counter 3-8 does not become "0" and the signal A remains "0", and the multiplexer 3-10 continues to select the signal "1". Therefore, the display address counter 3-11 continues to output continuous display addresses during one horizontal display period, as in the conventional display address generating circuit 5 shown in FIG.

When the setting of the display area extends in the horizontal direction as shown in FIG. 3B, the horizontal counter 3-8 is displayed during the horizontal display period.
Becomes "0", the signal A changes to "1", the multiplexer 3-10 selects the signal "2", and the contents of the registers 2 and 2-16 (DSA-OFX) in the display address counter 3-11. ) Is loaded. It is understood that this address is different from the display address of the conventional system and is the display address on the same horizontal coordinate line as DSA on the mapping of the video RAM as shown in FIG. 3 (b).

That is, the display area horizontally wraps around in the frame buffer area. In this way, the display address counter 3-11 continues incrementing from the DSA-OFX address and enters the horizontal flyback period. Then, the multiplexers 2-11 and 2-12 receive the registers 1 and 2-15.
Since the value of the frame buffer with the width (FBW) added to the contents of register 2 and 2-16 is selected, DSA + FBW for registers 1 and 2-15 and D for register 2 and 2-16.
The values of SA-OFX + FBW are loaded respectively. In this way, again, the display is performed during the horizontal display period, and the register 1,
The contents of 2-15 and registers 2 and 2-16 add FBW each time the horizontal blanking period is entered.
The display address of the DSA-OFX system is generated, the display is performed until the vertical blanking period, and the display returns to the original state.

Next, as shown in FIG. 3C, a case where the display area extends vertically from the frame buffer area will be described. At this time, the horizontal counter 3-8 is "0" during the horizontal display period.
However, the signal A remains "0". Vertical counter 3
Since -9 is not "0", the signal B is "0". Therefore, the multiplexer 3-10 uses register 1,
Select the 2-15 DSA system address and generate the display address. Further, while the horizontal display period is repeated, the contents of the vertical counter 3-9 are decremented, and when it becomes "0", the signal B becomes "1". Then multiplexer 3-
10 selects the signal "3" and loads the contents of the registers 3 and 2-17 into the display address counter 3-11. Registers 3 and 2-17 and registers 4 and 2-18 are FSA + O respectively.
The values of FX and FSA are loaded through the multiplexers 2-13 and 2-14, the signal B becomes "1", and the registers 3 and 2-
The outputs of 17 and registers 4 and 2-18 are switched to the side of the value obtained by adding FBW.

Therefore, in the next horizontal blanking period, FSA + OFX +
The value of FBW, FSA + FBW is loaded. Also, register 3,
The value of FSA + OFX loaded in 2-17 is the display address on the same vertical coordinate in the frame buffer area.
In other words, it means that it was wrapped around vertically. In this way, the display address of the next horizontal display period is generated, FBW is continuously added for each horizontal blanking period, and the state returns to the original state in the vertical blanking period.

In the same manner, when the horizontal and vertical wraparounds shown in FIG. 3D are performed, the DSA addresses of the registers 1 and 2-15 are used in the first horizontal display period. In the middle of the horizontal display period, the horizontal counter 3-8 becomes “0”, the signal A becomes “1”, and the multiplexer 3-10 operates as a register 2, 2.
The 16 DSA-OFX addresses are loaded into the display address counter 3-11 to generate the display address.

Next, the contents of registers 1, 2-15, 2 and 2-16 are displayed while adding FBW for each horizontal blanking period, and the contents of vertical counter 3-9 are decremented to "0". Then, the signal B becomes "1". At this time, since the horizontal counter 3-8 loads FBW-OFX again, the signal A
Becomes "0". FSA after the start of the next horizontal display period
Since the value of + OFX is loaded in the display address counter 3-11, it is displayed in order from this display address. When the content of the horizontal counter becomes "0", the signal A becomes "1". Therefore, the multiplexer 3-10 selects the registers 4 and 2-18 of the signal "4" and displays the FSA as the display address counter 3-1.
Load to 1 and display.

As described above, it is possible to perform a display in which the display area is horizontally and vertically wrapped.

Although the display start address (DSA) is described as a register set by the CPU in the above embodiment, a circuit configuration may be used in which the DSA is automatically calculated from the relational expression DSA = FSA + OFX + FBW × OFY.

Also, addition of FBW to DSA, FSA, OFX and FBW-OFX, FBL
-OFY, DSA-OFX, FSA + OFX, etc. may be calculated by a microprogram or software and directly applied to each register or counter.

[Operation of the invention]

In order to generate the display address with the above configuration, FIG. 8A in the case of performing horizontal crawl in the conventional circuit,
Even if scrolling is not performed while switching the display memories for two screens as shown in (b), the portion protruding from the frame buffer area in the state of FIG. 7 (b) is not a continuous address but a wrapped area. To do this, (I) write the display data in the non-display part of the scroll destination, (II) display start address (DSA) and X offset (OFX)
If the OFX becomes larger than the FBW, the horizontal wraparound can be performed by repeating the procedure of setting the first address of the horizontal display address to DSA and setting the OFX to “0”. You can This is exactly the same when scrolling in the vertical direction, and DSA and OFY may be controlled within the FBL area. In this way, scrolling can be realized by rewriting the minimum memory area. Therefore, it is possible to realize a display information processing apparatus having a high display speed and high flexibility even with a display memory.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a display address generating circuit according to an embodiment of the present invention, FIG. 2 is a main circuit diagram of a display address generating circuit according to an embodiment, and FIG. FIG. 4 shows a wrap-around state, FIG. 4 is a circuit diagram showing the entire conventional display address generation circuit, FIG. 5 is a circuit diagram of a main part of the conventional display address generation circuit, and FIG. 6 is a display timing of the conventional system. FIG. 7 is an explanatory diagram of display addresses, FIG. 7 is an explanatory diagram of display timing in the conventional method, and FIG. 8 is a diagram showing an example of a horizontal scroll method in another conventional method. 1 ... Central processing unit (CPU), 2 ... Video RAM 3 ... Bus switcher, 4 ... Bus switching control circuit 5 ... Display address generation circuit 6 ... Timing signal generation circuit 7 ... Digital / analog conversion Display unit 9 …… Address bus, 10 …… Data bus 11 …… CPU stop signal 12 …… Video RAM data bus 13 …… Video RAM address bus 14 …… Bus switching signal, 15 …… Display data Bus 16 …… Display address bus 17 …… Bus switching timing 18 …… Display clock signal, 19 …… Horizontal blanking period signal 20 …… Vertical blanking period signal, 21 …… Display signal 2-1 …… Frame buffer Width register 2-2 …… Display start address register 2-3 …… X offset register 2-4 …… Frame buffer start address register 2-5 …… Subtractor 2-6,2-7,2-8,2- 9,2-10 ... Adder 2-11,2-12 , 2-13,2-14 ... Multiplexer, 2-15
Register 1 2-16 Register 2, 2-17 Register 3 2-18 Register 4 3-1 Frame buffer width register 3-2 X offset register 3-3 Frame Buffer height register 3-4 …… Y offset register 3-6,3-7 …… Subtractor 3-8 …… Horizontal counter, 3-9 …… Vertical counter 3-10 …… Multiplexer 3-11 …… Display Address counter 5-1 ... Display start address register 5-2 ... Frame buffer width register 5-3 ... Adder, 5-4 ... Multiplexer 5-5 ... Register, 5-6 ... Display address counter

Claims (1)

[Claims] 1. A display information processing apparatus comprising at least a central processing unit for creating display data, a memory for storing the created display data, and a circuit for reading the display data from the memory. Alternatively, a frame buffer in which a storage area of the display data generated in the memory is defined as a two-dimensional area, a frame buffer width register that stores the width of the frame buffer, and a frame buffer height that stores the height of the frame buffer A register, a two-dimensional display start address register that stores a start address of a display area in the frame buffer area, and an X offset that sets a horizontal offset of the start address of the display area with respect to a start point position of the frame buffer area. Register and start of the frame buffer area A Y offset register for setting a vertical offset of the start address of the display area with respect to a point position, first starting display from an address held by the display start address register, and then horizontally from the frame buffer area. For a display area that does not extend in both the vertical and vertical directions, the value obtained by subtracting (X offset register value) from (frame buffer width register value) is less than (horizontal display address increase value). It is detected that it is large and the value obtained by subtracting (value of Y offset register) from (value of frame buffer vertical width register) is larger than (increase value of display address in vertical direction), and the value of display start address register is Set as the start point of the display address of the display area, In respect to the display area protruding only, less than the value obtained by subtracting from the (value of X offset register) (frame buffer width value of the register) is (horizontal increment of the display addresses),
Also, the value obtained by subtracting (value of Y offset register) from (value of frame buffer height register) is larger than (increase value of display address in vertical direction), and detected from (value of display start address register). The value obtained by subtracting the (value in the X-direction offset register) is set as the starting point of the display address of the display area, and for the display area that extends only vertically from the frame buffer area, (the frame buffer width register The value obtained by subtracting (value of X offset register) from (value) is larger than (increase value in horizontal direction of display address),
And it is detected that the value obtained by subtracting (value of Y offset register) from (value of frame buffer width register) is smaller than (increase value of display address in vertical direction), and the value of (display start address register) is detected. When the value obtained by adding the (value of the X-direction offset register) is set as the start point of the display address of the display area, and the display area overflows from the frame buffer area in both the horizontal direction and the vertical direction at the same time, ( The value obtained by subtracting (the value of the X offset register) from the value of the frame buffer width register is smaller than the (increase value in the horizontal direction of the display address), and the value of the (frame buffer height register) to the (Y offset register value) ) Is subtracted from the value (increment in the vertical direction of the display address), it is detected and Display information processing method, wherein the value of the display start address register) is set as the start point of the display address of the display area.