JP2002258827A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device which can prevent images on a display screen from being disordered, due to conversion processing by windows as an image display device which sets multiple windows on the display screen to make what is called a multiwindow display where multiple layers are displayed. SOLUTION: The image display device, which makes the multiwindow display by setting rectangular areas as windows on the display screen and displays image data drawn in different layers of a VRAM 105 in the respective windows, is provided with a frame buffer 110 corresponding to one screen; and once the alteration processing for the VRAM 105 is completed, the display data in the frame buffer 110 are switched to the contents of the VRAM 105, having been altered in synchronism with display operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image display device, and more particularly, to an image display device using a CRT, an LCD, or the like.

[0002]

2. Description of the Related Art As an image display device, for example, VRA
2. Description of the Related Art There is a graphic display device that sequentially reads image data developed in M and displays image information (image data) such as characters and patterns on a display device using a CRT (cathode ray tube) or an LCD (liquid crystal device).

In such a graphic display device, a so-called window display, in which a rectangular area is set in a screen and an image of a completely different layer is displayed, is generally performed as a method of switching display contents and expanding a screen.
As an application of such a display method, a so-called multi-window display that handles a plurality of windows has become popular.

As a method of performing multi-window display,
Conventionally, another image is drawn in that area of the displayed frame buffer (data is rewritten)
There are a software method as described above and a display address control method using hardware.

In the above-described software method, a frame buffer for holding the same image data as the displayed image is provided in addition to the VRAM in which all the images including the non-displayed image of each window are drawn. .

In the method of controlling the display address by hardware, a multi-window is displayed by drawing all the data including the image of the non-displayed portion of each window in the VRAM and switching the address by hardware.

In the software method, it is necessary to transfer the displayed portion to the frame buffer every time the VRAM layer is rewritten. Therefore, it has been a factor of delaying the drawing speed for changing the screen.

Conventionally, as a method of switching the display address by hardware, an address counter for a basic screen as a base before opening a window and an address counter for each window are separately provided, and a display is performed for each area of the display screen. A method for switching addresses is known. In addition, a method is known in which a display address of each window is determined by calculation on a basic counter output for each area.

For example, in Japanese Patent Application Laid-Open No. H11-161255, a plurality of rectangular areas are set as windows on a display screen of a display device, and image data drawn on different layers of a display memory is displayed in each window. An image display device comprising a display control circuit for performing multi-window display, the display control circuit including an address counter that outputs a display address of a basic screen having the entire display screen as a display area, and an address counter corresponding to each of the windows. Address offset value, coordinate values indicating the display position and size of each window on the display screen, and a window attribute register including a plurality of registers for setting the priority of each window, and a window attribute register synchronized with the display operation. Each window based on the value set in each of the window attribute registers. An offset switch for switching and outputting an address offset value with respect to a dow, and adding the display address of the basic screen output by the address counter and the address offset value output by the offset switch to display the basic screen and each window. An offset adder for outputting an address to the display memory.

In Japanese Patent Application Laid-Open No. 11-161256, a plurality of rectangular areas are set as windows in a display screen of a display device, and an image for performing multi-window display in which each window is drawn on a different layer from the display memory is set. In the display device, means for individually setting the virtual screen width of each layer on the display memory for each window is provided.

Japanese Patent Application Laid-Open No. H11-288345 discloses an image for performing multi-window display in which a plurality of rectangular areas are set as windows on a display screen of a display device and each window is drawn on a different layer from the display memory. The display device includes means for independently setting a width in the main scanning direction on the display screen and a virtual screen width of each layer on the display memory for each window.

[0012]

However, in the conventional multi-window display using hardware, there is a problem that the display flickers on the display screen when the display content of each window is changed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In an image display apparatus that performs a so-called multi-window display in which a plurality of windows are set in a display screen and a plurality of layers are displayed, It is an object of the present invention to provide an image display device capable of preventing an image on a display screen from being distorted due to conversion processing for each window.

[0014]

According to a first aspect of the present invention, a plurality of rectangular areas are set as windows in a display screen, and a different display memory is set in each window. In an image display device for displaying multi-window display by displaying image data drawn on a layer, one screen for expanding display data drawn on each layer of the display memory and outputting the expanded display data to a display screen A frame buffer for changing the display data of the display buffer to the contents of the display memory after the change in synchronization with the display operation when the change processing for the display memory is completed.

According to the above invention, the display data of the frame buffer is replaced with the display contents after the change of the display memory at the time when the process of changing the display contents of each window of the display memory is completed using the frame buffer for one screen. In this case, the image is not disturbed on the display screen due to the access to the display memory when the display contents are changed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an image display device according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the overall configuration of an image display device according to the present invention. The image display device shown in FIG. 1 includes a CPU 1, a ROM 2, a timing generator 3, a display control circuit 4, a bus driver 5, a multiplexer 6, a latch circuit 8, a display device 9, a VRAM 105, and a frame buffer 110.

The CPU 1 is a central processing unit for controlling the entire apparatus, and controls each section according to a program stored in the ROM 2. The ROM 2 stores a program for the CPU 1 to execute control of each unit and graphic pattern data for graphic display. The CPU 1, the ROM 2, and the multiplexer 6
They are connected via address buses (A0 to A15).

The display control circuit 4 has a function of repeating a cyclic (regular) display operation asynchronously with the CPU 1 in accordance with a timing signal generated by the timing generator 3. In order to repeat this cyclic screen display, the display control circuit 4 has priority in accessing the VRAM 105 as a display memory. CPU1
When rewriting or reading display data, the timing generator 3 controls the multiplexer 6 so that the display control circuit 4 is in a non-access timing.

The display control circuit 4 mainly comprises a display address generator for generating display addresses (GA0 to GA14). The CPU 1 first stores the display start address (start address) on the VRAM 105, the number of characters that can be displayed in the horizontal direction (main scanning direction) of the display screen (horizontal display screen width), and VR in the registers inside the display control circuit 4.
The number of writable characters in the main scanning direction of the AM 105 (virtual screen width of the basic screen) and the like are determined by a data bus
Set each through. These set values are also sent to the timing generator 3, and the timing generator 3 generates various synchronization signals for display according to these set values.

Further, the CPU 1 transfers graphic data of each image data to be displayed to a predetermined address of each layer in the VRAM 105 according to a program in the ROM 2 and draws one frame at a time. The display control circuit 4
The display addresses (GA0 to GA14) are output onto the graphic display address bus 10 in accordance with the frame synchronization signal generated by the timing generator 3.

The image data according to the address is VRA
After being read from M105 and expanded in the frame buffer 110 having the capacity of a frame having the memory capacity of one screen, it is transferred to the display device 9 via the latch circuit 8. The frame buffer 110 has a memory capacity for one screen, and when the process of changing the display content of each window of the VRAM 105 ends, the VRAM 105
Is transferred to the frame buffer 110, and the display content before the change and the display content after the change are switched in frame units.

The multiplexer 6 selects access from the CPU 1 and the display control circuit 4 to the VRAM 105.
Then, the bus driver 5 controls the data bus. The display device 9 may be a CRT, LCD, or any other display device capable of two-dimensional display of characters and figures.

Next, a portion of the display control circuit 4 relating to the present invention will be described with reference to FIG. FIG.
FIG. 3 is a block diagram showing a relationship between a portion forming a display address generator of the display control circuit 4 and the VRAM 105 and the display device 9. Although not shown in this block diagram, the display control circuit 4 includes a display start address (start address of the basic screen) on the VRAM 105, the number of characters that can be displayed in the main scanning direction of the basic screen (horizontal display screen width), and the like. , A register set by the CPU 1 of FIG.

The display control circuit 4 includes a main scanning counter 1
1, a sub-scanning counter 102, a window attribute register 103, a mask calculator 104, a VRAM 105, a display device 9, an effective layer controller 107, a window attribute switch 108, and a priority register 109.

The main scanning counter 101 and the sub-scanning counter 102 are counters used for displaying a basic screen. The main scanning counter 101 sets a display position in the main scanning direction and the sub-scanning counter 102 sets each position in the sub-scanning direction. Specify each display position.

The window attribute register 103 stores the origin coordinates (Wsx) of the display position on the display screen for each window.
n, Wsyn) and end point coordinates (Wexn, Weyn)
Registers and a VRA for each window
A plurality of registers for setting the virtual screen width Wmn of each layer on M105, and the address offset value of the layer corresponding to each window (V of origin data of each window)
And a plurality of registers for setting (address on the RAM 105) Awsn.

The priority register 109 comprises a plurality of registers for setting the priority of each window. The effective layer controller 107 includes a main scanning counter 101,
Sub-scan counter 102, window attribute register 10
3, and outputs a valid signal of only one layer based on each output value of the priority register 109.

The window attribute switch 108 selects an attribute of the window to be displayed from the window attribute register 103 according to the valid signal from the valid layer controller 107 and outputs the selected attribute to the mask calculator 104. The mask calculator 104 performs a mask process based on the output values of the main scanning counter 101, the sub-scanning counter 102, the window attribute switch 108, and the like, and then outputs a display address.

On the other hand, when displaying each window on the display device 9, the CPU 1 causes the window attribute register 1 to be displayed.
In 3, an attribute of each window to be displayed is set. That is, the origin coordinates (Wsxn, Wsyn) and the end point coordinates (Wex) of the display position on the display screen for each window.
n, Weyn) and the virtual screen width Wmn of each layer on the VRAM 105 are set independently, and the address offset value Aws of each layer corresponding to each window is set.
n is set. The priority of each window is set in the priority register 109.

As a result, the effective layer controller 107 controls the main scanning counter 101 and the sub-scanning counter 10
2, the virtual screen width Wmn of each layer on the VRAM 105 corresponding to each window set in the window attribute register 13, the origin coordinates (Wsxn, Wsyn) and the end point coordinates of the display position of each window on the display screen (Wexn, Weyn), based on the priority of each window set in the priority register 109, outputs a valid signal of only one layer.

As described above, the window attribute switch 1
08 selects a window attribute to be displayed from the window attribute register 103 in response to a layer valid signal from the valid layer controller 107, and
04. The mask calculator 104 performs a calculation by substituting the output values of the main scanning counter 101 and the sub-scanning counter 102 and the attribute of the window to be displayed selected by the window attribute switch 108 into the following equation, and displaying the window. Address (address on VRAM) Awdn
Is determined and output to the VRAM 105 as a display memory.

Awdn = (Wmn (Cy-Wsyn) +
(Cx-Wsxn)) + Awsn Here, Cx represents the output value of the main scanning counter 101 as Cy.
Is the output of the sub-scanning counter 102, Awdn is the display address of the nth window, Wmn is the virtual screen width of the layer on the VRAM 105 corresponding to the nth window, and (Wsxn, Wsyn) is the nth window. Indicates the origin coordinates of the display position on the display screen, and Awsn indicates the address offset value of the layer corresponding to the n-th window.

Each section in the above-described display control circuit 4 operates (in synchronization with the display operation) in accordance with the frame synchronization signal generated by the timing generator 3, whereby the display address is output from the mask calculator 104. Therefore, the VRAM 105 depends on the display address.
Is read from the frame buffer 110.
Is transferred to and displayed on a display device 9 such as an LCD.

As described above, the display address for reading out the image data drawn on each layer of the VRAM 105 is output from the display control circuit 4 in synchronization with the frame synchronization signal, and drawn on each layer on the VRAM 105. The image data of each window is picked up, transferred to the display device 9 via the frame buffer 110, and displayed. Therefore, a final multi-window screen is obtained.

When the CPU 1 outputs a transfer command to the display control circuit 4, the display control circuit 4 transfers the image of each window of the VRAM 105 to the frame buffer 110 in synchronization with the frame synchronization signal. FIG.
5 is a timing chart for explaining a change timing of display data of a frame buffer. In the figure, (A) shows a frame synchronization signal, (B) shows a transfer command, (C) shows a timing of the VRAM, and (D) shows a timing of the frame buffer 110. Figure (C)
As shown in FIG. 5, when the change processing for the VRAM 105 is completed, the CPU 1 outputs a transfer command to the display control circuit 4 as shown in FIG. In synchronization with the synchronization signal (display operation), as shown in FIG.
Is switched in frame units to the contents of the VRAM 105 after the change. Thereby, it is possible to prevent the disturbance of the image caused by the access to the VRAM when the display content is changed from being displayed on the display screen. Also, the frame buffer 11
Since the configuration is such that data is transferred from the VRAM 105 to the frame buffer 110 in synchronization with the normal data transfer timing from 0 to the display device 9, the switching of the frame and the switching of the image change match.

To change the display shape of each window, the origin coordinates (Wsxn, Wsyn) and end point coordinates (Wexn, Wsn) of the display position on the display screen are set for each window set in the window attribute register 103.
eyn) may be changed. It is not necessary to change the display data (image data) and the address on the VRAM 105.

In order to change the vertical relationship of each window, the priority of each window set in the priority register 109 may be changed, and it is not necessary to change the contents of the image data of the layer on the VRAM 105. In addition,
In the example shown in FIG. 3, window 2 has a higher priority than window 1.

Further, when scrolling the display in the window, the address offset value Awsn of the window attribute register 103 may be changed.
The display data drawn in 5 does not need to be corrected.

It should be noted that the present invention is not limited to the above-described embodiment, and can be appropriately modified and executed without changing the gist of the invention. For example, in this embodiment, an example in which the image display device of the present invention is applied to an LCD controller has been described. However, the present invention is not limited to this, and can be applied to other controllers such as a CRT controller. .

[0041]

As described above, according to the present invention,
A frame for one screen in an image display device in which a plurality of rectangular areas are set as windows in a display screen, and image data drawn on different layers of a display memory is displayed in each window to perform multi-window display A buffer is provided, and when the change processing for the display memory is completed, the display data of the frame buffer is switched to the contents of the changed display memory in synchronization with the display operation. Therefore, it is possible to provide an image display device which can prevent the image on the display screen from being disturbed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a block configuration of an image display device according to the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of a display control device of the image display device of FIG. 1;

FIG. 3 is a diagram showing an example of window display on a display screen.

FIG. 4 is a flowchart for explaining a change timing of display data of a frame buffer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 Timing generator 4 Display control circuit 5 Bus driver 6 Multiplexer 8 Latch circuit 9 Display device 101 Main scanning counter 102 Sub scanning counter 103 Window attribute register 104 Mask calculator 105 VRAM 107 Effective layer controller 108 Window attribute switch 109 Priority register 110 Frame buffer

Claims (1)

[Claims] 1. An image display apparatus for setting a plurality of rectangular areas in a display screen as windows and displaying image data drawn on different layers of a display memory in each of the windows to perform multi-window display. A frame buffer for one screen for expanding the display data drawn on each layer of the display memory and outputting the expanded display data to a display screen; Wherein the display data of the frame buffer is switched to the content of the display memory after the change in synchronization with the display memory.