JP4742507B2 - Image display device - Google Patents

Description

  The present invention relates to an image display device capable of simplifying display data writing processing to display data storage means of a display unit when scrolling display data displayed on an image display unit.

As a conventional image display device, when displaying a character message of a maximum of 192 characters stored in the storage unit on a liquid crystal display unit in which the amount of characters that can be displayed at one time is limited to about 6 characters × 3 lines, for example, In the control circuit, the character message stored in the storage unit is displayed on the VRAM included in the storage unit as the display data of 6 characters in the horizontal direction while being smoothly scrolled on the display unit, and the scroll display speed is touched with the touch sensor. There is known a communication terminal device having a function of receiving a text message such as a mobile phone or a pager that can be slowed down (see, for example, Patent Document 1).
Japanese Unexamined Patent Publication No. 2000-184420 (first page to fifth page, FIG. 1)

  However, in the conventional example described in Patent Document 1, the scroll display speed is different when displaying more character messages on the display unit than can be displayed on the display unit stored in the storage unit. Since the scroll display can be performed, the user can freely change the speed of the scroll display while watching the display of the text message on the display unit, and the scroll display that is easy to read for the user can be performed. Although it is possible, there is an unsolved problem that, when the scroll display control in this case is performed by the control circuit, the address setting in the display data writing process becomes complicated when the display data is expanded on the VRAM.

  Therefore, the present invention has been made paying attention to the unsolved problems of the above-described conventional example, and when displaying display data such as characters and images on a display unit such as a liquid crystal display, the characters and images are displayed. An object of the present invention is to provide an image display device that can simplify the display data writing process.

The first technical means comprises display means for displaying display data, a controller driver for outputting display data to be displayed on the display means, and external information processing means for writing the display data to the controller driver,
The controller driver stores display data to be displayed on the display means, and also displays display data storage means set to a display data amount larger than the display data amount of the display means, and display data is written to the display data storage means. The external information processing means and the display data stored in the display data storage means are added to the read start address by a step amount representing the address movement amount of the data storage means in one scroll display set in sequence. And a scroll display data reading means for sequentially reading from the new read start address calculated in this way to a read end address corresponding to the display data amount required by the display means and outputting to the display means. The display data storage means is designated by its own management address as the write address, Scroll display data writing means for writing scroll display data before starting reading by the data display data reading means, and the control driver converts the management address of the information processing means inputted to its own management address. The scroll display data reading means comprises write start timing notifying means for outputting an interrupt signal indicating the start time of the scroll period to the scroll display data writing means, The scroll display data writing means determines whether or not priority processing other than display processing exists when an interrupt signal indicating the start time of the scroll period is input from the writing start timing notification means. when said priority processing is not present writes scroll display data, disk said priority processing is present When not performing the writing Lumpur display data, characterized in that the writing of the scroll display data when the elapsed time from the start of the scroll period is equal to or greater than the time required to complete the write It is said.

According to the first technical means, when scroll display is performed, the scroll display data is written by designating its own management address in the information processing means, and the information inputted by the address conversion means in the display data storage means The management address of the processing means is converted into its own management address, and display data is written.
Therefore, when performing scroll display, writing of scroll display data from the information processing means to the display data storage means can be designated as a relative address without considering the actual address designation of the display data storage means. Data writing processing can be simplified.
Further, since the writing start timing is notified from the scroll display data reading means to the scroll display data writing means by the writing start timing notifying means, the information processing means writes the writing timing to the display data storage means based on the writing start timing. And the writing process can be simplified by omitting the monitoring process of the writing timing.

Further, a second technical means is the first technical means, wherein the information processing means sets a step amount at the time of scroll display, and sets the step amount set by the step amount setting means to the scroll amount. And a step amount notifying means for notifying the display data reading means.
According to the second technical means, the step amount setting means of the information processing means sets the step amount at the time of scroll display, and notifies the set step amount to the scroll display data reading means. The writing amount and the reading amount of the scroll display data can be exactly matched.

Further, the third technical means is the first or second technical means, wherein the information processing means is a value obtained by multiplying a scroll display data amount for the display data storage means by an integer n that can arbitrarily set a step amount. It is characterized by being configured to be set to.
According to the third technical means, by setting the scroll display data amount written in the display data storage means by the information processing means to an integer n times the step amount, the scroll display data reading means reads the scroll display data n times. Scroll display data only needs to be written once each time is read, and the number of times scroll display data is written to the display data storage means can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an image display device as information processing means having a function of generating a signal for writing display data to be displayed to the controller driver 11. Information processing apparatus 12, a liquid crystal display 13 that displays display data output from the controller driver 11, a Y driver 14 that drives the liquid crystal display 13, and a reference clock necessary for the controller driver 11 to display a liquid crystal screen. And an oscillation circuit 15 for generating.

  The controller driver 11 includes a dual port memory 16 as display data storage means capable of asynchronously performing an interface with the information processing apparatus 12 and an interface with the liquid crystal display 13, and display data from the information processing apparatus 12. It includes an information processing device logic circuit 17 that is input, and a display logic circuit 19 to which a reference clock signal DCLK from the oscillation circuit 15 and a set value from the display controller 18 are input.

  In addition, the controller driver 11 controls reading and writing to the X driver 20 that reads display data for one line from the dual port memory 16 and the memory areas 16U, 16S, and 16L that store the display data of the dual port memory 16. The read / write circuit 21 for the information processing apparatus, the row address decoder 22 indicating addresses in the Y (row) direction of the memory areas 16U, 16S and 16L when the information processing apparatus 12 reads and writes, and the memory when the information processing apparatus 12 reads and writes A column address decoder 23 that outputs addresses in the X (column) direction of the areas 16U, 16S, and 16L, and display data supplied to the X driver 20 among the display data stored in the memory areas 16U, 16S, and 16L. Display address decoder 24.

Here, the logic circuit 17 for the information processing apparatus has a function of performing processing related to the information processing apparatus 12 such as processing of commands sent from the information processing apparatus 12 and control of display data read / written to the dual port memory 16. is doing.
The display logic circuit 19 has a function of performing display-related control such as control for reading display data from the dual port memory 16 and supplying the display data to the X driver 20, and control of the Y driver 14.

Further, the X driver 20 is a circuit that converts display data read from the dual port memory 16 into a voltage required by the liquid crystal display 13.
The Y driver 14 receives data for selecting a line for writing a data signal supplied from the X driver 20 via the display controller 18 and is necessary for driving the liquid crystal display 13 with a selected / unselected voltage. Has a function of generating a large voltage. The Y driver 14 and the X driver 20 are supplied with a voltage necessary for display on the liquid crystal display 13 generated by the display power supply 25.

Furthermore, the display capacity of the liquid crystal display 13 is, for example, 176 × 180 dots, and the liquid crystal display 13 has 180 common electrodes on the left side and 176 segment electrodes on the upper side, as shown in FIG. An upper fixed display area 13U, a lower fixed display area 13L, and a scroll display area 13S arranged between the fixed display areas 13U and 13L are formed.
On the other hand, the capacity of the dual port memory 16 is 176 × 240 bits larger than the display capacity of the liquid crystal display 13. As shown in FIG. 2, the dual port memory 16 has an upper fixed display data storage area displayed in the upper fixed display area 13U between “000” and “039” with row addresses. A scroll display data storage area to be displayed in the scroll display area 13S is formed between 199 ", and a lower fixed display data storage area to be displayed in the lower fixed display area 13L is formed between" 200 "to" 239 ". .

The column address decoder 23 of the dual port memory 16 has an address of 176 which is the same as the number of dots in the X direction of the liquid crystal display 13. Since the row address decoder 22 of the dual port memory 16 performs 8-bit simultaneous writing, it has 30 addresses that are the result of dividing 240, which is the number of dots in the Y direction of the liquid crystal display 13, by 8.
The information processing device 12 designates an arbitrary address to the column address decoder 23 and the row address decoder 22 via the information processing device logic circuit 17, thereby displaying display data to be displayed at an arbitrary position in the dual port memory 16. Data can be written via the information processing device logic circuit 17 and the information processing device read / write circuit 21.

In the display data, one bit corresponds to one dot displayed on the liquid crystal display 13. If the display data is “0”, the corresponding predetermined dot of the liquid crystal display 13 is displayed in white, and if it is “1”, it is displayed in black.
The display address decoder 24 has the same 240 addresses as the number of dots in the Y direction of the liquid crystal display 13. The display logic circuit 18 designates one of the display addresses “0” to “239”. When the display address is designated, the dual port memory 16 outputs 176 data in parallel with the number of dots in the X direction of the liquid crystal display 13 in parallel and supplies the data to the X driver 20. The X driver 20 converts the received display data into a voltage necessary for driving the liquid crystal display 13 and supplies it to the liquid crystal display 13 for driving.

  As shown in FIG. 3, the display logic circuit 19 includes 8-bit address counters 31a to 31c with set and reset, registers 32a to 32f for storing 8-bit addresses, an 8-bit counter 33 with reset, and two 8-bit systems. Selectors 34a to 34c for selecting either data A or B, coincidence detection circuits 35a to 35d for comparing two 8-bit data, and “L” when the “H” level is input to the reset terminal R. RS type flip-flops 36a to 36c that output a level and output the "H" level when the "H" level is input to the set terminal S, an OR gate 38 that forms a set signal for the counter 31b, and an 8-bit counter 31a To 31c and 33 and RS type flip-flops 36b to 36c. And a gate 39 that generates. In FIG. 3, all the buses are 8-bit buses.

  Here, the end address FUE (for example, “039”) of the upper fixed display data storage area 16U formed in the dual port memory 16 is set in the register 32a, and stored in the dual port memory 16 in the register 32b. The display start address SAS (for example, “040”) in the scroll display data storage area 16S is set, and the start address SAL of the scroll display data storage area 16S formed in the dual port memory 16 (for example, “040”) is set in the register 32c. 040 ") is set. Further, the end address SAE (for example, “199”) of the scroll display data storage area 16S formed in the dual port memory 16 is set in the register 32d, and the scroll display area 13S of the liquid crystal display 13 is set in the register 32e. An address DSE (for example, “139”) corresponding to the end of the liquid crystal display 13 is set, and an address FLL (for example, “200”) corresponding to the head of the lower fixed display area 13L of the liquid crystal display 13 is set in the register 32f. Yes.

Further, the reference clock signal DCLK is input to the clock input terminals CK of the address counters 31a to 31c. Every time the reference clock signal DCLK is input, the count value is counted up, and the count value is output to the output terminal. Output from O.
Among these, the address counter 31a receives the leading address DUs (for example, “000”) of the upper fixed display data storage area 16U of the dual port memory 16 at the data input terminal D, and the count value output from the output terminal O. Is output to the other input side of the coincidence detection circuit 35a and the data input terminal A of the selector 34b in which the final address FUE of the upper fixed display area set in the register 32a is input to one input side.

  The address counter 31b has a display start address SAS of the scroll data storage area 16S set in the register 32b selected by the selector 34a and a scroll display data storage area 13S set in the register 32c. One of the leading addresses SAL is input, and the logical sum output of the OR gate 39 to which the reset signal RES and the frame display completion signal DE are input is input to the reset terminal R, and the count value output from the output terminal O Is output to the other input side of the coincidence detection circuit 35b supplied to one input side, respectively, in the data input terminal B of the selector 34b and the end address SAE of the scroll display data storage area 16S set in the register 32d.

  Further, the counter 31c receives the address FLL corresponding to the head of the lower fixed display area 13L set in the register 32f at the data input terminal D and the logical sum of the above-mentioned ORAGE and 39 at the reset terminal R. An output is input, and an address DLE (for example, “239”) corresponding to the end of the input terminal B of the selector 34c and the lower fixed display area 13L of the liquid crystal display 13 is input to the output terminal O. Is output to the other input side of the coincidence detection circuit 35d supplied to the side.

The count value of the address counter 31a or 31b selected by the selector 34b is output to the data input terminal A of the selector 34c, and the count value selected by the selector 34c is output to the display address decoder 24 as the display address LAD. .
Further, the coincidence detection signal output from the coincidence detection circuit 35a is output to the reset terminal R of the flip-flop 36a and the set terminal S of the flip-flop 36b, and is output to one input side of the OR gate 38. The coincidence detection signal output from the coincidence detection circuit 35b is input to the input side.

The set signal output from the positive output terminal Q of the flip-flop 36a is input to the set terminal S of the selector 34a, and the set signal output from the positive output terminal Q of the flip-flop 36b is input to the set terminal S of the selector 34b. The output of the OR gate 38 is input to the set terminal S of the address counter 31b.
Furthermore, the coincidence detection signal output from the coincidence detection circuit 35 b is input to the set terminal S of the flip-flop 36 a and the other input side of the OR gate 38.

  Furthermore, the address DSE output from the output terminal O of the register 32e and the count value output from the output terminal O of the address counter 33 corresponding to the end of the scroll display area 13S of the liquid crystal display 13 are input to the coincidence detection circuit 35c. The coincidence detection signal output from the coincidence detection circuit 35c is input to the set terminal S of the address counter 31c and the set terminal S of the flip-flop 36c, and the set signal output from the positive output terminal Q of the flip-flop 36c is the selector. It is input to the set terminal S of 34c.

  The coincidence detection signal output from the coincidence detection circuit 35d is input to one input terminal of the OR gate 39 as the frame display completion signal DE, and the reset input from the display controller 18 to the other input terminal of the OR gate 39. The signal RES is input, the logical sum output of the OR gate 39 is input to the set terminal S of the address counter 31a as a set signal, and further, as the reset signal, the reset terminal R of the address counters 31b and 33 and the flip-flops 36b and 36c. Input to the reset terminal R.

  Here, as shown in FIG. 4, each of the coincidence detection circuits 35a to 35d has eight exclusives to which each bit position data in two-system 8-bit count values inputted to the input sides A and B is inputted. The exclusive NOR circuits EXN1 to EXN7, the AND gate AND1 to which the outputs of the exclusive NOR circuits EXN1 to EXN4 are input, the AND gate AND2 to which the outputs of the exclusive NOR circuits EXN5 to EXN8 are input, and the AND gate AND1 AND gate AND3 to which the output of AND2 is input, D-type flip-flop DFF to which the output of AND gate AND3 is input to the data input terminal, and an output signal output from positive output terminal Q of this flip-flop DFF AND gate A to which the reference clock signal DCLK is input It is composed of a D4, the coincidence detection signal CDS from the AND gate AND4 outputs.

  In addition, the reference clock signal DCLK is input to the clock terminal CK via the inverter INV, and the reset signal RES is input to the reset terminal R of the flip-flop DFF. Accordingly, when the two 8-bit signals input from the flip-flop DFF coincide with each other, an “H” level output signal is output from the positive output terminal Q at the fall of the next reference clock signal DCLK, and the AND gate AND4 To the next reference clock signal DCLK, the coincidence detection signal that is at the “H” level is output.

The display logic circuit 19 outputs from the oscillation device 15 after a predetermined time (for example, a time corresponding to one clock cycle of the reference clock signal DCLK) elapses after the first reset signal RES is input from the display controller 18. The reference clock signal DCLK is started to be supplied to each part.
The setting values for the registers 32a to 32f of the display logic circuit 19 are set by the display controller 18 including a microprocessor, for example. The display controller 18 receives from the external information processing apparatus 12 the end address FUE of the upper fixed display area, the start address SAL and end address SAE of the scroll display data storage area 16S, and the start address FLL of the lower fixed display data storage area 16L. A display composed of a scroll start address SAS for starting scroll display, an end address DSE of the scroll display area 13S, a step amount ST indicating the amount of address movement when scroll display is performed, a scroll period SP indicating a scroll display period, and the like. Control data is input and a display start command is input. Based on these, display control processing shown in FIG. 5 is executed to set the registers 32a to 32f of the display logic circuit 19 and to set the scroll cycle. External information processing at the start Generating an interrupt signal notifying that the start of the scroll time relative location 12.

  In this display control process, first, in step S1, it is determined whether or not display control data has been input from the external information processing apparatus 12. If no display control data has been input, the display control process waits until the display control data is input. When the control data is input, the process proceeds to step S2, the input display control data is updated and stored in a predetermined storage area of the memory 18a built in the display controller 18, and then the process proceeds to step S3.

  In this step S3, the end address FUE of the upper fixed display data storage area included in the display control data is written to the register 32a of the display logic circuit 19, the scroll start address SAS is written to the register 32b, and the scroll display data storage area start address SAL is written. Is written in the register 32c, the scroll display data storage area end address SAE is written in the register 32d, the scroll display area end address DSE is written in the register 32e, and the lower fixed display data storage area start address FLL is written in the register 32f.

  Next, the process proceeds to step S4, where it is determined whether or not a display start command is input from the external information processing apparatus 12, and when the display start command is not input, the process waits until it is input. When it is input, the process proceeds to step S5, and a power supply command for starting power supply to the Y driver 14 and the X driver 20 is output to the display power supply 25, and then the process proceeds to step S6 to reset the reset signal RES. Is output to the display logic circuit 19 and the reference clock signal DLCK is started to be supplied to the display logic circuit 19 with a slight delay.

Next, the process proceeds to step S7, where a scroll period counting timer that counts until the input scroll period SP is reached is started, and then the process proceeds to step S8 to add the step amount ST to the current display start address SAS. After calculating a new display start address SAS (= SAS + ST), the process proceeds to step S9.
In step S9, it is determined whether or not the scroll period SP has ended by determining whether or not the scroll period counting timer has expired. If the scroll period SP has not ended, the process proceeds to step S10. Then, it is determined whether or not the changed display control data is input from the information processing device 12. When the display control data is input, the process proceeds to step S11, and the changed display control data, that is, the step amount ST and / or After the scroll period SP is updated and stored in the memory 18a, the process returns to step S9. When the scroll period ends, the process proceeds to step S12.

  In this step S12, it is determined whether or not a display end command is input from the external information processing apparatus 12. When the display end command is input, the process proceeds to step S13, and the Y driver 14 is connected to the display power source 25. The power supply stop command for stopping the power supply to the X driver 20 is output, and the supply of the reference clock signal DCLK from the oscillation device 15 to the display logic circuit 19 is stopped, and then the process returns to the step S1.

  On the other hand, if the determination result in step S12 is that the display end command has not been input, the process proceeds to step S14 to determine whether or not the step amount ST is “0”, and the step amount ST is “0”. If it is determined that there is no scroll display, the process returns to step S7. If the step amount ST is set to a value other than “0”, it is determined that the display is scroll display and the process proceeds to step S15. After writing the display start address SAS calculated in step S8 into the register 32b, the process proceeds to step S16.

In step S16, an interrupt signal indicating the start time of the scroll period is output to the external information processing apparatus 12, and the process returns to step S7.
The process of FIG. 5 corresponds to the scroll display data reading means, these processing in steps S1 6 corresponds to the write start timing informing means.
The external information processing apparatus 12 also has a scroll display setting device 40 that selects whether or not the user performs scroll display on the image display apparatus 10 and a step amount setting that sets a step amount when scroll display is performed. A column address equal to the column address of the dual port memory 16 for storing display data and a row address larger than the row address of the dual port memory 16. A display data storage device 43 is connected, and based on these, the data display processing of FIG. 6 is executed, display control data is formed and output to the display controller 18, and document data input from the input keys, the Internet Form and display display data such as image data input via Stored in over data storage device 43, and writes to the dual port memory 16 and outputs the display data required for display on the liquid crystal display 13 of the display data stored in the information processing apparatus for logic circuit 17.

  The data display process is executed as a timer interrupt process for a predetermined main program every predetermined time (for example, several msec). First, in step S21, a display data write completion flag FE described later completes writing of initial display data. Whether or not the display data to be displayed on the liquid crystal display 13 is formed is determined by determining whether or not it is set to “1” indicating that it has been performed and if this is reset to “0”. When the display data is not formed, the process proceeds to step S23, and it is determined whether the display end key is pressed or not, and when it is the display end state, the process proceeds to step S24. Then, a display end command is output to the display controller 18, and then the process proceeds to step S25 where the display data writing completion flag FE is set. It is reset to 0 "to terminate the timer interruption processing returns to the predetermined main program, and returns to the predetermined main program as it ends the timer interrupt process when it is not in display termination state.

Further, when display data to be displayed on the liquid crystal display 13 is formed as a result of the determination in step S22, the process proceeds to step S26 to set the scroll display setting unit 40, the step amount setting unit 41, and the scroll period setting unit 42. After reading the data, the process proceeds to step S27.
In this step S27, it is determined whether or not the scroll display is selected by the scroll display setting device 40. If the scroll display is not selected, the process proceeds to step S28, and the step amount ST for performing the scroll display is set to “0”. In step S30, the scroll period SP is set to the standard value. If scroll display is selected, the process proceeds to step S29, and the step amount setting unit 41 sets the step amount ST. After the step amount is set and the scroll period set by the scroll period setting unit 42 is set as the scroll period SP, the process proceeds to step S30.

  In step S30, the preset final address FUE of the upper fixed display data storage area 16U in the dual port memory 16, the start address SAL of the scroll display data storage area 16S, the end address SAE of the scroll display data storage area 16S, the lower side Address information composed of the start address FLL of the fixed display data storage area 16L, the address DSE corresponding to the end of the scroll display area 13S of the liquid crystal display 13, the scroll display start address SAS, the step amount ST, and the scroll period SP. Display control data configured with the scroll information configured is transmitted to the display controller 18.

Next, the process proceeds to step S31, and the upper fixed display data to be displayed on the upper fixed display area 13U of the liquid crystal display 13 is output to the information processing device logic circuit 17 by designating the row address and the column address of the dual port memory 16. Then, the process proceeds to step S32.
In this step S32, the display data to be displayed first in the scroll display area 13S of the liquid crystal display 13 among the display data is designated by the physical row address and column address which are managed by the own display data storage device 43 and processed. After the initial display data writing process to be output to the device logic circuit 17 is performed, the process proceeds to step S33.

In this step S33, the lower fixed display data to be displayed in the lower fixed display area 13L of the liquid crystal display 13 is output to the information processing device logic circuit 17 by designating the row address and column address of the dual port memory 16.
Next, the process proceeds to step S34, where a display start command is output to the display controller 18, and then the process proceeds to step S35 where the display data write completion flag FE is set to "1" and then the process proceeds to step S23. .

  On the other hand, when the determination result of step S21 is that the display data write completion flag FE is set to “1” indicating completion of initial writing to the dual port memory 16, the process proceeds to step S36 and each setting device 40 The setting data of .about.42 is read, and then the process proceeds to step S37 to determine whether or not there has been a change to the previous setting data. After the setting data is transmitted to the display controller 18, the process proceeds to step S39, and when there is no change in the setting data, the process directly proceeds to step S39.

In step S39, it is determined whether or not scroll display is selected by the scroll display setting unit 40. If scroll display is not selected, the process proceeds to step S40, and the display data writing completion flag FE is set to “0”. After resetting, the process proceeds to step S23, and when scroll display is selected, the process proceeds to step S41.
In step S41, it is determined whether or not an interrupt signal indicating the start time of the scroll period is input from the display controller 18, and if no interrupt signal is input, the process proceeds to step S23 as it is, and the interrupt signal is input. If YES in step S42, the flow advances to step S42 to determine whether or not priority processing other than display processing exists. If there is no priority processing, the flow jumps to step S44 described later. If priority processing exists, the flow advances to step S43. Then, the timer value of the scroll period counting timer activated by the display control process of the display controller 18 is read to determine whether or not it is greater than or equal to a predetermined value. When the scroll period counting timer is less than the predetermined value, the step is performed. The process proceeds to S23, and when it is equal to or larger than the predetermined value, the process proceeds to Step S44. A physical row address for managing display data corresponding to the step amount ST by the display data storage device 43 in a data storage area continuous in the scroll direction of the display data displayed in the scroll display area 13S of the existing liquid crystal display 13 Then, the scroll data writing process for designating the column address and outputting it to the information processing device logic circuit 17 is performed, and then the process proceeds to step S45.

  In this step S45, it is determined whether or not the fixed display data displayed on the upper and lower fixed display areas 13U and 13L of the liquid crystal display 13 has been changed. If the fixed display data has been changed, the process proceeds to step S46. The fixed display data to be written in the upper and / or lower fixed display data storage areas 16U and / or 16L corresponding to the changed fixed display data is output to the information processing device logic circuit 17, and then the step S23 is performed. If there is no change in the fixed display data, the process proceeds to step S23.

In the process of FIG. 6, the process of step S29 and the step amount setting unit 41 correspond to the step amount setting means, the process of step S30 corresponds to the step amount notification means, and the processes of steps S32 and S41 to S46 are scrolled. This corresponds to display data writing means.
On the other hand, when the display data to be written to the dual port memory 16 is input from the information processing device 12 to the logic circuit 17 for the information processing device, the column address is output to the column address recorder 23 for the information processing device as it is and the row address is also displayed. For this, the type of display data is discriminated, the relative address of the dual port memory 16 is calculated, and the address conversion process for outputting this to the row address decoder 22 for the information processing apparatus is executed.

  In this address conversion process, as shown in FIG. 7, first, in step S51, it is determined whether or not display data is input. If no display data is input, the process waits until the display data is input, and the display data is input. If YES in step S52, the flow advances to step S52 to determine whether or not the display data input from the information processing device 12 is upper fixed display data. If this is upper fixed display data, the flow advances to step S53 to be described later. After performing the upper fixed display data writing process, the process returns to step S51, and when it is not the upper fixed display data, the process proceeds to step S54.

  In this step S54, it is determined whether or not the input display data is the lower fixed display data. If this is the lower fixed display data, the process proceeds to step S55 to write the lower fixed display data to be described later. After the processing, the process returns to step S51. When the display data is not the lower fixed display data, it is determined that the display data is scroll display data, the process proceeds to step S56, the scroll display data writing process is performed, and the process returns to step S51.

The upper fixed display data write processing in the step S53, as shown in FIG. 8, first, the information processing apparatus for logic circuit leading row address AD _UL of the upper fixed display data input in step S61 as the conversion address value CADU After the data is stored in the memory 17a built in 17, the process proceeds to step S62.
In this step S62, the conversion row CADU stored in the memory 17a is subtracted from the inputted row address AD _Ui to calculate the physical row address LAD _Ui of the dual port memory 16, and then the process proceeds to step S63. Thus, the calculated physical row address LAD _Ui of the dual port memory 16 is output to the row address decoder 22 for the information processing apparatus, and the column address input from the information processing apparatus 12 is directly used as the column address decoder 23 for the information processing apparatus. The display data is further output to the read / write circuit 21 for the information processing apparatus, and the process proceeds to step S64.

In this step S64, it is determined whether or not the upper fixed display data has been written. This determination is performed by determining whether or not the row address LAD _Ui calculated in step S63 matches the end address FUE of the upper fixed display data storage area 16S of the dual port memory 16, and when LAD _Ui <FUE The process proceeds to step S65, the next upper fixed display data is read, and then the process returns to step S62. When LAD _Ui = FUE, it is determined that the upper fixed display data has been written and the upper fixed display data is written. The process ends and the process returns to step S51 in FIG.

In the lower fixed display data writing process in step S55 in FIG. 7, as shown in FIG. 9, first, in step S71, the top row address AD _LL of the input upper fixed display data is changed to the logic for the information processing apparatus. stored in the memory 17a incorporated in the circuit 17, then the process proceeds to step S72, the in the first physical address FLL of the stored first row address AD _LL and the lower fixed display data storage area 16L of the dual port memory 16 Based on the calculation of the following equation (1), the conversion address value CADL is calculated, stored in the memory 17a, and the process proceeds to step S73.

CADL = AD _LL −FLL (1)
In step S73, the physical row address LAD _Li of the dual port memory 16 is calculated by subtracting the conversion address value CADL stored in the memory 17a from the input row address AD _LL, and then the process proceeds to step S74. Thus, the calculated physical row address of the dual port memory 16 is output to the information processing device row address decoder 22 and the column address input from the information processing device 12 is output to the information processing device column address decoder 23 as it is. Further, after the display data is output to the read / write circuit 21 for the information processing apparatus, the process proceeds to step S75.

In this step S75, it is determined whether or not the writing of the upper fixed display data is completed. This determination is performed by determining whether or not the row address LAD _Li calculated in step S73 matches the end address FLE of the lower fixed display data storage area 16L of the dual port memory 16, and LAD _Li <FLE. Sometimes the process proceeds to step S76, the next scroll display data is read, and then the process returns to step S73. When LAD _Li = FLE, it is determined that the upper fixed display data has been written and the upper fixed display data is written. The process ends and the process returns to step S51 in FIG.

Further, in the scroll display data writing process in step S56 in FIG. 7, first, in step S81, the leading row address AD _SL of the input scroll display data is sent to the information processing device logic circuit 17 as shown in FIG. stored in the memory 17a of the built and then proceeds to step S82, the following on the basis of the first physical address SAL scroll display data storage area 16S of the leading row address AD _SL and the dual port memory 16 stored (2 ) To calculate the conversion address CADS, which is stored in the memory 17a, and then proceeds to step S83.

CADS = AD _SL −SAL (2)
At step S83, the subtracting the converted address CADS stored from the row address AD _SL input to the memory 17a calculates the physical row address LAD _Si of the dual port memory 16, then, it proceeds to step S84 Then, it is determined whether or not the calculated row address LAD _Si has exceeded the end address SAE of the scroll display data storage area of the dual port memory 16, and if LAD _Si > SAE, the process proceeds to step S85 to input the input row The address AD _SL is newly updated and stored in the memory 17a, and then the process returns to step S82. If LAD _Si ≦ SAE, the process proceeds to step S86.

In step S86, the calculated physical row address LAD _Si of the dual port memory 16 is output to the information processing device row address decoder 22, and the column address input from the information processing device 12 is used as it is. The data is output to the address decoder 23, and the display data is further output to the information processing device read / write circuit 21. Then, the process proceeds to step S87.

  In this step S87, it is determined whether or not writing of scroll display data is completed. This determination is performed by determining whether or not a scroll display data writing completion command has been input from the information processing apparatus 12. If the scroll display data writing completion command has not been input, the process proceeds to step S88. After the next scroll display data is read, the process returns to step S83. When a scroll display data write completion command is input, the scroll display data writing process is terminated and the process returns to step S51 of FIG.

7 to 10, steps S61 to S65, S71 to S75, and S81 to S87 correspond to address conversion means.
Next, the operation of the first embodiment will be described.
Now, assuming that display data to be displayed on the liquid crystal display 13 is not formed by the information processing apparatus 12 and a display end command is output to the display controller 18, the display control process of FIG. Then, the process proceeds from step S12 to step S13, and when the power supply stop command is output to the display power supply 25, the energization to the Y driver 14 and the X driver 20 is stopped, and the display on the liquid crystal display 13 is displayed. It is in a stopped state.

  In this display stopped state, the display data write completion flag FE is reset to “0” when the information processing apparatus 12 performs the data display process of FIG. 6, and therefore the process proceeds from step S21 to step S2. Since display data to be displayed on the liquid crystal display 13 is not formed, the process proceeds to step S23, and since the display end key is not pressed, the timer interruption process is ended as it is.

From this display stopped state, the information processing device 12 takes in display data including image data of the Internet, receives an e-mail, or starts creating document data by a key operation. Display data that needs to be displayed at 13 is created and stored in the display data storage device 43.
At this time, as shown in FIG. 2, in the data storage area 43a of the display data storage device 43, for example, “○” is displayed in the upper display data area 13U of the liquid crystal display 13 at the management addresses “010” to “049”, for example. The upper fixed display data represented by the above is stored, the display data to be displayed in the scroll display area 13S of the liquid crystal display 13 is stored in the management addresses “800” to “899”, and the management addresses “1060” to “1099” are stored. For example, it is assumed that lower fixed display data represented by “Δ” is stored.

In response to this, the information processing apparatus 12 reads the setting data of the setting devices 40 to 42 in the data display process of FIG. 6 (step S26).
At this time, if the scroll display setting unit 40 does not select scroll display, the step amount ST is set to “0” and the scroll period SP is set to the standard value (step S28).

  Then, the final address FUE of the upper fixed display data storage area 13U in the preset dual port memory 16, the start address SAL of the scroll display data storage area 16S, the end address SAE of the scroll display data storage area 16S, the lower fixed display data Address information composed of a start address FLL of the storage area 16L, an address DSE corresponding to the end of the scroll display area 13S of the liquid crystal display 13, and scroll information composed of a display start address SAS, a step amount ST, and a scroll period SP. The display control data constituted by is transmitted to the display controller 18 (step S30).

  Therefore, when the display control data is input from the information processing apparatus 12 in the process of FIG. 5, the display controller 18 stores the input display control data in the memory 18a (step S2), and then the display control data. Is written in the register 32a of the display logic circuit 19, the scroll start address SAS is stored in the register 32b, the scroll display data storage area start address SAL is stored in the register 32c, and the scroll display data is stored. The area end address SAE is written in the register 32d, the scroll display area end address DSE is written in the register 32e, and the lower fixed display data storage area start address FLL is written in the register 32f (step S3). Is entered In to wait.

The information processing device 12 outputs the display control data to the display controller 18 and then writes the data to the upper fixed display data storage area 16U of the dual port memory 16, for example, upper fixed display data for displaying an antenna display or the like indicating the reception sensitivity. The information representing the type is output to the information processing device logic circuit 17 (step S31).
Therefore, in the information processing device logic circuit 17, since the upper fixed display data is input by executing the processing of FIG. 7, the process proceeds from step S51 to S52 to step S53, and the upper side shown in FIG. The fixed display data writing process is executed.

In this upper fixed display data writing process, since the row address of the upper fixed display data input from the information processing device 12 is “010” to “049”, the leading row address AD _UL (= “010”) is set. when entered, the row address AD _UL of the head is stored in the memory 17a as converted address value CADU (step S61), and then converted address value CADU from the input row address AD _Ui (= "010") (= “010”) is subtracted to calculate the physical row address LAD _Ui of the dual port memory 16 (step S62).

Therefore, the row address LAD _Ui of the dual port memory 16 becomes “000”, and this row address LAD _Ui is output to the information processing device row address decoder 22 and the column address input from the information processing device 12 is the information. By being output to the processing device column address decoder 23 and the display data being output to the information processing device read / write circuit 21, the upper side of the first row address “000” of the upper fixed data display area 16 U of the dual port memory 16 is increased. When the writing of the fixed display data is started and the writing of the upper fixed display data for all the column addresses is completed, the upper fixed display data designating the next row address “011” is output from the information processing device 12.

  At this time, the information processing device logic circuit 17 continues the processing of FIG. 8, and therefore, by subtracting the conversion address value CADU from the current row address “011” in step S 62, The row address “001” is calculated, data is written to the row address, and then the upper fixed display data is sequentially written. When the data write of the final row address “049” is completed, the write is performed. The completion command is output to the information processing device logic circuit 17, and the process returns from step S64 to step S51 in FIG. 7 to complete the upper fixed display data writing process.

Next, when the scroll display data is output from the information processing device 12 to the information processing device logic circuit 17 together with a command representing the type, the information processing device logic circuit 17 executes the processing of FIG. After steps S51, S52, and S54, the process proceeds to step S56, and the scroll display data writing process of FIG. 10 is executed.
In this scroll display data writing process, when the first management address AD _SL (= “800”) of the scroll display data in the display data storage device 43 is input, it is stored in the memory 17a, and then the (2 ) and determines the start of the management address AD leading address of the scroll display data storage area 16S from _SL dual port memory 16 SAL (= "040") a subtraction to convert address value CADS (= "760") in accordance with equation ( In step S82), the conversion address value CADS (= “760”) is subtracted from the input management address AD _SL (= “800”) to correspond to the start address of the scroll display data storage area 16S of the dual port memory 16. A row address LAD _Si (= “040”) is calculated (step S83).

Since the calculated row address LAD _Si (= “040”) is smaller than the end address SAE (= “199”) of the scroll display data storage area 16S of the dual port memory 16, the process proceeds from step S84 to step S86. The row address LAD _Si (= “040”) and the column address are output to the information processing device row address decoder 22 and the information processing device column address decoder 23, respectively, and the display data is output to the information processing device read / write circuit 21. As a result, the writing of the scroll display data is started at the first row address of the scroll display data storage area 16S of the dual port memory 16.

  Thereafter, the scroll display data is sequentially written to the scroll display data storage area 16S, and when the scroll display data is written to the row address “139” corresponding to the end display position of the scroll display area 13S of the liquid crystal display 13, the writing is completed. When the write completion command is output from the information processing device 12 to the logic circuit 17 for the information processing device, the process returns from step S87 in FIG. 10 to step S51 in FIG. 7 to finish the scroll display data writing process. .

  Next, when the lower fixed display data is output from the information processing device 12, the lower fixed display data of the management address “1060” of the display data storage device 43 is displayed together with a command indicating the type of the information processing device logic circuit 17. In response to this, in the process of FIG. 7, the process proceeds from step S51 to S52 and S54 to step S55, and the lower fixed display data writing process of FIG. 9 is executed.

  In this lower fixed display data writing process, when the first management address “1060” of the data storage area of the display data storage device 43 is input, it is stored in the memory 17a (step S71), and then the (1 ) To calculate the conversion address value CADL. At this time, since the head management address is “1060” and the head address FLL of the lower fixed display data storage area 16L of the dual port memory 16 is “200”, the conversion address value CADL is “860”. .

Therefore, when the row address LAD _Li of the dual port memory 16 is calculated by subtracting the conversion address value CADL (= “860”) from the current management address AD _LL (= “1060”) in step S73, 200 ", writing of the lower fixed display data to the start address FLL (=" 200 ") of the lower fixed display data storage area 16L of the Durport memory 16 is started, and writing to all the column addresses is completed. Since the next management address AD _Li becomes “1061”, the second row address “201” of the lower fixed display data storage area 16L of the dual port memory 16L is calculated in step S73, and the data to this row address is calculated. Is written. Thereafter, when the display data of the management address “1099” is written from the information processing device 12 to the row address “239” of the dual port memory 16, a write completion command is sent from the information processing device 12 to the logic circuit 17 for the information processing device. As a result of the output, the process returns from step S64 to step S51 of FIG.

  When the writing of the display data to the upper fixed display data storage area 16U, the scroll display data storage area 16S, and the lower fixed display data storage area 16L of the dual port memory 16 is completed by the writing process, the information processing apparatus 12 displays the display data. A display start command is output to the controller 18 (step S34), and the display data write flag FE is set to "1" (step S35).

  When a display start command is input from the information processing device 12, the display controller 18 outputs a power supply command to the display power supply 25 (step S <b> 5), thereby the Y driver 14 and the X driver from the display power supply 25. 20 is supplied with electric power. Next, the reset signal RES is output to the display logic circuit 19 and the supply of the reference clock signal DCLK from the oscillation device 15 to the display logic circuit 19 is started slightly later than this (step S6). Next, a scroll period counting timer is started (step S7).

  In the display logic circuit 19, as shown in FIG. 12A, when a reset signal RES is input from the display controller 18, this is supplied as a set signal to the set terminal S of the address counter 31a, whereby this address counter “000” set in the data input terminal D of 31a is set as the count value, and this is supplied from the output terminal O to the input terminal A of the selector 34b.

  On the other hand, when the logical sum of the reset signal RES and the frame display completion signal DE is supplied to the reset terminal R of the RS flip-flop 36b, the output of the positive output terminal Q becomes low, which is the set terminal of the selector 34b. Therefore, the selector 34b selects the input terminal A, and "000" input to the input terminal A is input to the input terminal A of the selector 34c.

  At this time, since the logical sum of the reset signal RES and the frame display completion signal DE is input to the reset terminal R of the RS flip-flop 36c, the positive output terminal Q becomes low, and the selector 34c inputs the input terminal. A is selected, and “000” input to the input terminal A is output to the display address decoder 24 as the display address LAD.

In addition, the reference clock signal DCLK output from the oscillation device 15 with a predetermined time delay from the input of the reset signal RES is started to be supplied to the address counters 31a to 31c and 33.
Therefore, the display data of the top address “000” in the upper fixed display data storage area 16U of the dual port memory 16 is read as shown in FIG. 12C, and this is the X driver 20, which is shown in FIG. They are taken in as shown in FIG. 12 (d) at the fall of the reference clock signal DCLK.

Further, as shown in FIG. 12 (e), the display logic circuit 19 outputs a selection signal YDATA that becomes a high level from the rising edge of the reset signal RES to the next rising edge of the reference clock signal DCLK to the Y driver 14, and Y The driver 14 performs line selection when the selection signal YDATA is at a high level, and enters a line non-selection state when the selection signal YDATA is at a low level.
The Y driver 14 takes in the selection signal YDATA at the falling edge of the reference clock signal DCLK, and transfers the selection signal YDATA by each register of an internal 180-stage shift register (not shown). Each register output of the 180-stage shift register sequentially moves to the right according to the reference clock signal DCLK as shown in FIGS. 12 (e0) to (e179).

When the driver data of the X driver 20 is the data of the display address “000”, the selection signal Y 0 of the Y driver 14 becomes high level, so that the data of the display address “000” is displayed on the first line of the liquid crystal display 13. Is done.
After that, every time the reference clock signal DCLK is sequentially input, the count value of the address counter 31a is counted up as shown in FIG. 12C at the rising edge, and the X driver 20 shows it at the falling edge of the reference clock signal DCLK. Data is taken in as shown in FIG.

  On the other hand, in the display logic circuit 19, as shown in FIG. 13C, the count value of the address counter 31a is counted up at the rising edge of the reference clock signal DCLK shown in FIG. 13B, and this count value is stored in the register 32a. When the set FUS is “039”, the 8-bit comparison output CS of the coincidence detection circuit 35a becomes a high level as shown in FIG. 13 (d), and the output FOS of the D-type flip-flop DFF is accordingly changed as shown in FIG. The coincidence detection signal CDS which is at a high level as shown in (e) and is at a high level between the rise and fall of the reference clock signal DCLK as shown in FIG. 13 (f) is output from the AND gate AND4.

On the other hand, the address counter 31b is reset to “000” when the reset signal RES is input, and in this state, a high level set signal is not input to the set terminal S, so that FIG. As shown in FIG. 4, the count is incremented every time the reference clock signal DCLK is input.
In this state, when the high-level coincidence detection signal CDSa is output from the coincidence detection circuit 35a as described above, this is input to the reset terminal R of the RS flip-flop 36a, so that the set terminal S of the selector 34a becomes By going low, the SAS “040” set in the register 32b input to the input terminal A is selected and supplied to the data input terminal D of the address counter 31b. Therefore, when the coincidence detection signal CDSa is input to the set terminal S of the address counter 31b via the OR gate 38, the count value of the address counter 31b is changed from “039” to “040” as shown in FIG. The count value “040” is input to the input terminal B of the selector 34b, and the high-level match detection signal CDSa is supplied from the match detection circuit 35a to the set terminal S of the RS flip-flop 36b. When this is set and the positive output becomes high level and is input to the selector 34b, the selector 34b selects the count value “040” of the address counter 31b supplied to the input terminal B, and this is selected. 34c is supplied to the input terminal A.

For this reason, the display address LAD output from the selector 34c becomes “040” as shown in FIG. 13 (o), and the count value of the address counter 31b is counted up every time the reference clock signal DCLK is input thereafter. The display address LAD output from the selector 34b is counted up as shown in FIG.
The address counters 31c and 33 are also incremented each time the reference clock signal DCLK is input after being cleared to “000” by the reset signal RES as shown in FIG. 13 (k).

  Thereafter, when the count value of the address counter 33 reaches the scroll display area end address DSE (= “139”) set in the register 32e, a high level coincidence detection signal CDSc from the coincidence detection circuit 35c is shown in FIG. 13 (j). When this is input to the set terminal S of the address counter 31c, the start address FLL (= “200”) of the lower fixed display data storage area 16L set in the register 32f is set as the count value. The count value “200” is input to the input terminal B of the selector 34c.

  On the other hand, since the coincidence detection signal CDSc outputted from the coincidence detection circuit 35c is inputted to the set terminal S of the RS flip-flop 36c, the flip-flop 36c is set, and the positive output thereof becomes a high level, and this is outputted to the selector 34c. Since it is input to the set terminal S, the selector 34c selects the count value “200” of the address counter 31c input to the input terminal B, and this is output as the display address LAD as shown in FIG. 13 (o). Is done.

Thereafter, the count value of the address counter 31c is incremented every time the reference clock signal DCLK is input, and this count value is selected by the selector 34c and output as the display address LAD.
Thereafter, when the count value of the address counter 31c becomes “239”, the coincidence detection circuit 35d outputs a high-level coincidence detection signal DE as shown in FIG.

  Therefore, the display addresses LAD output from the display logic circuit 19 are “000” to “039”, “040” to “139”, “200” to “239”, and the upper fixed display data of the dual port memory 16. Upper fixed display data stored in the storage area 16U, scroll display data from addresses "040" to "139" in the scroll display data storage area 16S, and lower fixed display data stored in the lower fixed display data storage area 16L As the display data is sequentially read out and displayed on the liquid crystal display 13, as shown in FIG. 11, the upper fixed display data “A” to “A” represented by “O” are displayed on the liquid crystal display 13. Scroll display data represented by “J” and lower fixed display data represented by “Δ” are displayed.

  During this time, in the information processing apparatus 12, since the display data write flag FE is set to “1”, the process proceeds from step S21 to step S36, and the setting data of the setting devices 40 to 42 is read and changed to these. If there is no, the process proceeds to step S39, and if the scroll display is not selected, the process proceeds to step S40, the display data write flag FE is reset to “0”, and the display end is selected. The timer interrupt process is terminated as it is. For this reason, when new display data is not created in the next timer interrupt process, the process proceeds from step S22 to step S23, and then the timer interrupt process is terminated. Therefore, the display control process in the information processing apparatus 12 is simplified, and the burden of the display control process can be reduced.

On the other hand, the display controller 18 proceeds to step S8, and calculates a new display start address SAS by adding the step amount ST set to “0” to the current display start address SAS (= “040”). However, since the step amount ST is “0”, the display start address SAS is not changed.
Thereafter, it is determined whether or not the scroll period counting timer has expired, and it is determined whether or not the scroll period SP has ended. When the scroll period SP has not ended, the display changed from the information processing device 12 is displayed. It is determined whether or not control data has been input (step S12). Since no display control data has been input, the process returns to step S11 as it is, and when this state is repeated and the scroll period SP is completed, the process proceeds to step S14. Thus, it is determined whether or not a display end command has been input from the information processing apparatus 12. However, since the display end command has not been input, the process proceeds to step S16, and the step amount ST is “0”. Return to, and start the scroll period counting timer again. Further, the counters 33, 31b, 31c and the flip-flops 36b, 36c are reset by the coincidence detection signal DE, and the counter 31a is set. Therefore, the display logic 19 performs the same operation as described above, and FIG. The display state of the upper fixed display area 13U, the scroll display area 13S, and the lower fixed display area 13L is continued.

  In the fixed display state of the scroll display area 13S, scroll display is selected by the scroll setting device 40 of the information processing apparatus 12, the step amount ST is set to, for example, “020” by the step amount setting device 41, and the scroll period is set. When the desired scroll period SP is set by the device 42, the information processing apparatus 12 determines that the setting data has been changed in step S37, proceeds to step S38, transmits the changed data to the display controller 18, and then selects the scroll display. Thus, the process proceeds from step S39 to step S40, and since the scroll display completion interrupt signal is not input from the display controller 18, the timer interrupt process is terminated through step S23 and the process returns to the predetermined main program.

When the display controller 18 receives the display control data changed in step S10 in the display control process of FIG. 5, the display controller 18 proceeds to step S11 and stores the changed display control data, that is, the step amount ST and the scroll period SP in the memory 18a. After updating and storing, the process returns to step S9 and waits until the end of the scroll period SP.
When the scroll period counting timer expires and the scroll period SP ends, the process proceeds from step S9 to step S12. Since no display end command is input, the process proceeds to step S14 and the step amount ST is “000”. Therefore, the process proceeds to step S15, and the display start address SAS is written into the register 32b. Next, the process proceeds to step S16, an interrupt signal indicating the start time of the scroll period is output to the external information processing apparatus 12, and then the process returns to step S7 to start the scroll period count timer set to the roll period SP. To do.

However, since the display start address SAS is not changed at this time, the display start address SAS is maintained at “040”, and the display state before the scroll selection is maintained.
On the other hand, in the information processing apparatus 12, when an interrupt signal indicating completion of scroll display is input from the display controller 18, since scroll display is selected, the process proceeds from step S39 to step S41 to step S42. It is determined whether or not priority processing that prioritizes processing over display control exists. If priority processing does not exist, the process proceeds directly to step S44 to write to the scroll display data storage area 16S of the current dual port memory 16. Scroll display data in which new display data “K” and “L” are written in the row addresses “040” to “139”, which are continuously stored in the scroll direction, that is, the row addresses “140” to “159”. After performing the write process, the timer interrupt process is terminated through step S23 and the program returns to the predetermined main program. That.

  If priority processing exists, the process proceeds to step S43 to read the timer value of the scroll period counting timer, and until the current scroll period SP ends, the scroll amount corresponding to the step amount ST is reached. It is determined whether or not the display data is equal to or greater than a predetermined value corresponding to the time required to complete the writing to the scroll display data storage area 16S of the dual port memory 16, and if it is less than the predetermined value, the process proceeds to step S23. When the value is equal to or greater than the predetermined value, the process proceeds to step S44, where scroll display data writing processing for writing new display data “K” and “L” is performed.

In any case, the writing of scroll display data to the scroll display data storage area 16S of the dual port memory 16 is completed before the next scroll period SP is started.
Then, the process proceeds to step S8, and a value obtained by adding the step amount ST (= “020”) to the current display start address SAS (= “040”) is calculated as a new display start address SAS (= “060”). Then, the process waits until the scroll period counting timer expires and the scroll period SP ends.

Thereafter, when the scroll period SP is completed, the process proceeds from step S9 to step S12 to step S14. Since the step amount ST is set to a value other than “000”, the process proceeds to step S15 and the display start address SAS. Is transferred to the register 32b, and then the process proceeds to step S16 to output an interrupt signal indicating the start point of the scroll period to the external information processing apparatus 12. The display logic circuit 19 sequentially outputs “000” to “039”, “060” to “159”, and “200” to “239” as the display address LAD. In this way, scroll display data represented by character data “C” to “L” is displayed.

As described above, the display data for the scroll corresponding to the step amount ST at the time of the next scrolling is written between the scroll periods SP, which is the cycle at which the display address LAD is output from the display logic circuit 19, and then the dual port. Since the display data of the memory 16 is read and supplied to the liquid crystal display 13, scroll display is sequentially performed.
Then, after writing from the information processing device 12 to the end address “199” of the scroll display data storage area 16S in the dual port memory 16 is finished, when the scroll display data is written next, the display data storage device 43 Since the management address AD _Si is “960”, the row address LAD _Si calculated in step S 83 is “200” obtained by subtracting “760” from “960”, and the scroll display data storage area 16 S of the dual port memory 16. Therefore, the process proceeds to step S85, and the row address AD _Si (“960”) output from the information processing apparatus 12 is updated and stored in the memory 17a. Control goes to step S82.

Therefore, the conversion address value CADS (= “920”) is calculated by subtracting the head address SAL (= “040”) of the scroll display data storage area 16S from the stored row address AD _Si (“960”). Since this is updated and stored in the memory 17a, the row address LAD _Si calculated in step S83 becomes “040”, the start address SAL of the dual port memory 16S is designated, and scroll display data is written to this, and the following The row address to be sequentially written is increased.

  In response to this, the display start address SAS written in the register 32c of the display logic circuit 19 also sequentially increases by the step amount ST (= “020”), whereby the match detection signal CDSa is supplied from the match detection circuit 35a. The count value set in the address counter 31b at the time of output increases and, as shown in FIG. 15 (h), before the count value of the address counter 33 reaches “139”, the SAE “ When reaching 199 ″, the coincidence detection circuit 35b outputs a coincidence detection signal CSb at a high level as shown in FIG. 15 (i).

  Since the coincidence detection signal CDSb is supplied to the set terminal S of the RS flip-flop 36a, the output of the positive output terminal Q of the flip-flop 36a becomes high level, and the dual port memory set in the register 32c by the selector 34a 16 is selected as the leading address SAL (= “040”) of the scroll display data storage area, which is input to the data input terminal D of the address counter 31b, and the coincidence detection signal CSb of the coincidence detection circuit 35b is input to this address counter 31b. Therefore, the count value is set to the head address SAL (= “040”) and this is supplied to the selector 34b. At the time when the coincidence detection signal CDSa is output from the coincidence detection circuit 35a in the selector 34b. Since input terminal B is selected, Head address SAL (= "040") is supplied to the selector 34c, and output to the display address decoder 24 as the display address LAD.

Therefore, the scroll display data is read from the start address “040” of the scroll display data storage area 16S of the dual port memory 16, and the scroll display is continued.
Thereafter, when a key or the like for ending the display process is operated on the information processing apparatus 12, the process proceeds from step S23 to step S24 in the data display process of FIG. 6, and a display end command is output to the display controller 18, Next, after the display data write flag FE is reset to “0”, the timer interrupt process is terminated and the process returns to a predetermined main program.

  For this reason, in the display controller 18, when a display end command is input, the process proceeds from step S 14 to step S 15, and a power supply stop command is output to the display power supply 25, to the Y driver 14 and the X driver 20. And the input of the reference clock signal DCLK from the oscillation device 15 to the display logic circuit 19 is stopped, and the data display on the liquid crystal display 13 is ended.

  Thus, according to the above embodiment, when the display data is displayed on the liquid crystal display 13 by the information processing device 12, the display data storage device 43 of its own is displayed together with the command indicating the type of display data from the information processing device 12. By directly outputting the row address and column address used in the processing to the logic circuit 17 for the information processing apparatus, the row address is converted into the row address used in the dual port memory 16 by the logic circuit 17 for the information processing apparatus. Therefore, it is not necessary to control the data write address of the dual port memory 16 on the information processing device 12 side, and the display data write processing to the dual port memory 16 is greatly compared with the conventional example. The processing efficiency of the information processing apparatus 12 can be significantly improved.

  Further, at the time of scroll display, display data reading processing from the scroll display data storage area 16S of the dual port memory 16 is performed by the display controller 18 and the display logic circuit 19, and the information processing device 12 responds to the step amount ST within the scroll period. The scroll display data may be written based on an interrupt signal input from the display controller 18, and the load of the scroll display processing in the information processing apparatus 12 can be greatly reduced. This can be performed effectively, and the processing efficiency of the information processing apparatus 12 can be further improved.

  In the above embodiment, the case where the address conversion is performed for all of the upper fixed display data storage area 16U, the scroll display data storage area 16S, and the lower fixed display data storage area 16L in the logic circuit 17 for the information processing device has been described. However, the present invention is not limited to this, and the upper fixed display data storage area 16U and the lower fixed display data storage area 16L are less frequently subjected to address conversion processing than the scroll display data storage area 16S. Steps S52 to S55 and the processes in FIGS. 8 and 9 may be omitted, and the address conversion process may be performed only when the scroll display data is written in the scroll display data storage area 16S.

  In the above embodiment, the case where the upper fixed display data, the scroll display data, and the lower fixed display data are output in this order from the information processing apparatus 12 has been described. However, the present invention is not limited to this, and any order may be used. The display data can be output to the information processing device logic circuit 17.

  Further, in the above embodiment, the display controller 18 outputs an interrupt signal to the information processing apparatus 12 at the end of the scroll period SP, that is, at the start of the scroll period SP, and the information processing apparatus 12 uses the scroll period counting timer. However, the present invention is not limited to this. As shown in FIG. 16, the information processing apparatus 12 omits step S43 in the above-described processing of FIG. Instead, if it is determined in step S42 that there is priority processing, the process proceeds to step S47, and writing for the scroll display data is performed from the time when the scroll display completion interrupt signal is input until the end of the scroll period SP. The write start timing determination timer that determines the write start timing that can be completed is started. If the write start timing determination timer is not started, the process proceeds to step S48, and after starting the write start timing determination timer, the process proceeds to step S49. If it has been activated, the process proceeds directly to step S49. In step S49, it is determined whether or not the write start timing determination timer has expired. If it has not expired, the process proceeds to step S23. It may be determined that it is the timing to start loading, and the process may proceed to step S44. In this case, since it is not necessary for the information processing device 12 to read the timer value of the step S scroll period counting timer, the load of the data display processing of the information processing device 12 can be reduced accordingly. Furthermore, the display controller 18 measures the timing at which writing of scroll display data in the information processing device 12 can be completed before the end of the scroll period SP, and outputs a write interrupt signal to the information processing device 12. In this case, the data display processing load on the information processing apparatus 12 can be further reduced.

  Furthermore, in the above embodiment, only the display data corresponding to the scroll display area 13S of the liquid crystal display 13 is displayed in the initial display data writing process (step S32) to the scroll display data storage area 16S of the dual port memory 16. However, the present invention is not limited to this, and the initial display data writing process corresponds to the display data corresponding to the scroll display area 13S of the liquid crystal display 13 and the scroll step amount ST. When the display data obtained by adding the scroll display data to be written is written and placed, the writing to the scroll display data storage area 16S in the dual port memory 16 in the information processing device 12 does not end before the school period SP ends. Scroll display data being written is displayed when Is the it is possible to reliably avoid.

  In the above embodiment, the case has been described in which the scroll display data written in the scroll display data storage area 16S of the dual port memory 16 by the information processing apparatus 12 at the time of scroll display is the data amount corresponding to the step amount ST. However, the present invention is not limited to this, and scroll display data corresponding to an integer n times the step amount ST may be written once, and the scroll display data may be written once every integer n times. In this case, the writing process of the scroll display data in the information processing apparatus 12 can be further reduced.

  Furthermore, in the above-described embodiment, the case where the display controller 18 outputs an interrupt signal indicating the start time of the scroll period SP to the information processing apparatus 12 has been described. However, the present invention is not limited to this, and FIG. As shown in FIG. 5, in the display control process of FIG. 5, instead of the process of step S16, step S91 for setting a scroll period start flag FS indicating the start of the scroll period to “1” is provided, and the determination result of step S9 is displayed. When the completion signal DE is not input, the process proceeds to step S92 to determine whether or not the scroll period start flag FS has been read by the information processing apparatus 12, and the determination result is that the scroll period start flag FS is read. If so, the process proceeds to step S93 to scroll the period After the start flag FS is reset to “0”, the process returns to step S8, and when there is no reading of the scroll period start flag FS, the process similar to FIG. 5 may be performed except that the process directly returns to step S8. . In this case, the information processing apparatus 12 side reads the scroll period start flag FS at a predetermined timing, and when the scroll period start flag FS is read, the display controller 18 side sets the scroll period start flag FS. Since it is reset to “0”, the processing related to the interrupt signal input from the display controller 18 on the information processing apparatus 12 side can be omitted, and the burden of the data display processing can be further reduced. However, since it is possible that the process proceeds to step S14 with FS = "1", the scroll period start flag FS is reset to "0" in step S94 before that.

Furthermore, the processing of FIGS. 6, 16 and 17 is executed at every timer interruption, but is executed only when an interrupt signal indicating the start point of the scroll period SP is input from the display controller 18 to the information processing device 12. It is also possible to implement as a process to do. This can reduce the number of processing times, further reducing the load.
Furthermore, in the above embodiment, the case of performing the scroll display in the lower side has been described. However, the present invention is not limited to this, and in the case of performing the scroll display in the upper side, the logic circuit 17 for the information processing apparatus is used. Thus, when the address is changed from the start address SAL to the end address SAE side in the scroll display data storage area 16S in the dual port memory 16, the scroll display is performed from the row address obtained by subtracting the address corresponding to the step amount ST from the current row address. If the value obtained by subtracting the step amount ST from the current display start address SAS is equal to or larger than the start address SAL of the scroll display data storage area 16S in the display controller 18 in accordance with this, the current display start address SAS is written. The value obtained by subtracting the step amount ST from If the value obtained by subtracting the step amount ST from the current display start address SAS is less than the head address SAL, the new display start address SAS is calculated by the following equation (1). calculate.

SAS = SAE- {ST- (SAS-SAL)} (1)
That is, a value obtained by subtracting the difference between the current display start address SAS and the start address SAL of the scroll display data storage area 16S from the step amount ST and the end address SAE of the scroll display data storage area 16S is newly displayed. Calculate as address SAS.

Then, by writing the calculated display start address SAS into the register 32b of the display logic circuit 19, it is possible to perform an upward scroll display.
In the above embodiment, the case where the information processing device logic circuit 17 is configured by software has been described. However, the display logic circuit 19 can also be configured by hardware in the same manner as the display logic circuit 19. It can also be configured.

Furthermore, although the case where scroll display is performed in the vertical direction has been described in the above embodiment, the present invention is not limited to this, and scroll display can also be performed in the horizontal direction or in the vertical and horizontal directions.
Furthermore, in the above-described embodiment, the case where the liquid crystal display 13 is provided with the upper fixed display region 13U, the scroll display region 13S, and the lower fixed display region 13L has been described. One or both of the fixed display area 13U and the lower fixed display area 13L may be omitted to secure a wide scroll display area 13S.

  Furthermore, in the above-described embodiment, the case where the information processing device 12 is configured to be able to change both the scroll display step amount ST and the scroll period SP has been described. However, the present invention is not limited to this, and the step amount ST Alternatively, only the scroll period SP can be changed, or the step amount ST and the scroll period SP can be fixed to standard values.

    Moreover, in the said embodiment, although the case where the liquid crystal display 13 was applied was demonstrated as a display means, it is not limited to this, Other display apparatuses, such as an organic electroluminescent display, can be applied.

It is a block diagram which shows the image display apparatus of one Embodiment of this invention. It is explanatory drawing which shows the memory content of a dual port memory. It is a block diagram of a display logic circuit. It is a block diagram of a coincidence detection circuit. It is a flowchart which shows the display process of a display controller. It is a flowchart which shows the data display process of information processing apparatus. It is a flowchart of the logic circuit for information processing apparatuses. It is a flowchart of the upper fixed display data writing process of FIG. It is a flowchart of the lower side fixed display data writing process of FIG. It is a flowchart of the scroll display data writing process of FIG. It is explanatory drawing which shows the display state of a liquid crystal display. 3 is a time chart for explaining the operation of an XY driver. It is a time chart used for operation | movement description of a display logic circuit. It is explanatory drawing which shows the scroll state of a liquid crystal display. It is a time chart used for operation | movement description of a display logic circuit. 10 is a flowchart illustrating a modification of data display processing of the information processing apparatus. It is a flowchart which shows the modification of a display controller.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Image display apparatus, 11 Controller driver, 12 Information processing apparatus, 13 Liquid crystal display, 14 Y driver, 15 Oscillator, 16 Dual port memory, 17 Information processing apparatus logic circuit, 18 Display controller, 19 Display logic circuit, 20 X driver, 21 information processing device read / write circuit, 22 information processing device row address decoder, 23 information processing device column address decoder, 24 display address decoder, 25 display power supply, 31a to 31c, 33 address counter, 32a to 32f register, 34a-34c selector, 35a-35d coincidence detection circuit.

Claims (3)

Display means for displaying display data, a controller driver for outputting display data to be displayed on the display means, and an external information processing means for writing the display data to the controller driver,
The controller driver stores display data to be displayed on the display means, and also displays display data storage means set to a display data amount larger than the display data amount of the display means, and display data is written to the display data storage means. The external information processing means and the display data stored in the display data storage means are added to the read start address by a step amount representing the address movement amount of the data storage means in one scroll display set in sequence. Scroll display data reading means for sequentially reading from the new read start address calculated in this way to a read end address corresponding to the display data amount required by the display means and outputting to the display means,
The information processing means designates a write address for the display data storage means with its own management address, and scroll display data writing means for writing the scroll display data before starting to read by the scroll display data reading means And
The control driver has address conversion means for converting the management address of the information processing means to be input into its own management address,
The scroll display data reading means includes a writing start timing notifying means for outputting an interrupt signal indicating a start time of a scroll period to the scroll display data writing means,
The scroll display data writing means determines whether or not priority processing other than display processing exists when an interrupt signal indicating the start time of the scroll period is input from the writing start timing notification means. When the priority processing does not exist, the scroll display data is written, and when the priority processing exists and the scroll display data cannot be written, the elapsed time from the start of the scroll period is completed. An image display device, wherein the scroll display data is written when the time required for the time is exceeded. It said information processing means, having a step amount setting means for setting the step amount in the scroll display, and a step amount notifying means for notifying step amount set in the step amount setting means to the scroll display data read means The image display apparatus according to claim 1. It said information processing means, the scroll display data amount with respect to the display data storage unit, according to claim 1, characterized in that it is configured to set the step amount arbitrarily settable integral n-fold value or 2. The image display device according to 2.

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