JPS61113091A - Image memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to the North American Display Level Standard Protocol C and lower, N
APLPS: North American Pr
esentationProtocol 5yntax
The present invention relates to a device suitable for controlling an image memory in an image communication system such as Videotex or Teletext according to the Japanese Patent Application Publication No.

In particular, the present invention relates to an image memory control device that can efficiently perform incremental point scroll processing in NAPLPS.

[Technical background of the invention]

In NAPLPS videotex and teletext, the image display area on the screen is expressed in x-y coordinates, and when sending image information such as characters and figures, the display area is expressed in x-y coordinates.
It is designed to be indicated by the y-coordinate.

Graphic information is transmitted mainly using graphic description commands (hereinafter referred to as PD).
I: Picture DescriptionIn
(referred to as struetlon) is used. This PD
I can be composed of "commands" that indicate basic graphical elements such as points, straight lines, and arcs in graphical information, and "operands" that indicate the display area (display position and display area size) of graphical information. Almost.

At the receiving terminal, a microprocessor (hereinafter referred to as MPU) decodes the sent PDI and uses a processing algorithm suitable for the decoded figure to calculate the drawing coordinate values x and y of the figure. The operation of loading drawing data into the image memory address corresponding to the coordinate values x and y is repeated.

There is a function called a logical pixel processing function that specifies the display area of graphic information. This logical pixel processing function decomposes basic graphic elements into rectangular pixel blocks (referred to as logical pixels) consisting of a plurality of physical pixels, and specifies the display area of graphic information in units of logical pixels. The designation of the display area of this logical pixel is determined by the characteristic XoyYo (generally, one of the four corners) of a specific physical pixel within the logical pixel.
The coordinates of the physical pixels located at the two corners are used) and the coordinates X,,Y.

It is determined by the width dX in the horizontal direction and the width dY in the vertical direction from the base point. Within this logical pixel, all physical pixels are filled with the same drawing color.

In this case, the coordinates Xo, Y, indicate the display position, and the width dX,
dY indicates the size of the display area.

By the way, among the display processing functions in NAPLPS, there is an incremental point processing function. This incremental 4? The Indian processing function is a type of PDI command used when transmitting natural drawing figures, and data in the format shown in FIG. 11 is sent. In the figure, the field command FC includes data specifying the area in which the next successive incremental point data is to be displayed. Data specifying this display area is allocated in logical pixel units, and data indicating the display position and area size is given to each logical pixel.

Field command FC is followed by incremental point command IPC. The command IPC includes a backing counter PC and a drawing data array. The backing counter PC specifies the delimiter of the drawing data string.

This specifies the number of bits of drawing data for each logical pixel.

Incremental point processing involves dividing the drawing data string into units of the specified number of bits of the backing counter PC, and writing the data into a memory address corresponding to the display area of the corresponding logical pixel. The writing method is such that each time the address corresponding to the horizontal width dX of the logical pixel is updated, one vertical address is updated.

In this case, the horizontal address is always updated from the starting point side. When all addresses within a logical pixel are updated in this manner, writing of drawing color data to that logical pixel is completed. The precondition for the above operation is that the signs of dX and dY of the logical pixel and dX and dY of the field match, but if they do not match, the data is discarded as error data. .

Incremental point processing ends when all of the drawing data fits within the field. However, if the drawing data continues further, the drawing data that has already been written in the field is moved by a height that is the inverse of the sign of the vertical width dY of the logical pixels in the field, and then the previous line is moved again. Following this, it is necessary to process the drawing data. In other words, it is necessary to scroll within the field. Here, if the sign of dY of the logical pixel is positive, it is necessary to scroll down, and if it is negative, it is necessary to scroll up.

[Problems with background technology]

Conventionally, the method of scroll processing for scroll display is to shift the data read address for display in the vertical direction, add this to the image memory, and read the drawing data one line earlier (or later) than the display area. This is generally done in such a way as to obtain . In the case of scrolling the entire image display area, this method can be easily implemented by simply using a presettable counter as the counter that generates the display data read address in the vertical direction. However, when scrolling a partial area, the display data read address in the horizontal direction becomes involved, which complicates the circuit configuration and inevitably increases the circuit scale. Furthermore, since there may be a plurality of partial areas to scroll, it is necessary to prepare a plurality of the same circuits, which is actually very difficult to implement using this method.

Therefore, in general, a partial area is scrolled by vertically shifting the drawing data within the scroll area using the MPU. In this case, the processes performed by the MPU include a process of reading the drawing data from the image memory, and a process of writing the read drawing data into the image memory by changing the vertical address.

However, in NAPLPS, drawing data is generally 1
Since each pixel consists of about 4 bits, in the above scroll processing method, the amount of data handled by the receiving terminal for scroll processing is enormous, and the workload of the MPU increases considerably. . As a result, the receiving terminal's ability to process received data deteriorates, creating the problem of having to either prepare a large-capacity data buffer circuit to store unprocessed data or lower the data transmission rate. It arises.

[Purpose of the invention]

The present invention has been made in order to cope with the above-mentioned circumstances, and an object of the present invention is to provide an image memory control device that can lighten the burden on the MPH for scrolling processing.

[Summary of the invention]

In this invention, for example, each time a memory area of a size corresponding to a scroll area is updated in the horizontal direction, one update is made in the vertical direction.
A data read address and a data write address for scrolling are obtained according to this means, two periods are set in a time-sharing manner for each address update cycle of the means, and the data read address is updated in the previous period. , the data write address is given to the image memory in a later period.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In the following description, the present invention will be described as an image display area configuration using an image with 256 dots in the horizontal direction and 200 dots in the vertical direction, which is the standard configuration of NAPLPS, as shown in FIG. A case where the method is applied to a system having a display area A will be explained as a representative example. In NAPLPS, 1
The number of bits of the drawing data for dots is 4 bits,
16 (2) colors can be selected.

The apparatus shown in FIG. 1 is configured so that scroll processing can be performed not only during an image non-display period such as a vertical blanking period, but also during an image display period.

Furthermore, the apparatus shown in FIG. 1 is configured to be able to write drawing data in logical pixels as described above (hereinafter referred to as logical pixel processing) by using the configuration for executing scroll processing. ing.

Here, the configuration for enabling scroll processing to be executed during the image display tU] is configured as h1? , reveal.

In FIG. 1, it is an 1llIi image memory. This image memory 11 is a two-dimensional memory, and each address corresponds to the X-Y coordinates of each physical pixel on the image display area A shown in FIG.
: Corresponds to 1.

Image memory 11Vi, 4 R, AM 111-114
Consists of. Each RAM 111-114 has a storage capacity of 4×16 bits. In the image display area A, drawing data Dn (0≦n≦255
) is divided into 64 blocks Bm (0≦m≦63) of 4 dots each as shown in Fig. 2, and each block has 4 dots.
The drawing data for each dot is stored in RAM.
It is stored in 111-114. That is, RAM1
This corresponds to nl14rn of the drawing data Dn stored in 11. Similarly, n of the drawing data Dn stored in the RAMs 112 to 114 is 4m+1.4m, respectively.
This corresponds to +2.4m+3. - In other words, the drawing data displayed on the physical pixel whose X coordinate value is expressed by 4K (0≦≦63) is written to the horizontal address Ao-A of K in the RAMJ 11. Similarly, the drawing data displayed at the physical pixels whose X coordinate values are represented by 4, +1.4, +2.4, and +3 are stored in the RAM 112, respectively.
~114, horizontal address Ao'-A is stored at address K.

An image memory 11 in which drawing data is stored as shown in FIG.
In this case, during the display period of the four-dot drawing data of each block Brn, the four-dot drawing data of the next block is read out.

To explain this, in FIG. 1, 12 is a counter that generates a horizontal data read address for display, and 13 is a counter that also generates a vertical data read address.

The counter 12 is an 8-stage up counter and counts the display clock CP. This counter 12 is reset every horizontal scanning period by a pulse XST that is outputted before the horizontal display start timing TH and the display clock, as shown in FIG. As a result, in the image memory 11, the drawing data for four dots of the next block Bn1+1 is addressed in the display period TrrI of each block Bm, although the details will be described later.

The counter 13 is an eight-stage Zorisetta sol down counter. The count value of this counter 13 is preset to °199'' in accordance with the pulse YST (see Figure 2) output at the vertical display start timing, and from then on,
By counting the horizontal synchronization pulses HD, the count is counted down by 11'' for each horizontal line until the count value reaches 0''. The preset value of counter 13 is @1
The reason why it is set to ``99'' is that the X coordinate value of the display start line in NAPLPS is ``199''. Thereby, the output address of the counter 13 and the X coordinate value of the image display area A are made to match.

The output addresses of the counters 12 and 13 are given to the image memory 1 via the data selector 14. in this case,
Counter 13 is given the output of all stages, but counter 1
2, only the outputs of the upper six stages are given. Accordingly, as shown in FIG. 3(h), drawing data for four dots and g of each block Bm is read out from the image memory 11 at one time. The 4 dots (16 bits) of parallel data read out in the manner shown in FIG.
4 is loaded. Then, as shown in FIG. 3(1), these parallel/serial conversion circuits 151 to 154 output serial data with one dot as one unit in accordance with the display clock cp.

Four dots worth of drawing data simultaneously output from the image memory 11 are transferred to parallel/serial conversion circuits 151 to 1541C load/frus LDP (see Fig. 3 (g)).
is output from the NAND circuit 18 shown in FIG. This NAND circuit 18 uses the outputs of the lower two stages of the counter 12 (see FIGS. 3(c) and 3(d)) to obtain a rotary pulse LDP. As a result, the load pulse LDP is not output every four display clocks CP, and its generation timing is as shown in FIG. coincides with the timing of occurrence.

In summary, this example uses 25
64 pieces of drawing data for 6 dots each for 4 consecutive dots
Divide into blocks. Then, during the display period Tn of the drawing data for 4 dots pasted in each block, the next block B
The drawing data for four dots, m+, are read out at one time and prepared for display.

In this way, the drawing data for four dots is stored in the image memory 11.
By reading the image data at once, the period for accessing the image memory 1 for display can be shortened. As a result, during the image display period, it is possible to obtain free time in which the image memory 11 is not accessed for display purposes. In this embodiment, this free time is used to perform scroll processing and logical pixel processing that is executed using the configuration for this scroll processing.

Specifically, as shown in FIG. 3ff), the counter 12
When the second stage output Ql is 1", the data selector 14 selects the data read address RA for display, and
In this case, address AA for scroll processing and logical pixel processing is selected. As a result, data reading for display is performed in the second half of the display period Tm of each block Bm, and scroll processing and logical pixel processing are performed in the first half.

Note that FIG. 3(e) shows the third stage output Q2 of the counter 12, and its inversion interval coincides with the display period Tm of each block Bm.

Address AA for scroll processing is given from counters 34 and 35, details of which will be described later.

Next, the scroll process will be explained, but in order to make the scroll process easier to understand, the logical pixel process executed using the configuration for the scroll process will first be explained.

The drawing data written to the memory address corresponding to the logical pixel is output from the MPU (not shown) (the basic number of bits is 16 bits) onto the data path DB, and is latched into the latch circuit 19 at the timing of the latch pulse Ll. be done. Although the details will be described later, this latch data is provided to three-state buffer circuits 21 to 24 via the data selector 20 during logical pixel processing. These three-state buffer circuits 21 to 24 each have R
Corresponds to AM 111-114. These three-state buffer circuits 21 to 24 have corresponding RAM J
11 to 114 data write permission pulses WEP,
~WEP4 power will be given. The three-state buffer circuits 21 to 24 are normally high impedance, but become low impedance when data write permission is given to the corresponding RAM 111 to 114 (WEP 1% WEP 4), and the latch of the latch circuit 19 becomes low impedance. Provide data to corresponding RAMs 111-114. As a result, drawing data is written into the RAMs 711 to 114 to which the data write permission pulses WEP and P4 are applied.

Here, data write permission pulses WEP 1 to WEP
The generation operation of No. 4 will be explained.

The D flip-flop circuit 25 is always connected to the data input terminal.
w1m+ is input, and a pulse L4 shown in FIG. 4 rb+ is applied to the clock terminal. As shown in FIG. 4(e), the Q output Pl of the D free-lag flow circuit 25 rises at the timing of the rise of the pulse L4. This Q output P1 is applied to the data input terminal of the D flip-flow 21 circuit 26. The clock input terminal of this D flip-flop circuit 26 is connected to the second stage output Q1 of the counter 120.
(see FIG. 4(a)) is passed through an inverter circuit 27 to provide an A pulse P2 (see FIG. 4(d)). Therefore, the Q output P3 of the D flip-flop circuit 26 becomes "1#" at the first rising edge of the ij pulse Pg after the rising of the Q output Pl (see FIG. 4 (e3). When becomes 61#, the AND circuit 28 opens and pulse AT is obtained through pulse P2 (Figure i4 (
f)).

Here, the pulse L4 is a pulse that instructs logical pixel processing, and is a pulse that is not synchronized with the data read timing for display.

The D frizzo flop circuits 25 and 26 are constructed by synchronizing /1,000 rus L4 with the second stage output Q1 of the counter 12.
It serves to synchronize the start timing of logical pixel processing with the data read timing.

During logical pixel processing, details will be described later, but the AND circuit 29 uses an r-t, and the pulse AT passes through the AND circuit 29 and directly becomes the pulse WT (see FIG. 4(J)). This pulse WT becomes a generation reference for a data write pulse WP and a data write address in logical pixel processing. This pulse WT is applied to an AND circuit 30. D Furia Zoflo 21 circuit 31 is display clock CP
is inverted by the inverter circuit 32, and the first stage output Q of the counter 12 is obtained.

is delayed by half a clock of the display clock CP and is applied to the AND circuit 30. Therefore, from the AND circuit 30, as shown in FIG. can get.

This data write pulse wp is applied to a counter 59 that generates a horizontal data write address, the details of which will be described later.
According to the outputs of the lower two stages, the data decoder 33 distributes the data write permission pulses WEP 1 to P2, and selectively supplies them to the RAMs 111 to 114.

Here, the pulse WT is an inversion of the second stage output Qt of the counter 12, as is clear from FIGS. 4(a) and 4(j). Therefore, data write pulses W that are obtained in synchronization with this pulse WT and the same number as this /f pulse WT are obtained.
Only one drawing data is written by P during the display period Tm of each block Bm. Moreover, the writing is performed when the data selector 14 selects the address AA on the counter 34, 35 side.

Here, generation of a data write address will be explained.

In FIG. 1, 34 is a counter that generates a data write address in the horizontal direction during logical pixel processing;
is a counter that generates a vertical data write address. These counters 34 and 35 are 8-stage Brisetta pullazzo down counters. These data write addresses output from the counters 34 and 35 are as shown in FIG. The data is applied to the image memory 11 via the data selector 14.

In this case, only the outputs of the upper six stages of the counter 34 are given to the image memory 1, and the outputs of the lower two stages are given to the data decoder 34 as described above, and the data write pulse WP is sent to the data write pulse WP. permission pulse WEP,
~WEP, is used for sorting. Further, the output of the counter 35 is sent to a data selector 59, the details of which will be described later.
and is applied to the image memory 11 via the adder 58, but during logical pixel processing, this data selector 59
The adder 58 passes the output of the counter 35 as is.

Here, the update form of the data write address generated from the counters 34 and 35 will be explained.

Now, consider a logical pixel S as shown in FIG.

This logical pixel S has coordinate values xo, y of its lower left corner
, is a logical pixel that is given as data indicating the display position. When the data indicating the display position is selected in this way, the logical pixel S is located in the fourth quadrant on the x-y coordinates with the coordinate value XQ * Y6 as the origin, and its horizontal width dX and vertical width are The width dY in the direction shows a positive value.

In FIG. 5, the arrow shown in the logical pixel S indicates the direction in which the data write address is updated. As shown in the figure, the data write address starts from the coordinate value X6 a Y6, updates the address corresponding to the width dX in the horizontal direction once, and then updates the address in the vertical direction by one, which is repeated.

In this case, at the vertical address update point, the horizontal address starts updating from the last address in the previous address update period. the result,
The data write address is updated in parallel in the horizontal direction and in a zigzag pattern in the vertical direction. In this case, the counter 34 initially performs an up operation, and thereafter switches between an up operation and a down operation each time the address corresponding to the horizontal width dX is updated once. Further, the counter 35 always performs an up operation.

Here, control of the counters 34 and 35 to obtain the address update form as described above will be explained.

The MPU outputs data indicating the coordinate values X, lY, to the data bus DB. Of these, data indicating the X coordinate f orthogonal Xo is loaded into the counter 34, and data indicating the Y coordinate value Yo is loaded into the counter 35 using the pulse L4 as a load pulse. In addition, the horizontal width dX and code PX1 of the logic pixel S in the MPU Ii and the vertical width dY and code PY
The data indicating this is output onto the data bus DB. In this case, the data indicating the width is actually data of dX-1, dY-1. Below, these dX-1, dY-1 are dx+d'
It is written as 1. These (PX, dx), (PY, d
y) are pulses L3.y), respectively. It is latched by the latch circuits 36 and 37 at the timing of L. here,
The data (PX, dx) and (PY, dy) are composed of 9 bits, and the lower 8 bits contain dx, d
Data indicating y is set, and the most significant bit is a code P.
Data indicating X and PY is set. Here, as described above, the code indicates in which quadrant of the first to fourth quadrants the logical pixel S is located in the X-Y coordinate system whose origin is the coordinate value indicating its display position. In the example of FIG. 5, since the logical pixel S is in the first quadrant, dX and dY are positive. Therefore, data indicating a positive sign is set in the sign bits of latch circuits 36 and 37. In the circuit shown in FIG. 1, 0'' is used as data indicating a positive sign, and ``1'' is used as data indicating a negative sign.

Data indicating the position of the display area of the logic pixel S is now set in the counters 34 and 35, and the latch circuit 36.
37, data indicating the size of the display area of the logical pixel S (including the code) is set.

Note that (PX) for latch circuits 36 and 31.

The data sets such as dx), cpy, and dy) and the drawing data for the latch circuit 19 are set by PD■
It is not necessary to perform this while displaying the figure, but it may be performed when the PDI of the logical pixel is received. In this way, counter 3
4. When the coordinate values xo and yo are set in 35, the data write address is automatically updated, and the drawing data is written according to this address, so M
The PU can immediately start decoding the PDI of the newly sent logic pixel.

When the counter 34 is set to the coordinate fit Y o,
Using the pulse WT (see Figure 4) which is the reference for generation of the data write pulse WP and updating of the data write address AA as a counting clock, as shown in Figure 5 above, the address for the width in the horizontal direction is It moves up and down and is updated repeatedly.

For this up-down operation, the pulse WT is sent to the up terminal UC of the counter 34 by the data decoder 38.
K and down terminal DCK. This distribution control is performed as follows. data decoder 38
In this case, the data of the sign bit Q8 of the latch circuit 36 is 'o#
In this case, the pulse WT is applied to the up terminal UCK of the counter 34 at the start of address updating.

As a result, the output of the counter 34 changes from X to 1 at the falling timing of the pulse WT, as shown in FIG.
I will upload it one by one. Note that FIG. 4 shows a representative case where dX=3.

The pulse WT is also given to a counter 39. This counter 39 is an 8-stage up counter that uses 9 pulses WT as a counting clock. And Fig. 4(b)
After being reset by the pulse L4 shown in FIG. do.

When the count output of the counter 39 matches the data of the lower 8 bits of the latch circuit 36, the coincidence detection circuit 42 outputs a coincidence pulse P4 shown in FIG. The pulse P5 shown in FIG.
(See FIG. 4 (r3)) is obtained. Pulse P7 is obtained by passing this pulse P6 and pulse P5 through the inverter circuit 45.
(See FIG. 4(II)) through the NAND circuit 46, a pulse P8 shown in FIG. 4(1) is obtained. When this pulse P8 falls, the counter 39
Since is reset, the coincidence pulse P4 also falls.

Pulse P8 is applied to counter 47. This counter 47 is an eight-stage counter that uses pulse P8 as a counting clock.

After the counter 47 is reset in the same way as the counter 47 by the pulse L4 passed through the inverter circuit 40 and the OR circuit 48, it counts up by one at the timing of the fall of the pulse P8.

The data of the least significant bit of the counter 47 operating in this manner is used together with the data of the sign bit of the latch circuit 36 to control the data decoder 38 to distribute the pulse WT to the up terminal UCK and the down terminal DCK of the counter 34. used for. That is, the data of the least significant bit of the counter 47 and the data of the sign bit of the latch circuit 36 are provided to the exclusive OR circuit 49. At the beginning of the address update, the output of the least significant bit of the counter 47 is '0'.The output of the exclusive OR circuit 49 is determined by the data of the sign bit of the child circuit 36. In this case, the data of this sign bit is 10#, so the exclusive OR circuit 4
The output of 9 is 0#. The data decoder 38 outputs a pulse W when the output of the exclusive OR circuit 49 is 10".
T is applied to the up terminal UCK of the counter 34. When the counter 34 updates the address for 1idX in the horizontal direction and a pulse P8 is obtained from the NAND circuit 46, the counter 4
The output of the least significant bit of No. 7 switches from "0#" to "1". Accordingly, the output of the exclusive OR circuit 49 is also switched from "0#" to "1#".The data decoder 38
When the output of the exclusive OR circuit 49 is 11#, the pulse WT is applied to the down terminal DCK of the counter 34. Accordingly, the counter 34 now performs a down operation.

Thereafter, each time the pulse P8 is output from the NAND circuit 46, the output of the least significant bit of the counter 47 is inverted, so the output of the exclusive OR circuit 49 is inverted, and the counting direction of the counter 34 is switched.

Note that, as mentioned in the explanation of FIG. 5 above, the address of the counter 34 is updated from the last address before the change after the color direction is turned off and incremented by 1. This is done as follows.

That is, the coincidence signal P4 output from the coincidence detection circuit 42 is inverted by the inverter circuit 50, and the coincidence signal P4 output from the coincidence detection circuit 42 is inverted by the inverter circuit 50,
Close dart 1. As a result, at a switching point in the counting direction of the counter 34, the supply of the pulse WT to the counter 34 is blocked, and change in the output of the counter 34 is prohibited. Accordingly, each time the counter 34 updates the address corresponding to the horizontal width dX once, it starts the next update from the last address. The input state of the pulse WT to the up terminal UCK of the counter 34 is shown in FIG.
Furthermore, the input state for the down terminal DCK is shown in FIG. 4(v).

Next, control of the counter 35 will be explained.

Every time the counter 34 updates the address corresponding to the horizontal width dX once, the /mother pulse P8 outputted from the NAND circuit 46 is sent to the up terminal UCK and down terminal DC of the counter 35 by the data decoder 52.
Allocated to K. That is, when the sign bit Qs latched in the latch circuit 37 is 10'' data, the data decoder 52 applies a pulse P@ to the up terminal UCK of the counter 35, causing the counter 35 to operate up. When the code (pi) Qs is '1' data, a pulse P8 is applied to the down terminal DCK of the counter 35, causing the counter 35 to operate down.

In this case, since the sign bit of the child circuit 37 is "0#," the counter 35 is "Y" as shown in FIG.
Count up one by one.

In addition, in FIG. 4, dY=3 is shown as a representative.

Here, the operation to obtain the end timing of logical pixel processing will be explained.

As mentioned above, the counter 47 is set to /'? As shown in Fig. 4 (0), the falling edge of P8 is at the timing of 6.
In this operation, when the count output of the counter 47 matches the lower 8 bits of the latch data of the latch circuit 37, the match detection circuit 53 increments the count by 1 from "0". As shown, the AND circuit 54 outputs the logical product of this pulse P and the pulse P5 output from the AND circuit 43, and outputs the pulse P1o (FIG. 4(x)). ) are obtained.D flipflop circuit 55, inverter circuit 56
, the NAND circuit 57 is the previous D flip floor 1 circuit 44
, the inverter circuit 45, and the NAND circuit 46 generate the pulse P5.
In the same way as obtaining the pulse P8 which falls at the same timing as the falling edge of the pulse P6 from the display clock CP and the display clock CP, the pulse P8 is obtained using the pulse PIG and the display clock CP.
The pulse Pta falls at the falling timing of 16 and has a pulse width of half a clock of the display clock CP.
(See Figure 4 (zz)). Output pulse ptt+p1 of D flipflop circuit 55 and inverter circuit 56
g are shown in FIG. 4(y) #(zt), respectively.

At the falling edge of the pulse pxs, the D flip flop circuits 25 and 26 and the counters 39 and 47 are reset. This stops the generation of pulse AT.

As a result, the Noculus WT is no longer output, the generation of the data write pulse wp and the update of the data write address are stopped, and the data write is completed.

Pulse P5 is a Noculus pulse that is output when all the addresses in the horizontal direction are updated, and pulse P is a pulse that is output when all the addresses in the vertical direction are updated. Therefore, take the AND of this pulse P51P),
The fact that the pulse P13 indicating the data write end timing is obtained from this AND output means that the data write operation is ended when all the addresses of the logical pixels S have been updated.

Next, scroll processing, which is a feature of this invention, will be explained.

Note that in the following description, scrolling processing for obtaining vertical downscrolling will be described as a representative example.

The scrolling process in this embodiment is roughly divided into a process of reading out drawing data from the image memory 1 and a process of putting the read data into the image memory 11. Unfortunately, the scrolling process in this embodiment is performed by shifting the drawing data.

First, the scroll area is located at the bottom left corner, which is the same as the display area of the logical pixel S above. 45 marks X,,Yo
Consider an area whose display position is indicated by .

In this case, the address update operation of the counters 34 and 35 and the data write pulse generation operation are shown in FIG.
- As shown in (zz), it is the same as that in the previous logical pixel processing (Fig. 6 (a) to (zz) have the same content as the previous Fig. signal)
. However, in this case, the reference pulse WT, which is the reference for the generation of the data write pulse WP and the address updating operation of the counters 34 and 35, is one half of the logic pixel processing, as shown in FIG. 6(j). occurs with a frequency of . in this case,
As the pulse WT, an even-numbered pulse in the /IP pulse train of the pulse AT is selected. The address update operation of the counters 34 and 35 is different from the logical pixel processing.
The data y is not dY-1 but dY-2. Accordingly, among the vertical addresses, the address of the highest line, -tb, 1s(X
o + dX-1) is not specified.

No J? The frequency of occurrence of ruth WT is 2 times that during logical pixel processing.
Since the output address of the counters 34 and 35 is set to 1/2, the output addresses of the counters 34 and 35 are updated once during the display period of two blocks Bn. Therefore, while the counters 34 and 35 continue to output the same address, the data selector 14 outputs the address AA given from the counters 34 and 35 by 2.
You will have to choose twice.

Here, while the counters 34 and 35 continue to output the same address, the data selector 14 outputs the same address as the counters 35 and 36.
The reason why the output address of is selected twice will be explained. That is, as mentioned above, the scrolling process of this embodiment is a process of reading data from a certain address in the image memory 1 according to the scroll mode (scrolling down or up in one vertical direction, scrolling right or left in the horizontal direction). , and writing the read data to a predetermined address. In order to execute these two processes, it is necessary to create a data read address and a data write address. In this embodiment, these two addresses are created based on the output addresses of counters 34 and 35. Therefore, counter 34. The address update interval of '35 is set twice as long as that of logical pixel processing, so that the data selector 14 can select the address AA on the counters 34 and 35 twice in each address update cycle. In each address update cycle, when the data selector 14 first selects the address AA on the counter 34, 35 side, the counter 34,
A data read address is created from the output address of counter 35, and when selected, a data write address is created from the output address of counters 34 and 35, and is given to the image memory 1 through the data selector 14. That's why.

We are now considering the case where the output addresses of counters 34 and 35 are updated from the lowest line of the scroll area as shown in Figure 5 above, and we are also considering processing for downward scrolling in the vertical direction. , the output addresses of the counters 34 and 35 can be used as they are as data write addresses. On the other hand, as the data read address, the output address of the counter 34 can be used as is as the data read address in the horizontal direction.
As a data read address in the vertical direction, it is necessary to increase the output address of the counter 35 by one line.

Counter 35 when reading data and writing data
The adder 58 and the addition number generation circuit 59 convert the output address of the address and create two addresses.

The adder 58 uses the output address of the counter 35 as an addition number, and adds the output of the addition number generation circuit 59 to this number. The addition number generation circuit 59 uses LS when reading data.
It outputs 8-bit data in which only B is "1", and when writing data, it outputs 8-bit data of all 10#s. Therefore, when reading data, the counter 35
11# is added to the output address of image memory 11.
address on one line. On the other hand, when writing data, the output address of the counter 35 is given to the image memory 11 as is.

As a result, the drawing data is shifted down by one line in the image memory 11 in preparation for down-scroll display.

Here, data read processing and data write processing in the scroll processing will be explained in more detail with reference to FIG.

First, the operation of generating pulses WT at half the frequency of logical pixel processing will be described. Data for identifying the scroll processing mode and the logical image-3 tot processing mode is set in the latch circuit 60. This mode identification data is outputted to the data bus DB by the MPU and latched by the latch circuit 60 at the timing of the pulse L5.

This mode identification data is 2-bit data, and its identification contents are as shown in the table below.

In other words, when the 1st bit Qo is 10'' data, 2
Indicates the logical pixel processing mode regardless of the data of bit Ql. On the other hand, when the first bit Qo is "1" data, the second bit Q! When is 0” data, it indicates the scroll processing mode for down scroll display, and 2
When the Q breath of the pit is "1# data," it indicates a scroll processing mode for up scrolling.

Since we are now considering scroll processing for down-scroll display, the 1st bit Qo is '1' as shown in Figure 6 (1). Therefore, this 1st bit Qo
The output of the NAND circuit 61 to which data is given is determined by the Q output of the D flip-flop circuit 62. D
The Frizzo flop circuit 62 uses Tsutomu Ishikawa as its data input, and uses the pulse P14 (see FIG. 6 (g)) obtained by inverting the pulse AT in the inverter circuit 63 as its clock input, so its Q output is determined by the falling edge of the pulse AT. It is repeatedly reversed at the same timing. This Q output is inverted by the NAND circuit 61 and becomes a pulse pts as shown in FIG. 6(h), which controls the opening and closing of P-) of the AND circuit 29. Therefore, in the pulse train of the zf pulse AT, the odd numbered pulses are removed by the AND circuit 29, and only the even numbered pulse t4' is outputted as the pulse WT.

On the other hand, in the logical pixel processing mode, the first bit Qo of the mode identification data is always 0 as shown in FIG. 4 (1).
Therefore, the output of the NAND circuit 6 is always 1#. Therefore, as the pulse WT, the pulse AT can be obtained as is.

Next, the addition number generation operation of the addition number generation circuit 59 will be explained. Now, since the first bit Qo of the mode identification data is 11#, this first bit data, the Q output of the D flip-flop circuit 62 (a pulse obtained by inverting the pulse pts shown in rh in FIG. 6), and the pulse AT The output of the AND circuit 64 to which A? Only odd-numbered pulses in the pulse train are output as pulses Pig, as shown in FIG. 6 (I3). This no J? The pulse P16 is given to the addition number generation circuit 59 as a B input. The A input of the addition number generating circuit 59 is supplied with the data of the second bit Q1 of the mode identification data. The addition number generating circuit 59 is a circuit whose output of 8 bits Oo to 07 is determined according to its A and B inputs, and its output is expressed by the following logical formula.

4l-0o =B101~07-A-B As is clear from this logical expression, the least significant bit of the output of the addition number generation circuit 59 is not "1" during the pulse P16 period, and is I□I+ during other periods. becomes.

Further, the upper 7 bits are always "0" because the second bit data of the mode identification data for person A is 10. Therefore, the addition number output from the addition number generation circuit 59 is the same as the pulse P16. The period is "OOOOOO001" and all other periods are "0#". the result,
As shown in FIG. 6 (I4), the output address of the adder 58 is the address obtained by adding "1#" to the output address of the counter 35 only during the pulse Pig period, and the output address of the counter 35 during other periods. It becomes the address.

As is clear from the comparison with FIG. 6 (2,), the period of P16 is the same as that of the data selector 1 in each address update period of the counters 34 and 35 (the update point is indicated by P).
4 selects the address AA on the counters 34 and 35 during two periods II.

It corresponds to the previous period Il of I2. Therefore, from the data selector 14, (zs), (zy) in FIG.
■Period as shown! Then, among the output addresses of the counters 34 and 35, the address obtained by incrementing the output address of the counter 35 by one line is output, and in period 2, the output addresses of the counters 34 and 35 are output as they are.

Then, the drawing data is read out from the image memory 11 using the selected address MA of the data selector 14 in period (1) as the data readout address, and the drawing data is read out from the image memory 11 using the selected address MA of the data selector 14 in period (2) as the r-Yuso writing address. The drawn drawing data is written into the image memory 1. That is, during the period 1, since the pulse WT is not generated, the data write pulse WP is also not generated.

Therefore, data write permission pulses WEP 1 to W
EP does not occur either. As a result, the image memory 1 enters the read mode. With this, image memory 11-4
The output data of the two RAMs 111-114 is input one bit at a time to data selectors 65-68 starting from the least significant bit. The data selectors 65 to 68 select the drawing data corresponding to the horizontal address of the data read address from among the input data according to the output of the lower two bits of the counter 34. This selection data is latched into the latch circuit 69 at the falling edge of the second stage output of the counter 12 which switches the selection address MA in the data selector 14.

The drawing data latched by the latch circuit 69 in this manner is provided to the three-state buffer circuits 21 to 24 via the data selector 20 during period (2) 8, and is written into the image memory 11. That is, in this period I2, since the pulse WT is generated, the data write pulse WP is generated. With this, either one of the lower two bits of the counter 34 is output from the data decoder 33.
Two data write permission pulses are output, and the drawing data is written to the RAM to which this data write permission pulse is applied.
K is written.

The data selector 20 selects the latch data of the latch circuit 69 in the scroll processing mode, and selects the latch data of the latch circuit 19 in the logical pixel processing mode, and this is controlled as follows. Ru. The AND circuit 70 outputs the first bit data of the mode identification data and the Q output of the D flip-flop circuit 62.
)/" and pulse AT f-). If it is in the scroll processing mode, the first bit of the mode identification data is 1", so the AND circuit 70 outputs one of the pulse AT pulses. Even number 7 (Rusga)
jruspty (see Figure 6 (Zll)). Conversely, in the logical pixel processing mode, the first bit of the mode identification data is @0#, so the output of the AND circuit 70 is '0'.The output of the AND circuit 70 is the control terminal of the data selector 20. When the control input of the data selector 20 is '1#, the latch circuit 69
When the latch data is "0", the latch circuit 19
Select latch data. The pulse P17 corresponds to the pulse WT in the scroll processing mode, and this corresponds to the period ■
2, the latch data of the latch circuit 69 is selected by the data selector 2o and written into the image memory 11 only during the period I in the scroll processing mode.

Since the pulse pty matches the pulse WT, it is conceivable that the /f pulse PIT can also be used as the pulse WT.
/Circe P17 is a necessary pulse only in the scroll processing mode, whereas the pulse WT also occurs in the logical pixel processing mode.

Therefore, in this embodiment, the pulse pulse P17 is generated through a route different from that of the pulse WT.

FIG. 7 shows the above-mentioned scrolling process on the scroll display area. In the figure, a solid arrow W indicates an update of the data write address, and a solid arrow R indicates an update of the data read address. Both are shown with a difference on the time axis. Further, vertical arrows such as those shown by broken line arrows indicate shifts in drawing data.

In this way, by shifting the drawing data by one line, the scrolling process for cedar run scroll display ends, but if more drawing color data continues in the scrolling process in incremental point processing, the shift operation ends. After that, this data is processed by MPU (
Xo, Yo+2) ~(Xo+2, Yo
+2).

Note that when performing scroll processing for up-scroll display, the scroll display area may be set in the fourth quadrant, as shown in FIG. In this case, the sign bit of the latch circuit 37 that latches the data indicating the vertical width dX is set to 1'' indicating a negative sign.
In the latch circuit 60, mode identification data of Qo """ 1, Q1=1 is set.Furthermore, the addition number generation circuit 59 is set to all "1' data,
In other words, -1 data is generated, and all other periods are
It is sufficient to generate data of 0#. As a result, in period I, 11# is subtracted from the output address of the counter 35, and for the data write address,
A data read address one line below can be obtained.

As described in detail above, according to this embodiment, the process performed by the MPU in the scroll process is performed by using the counters 34 and 35.
The following three processes are performed: setting data indicating the start point of address update in the latch circuits 36 and 37, data indicating the scroll area size in the latch circuits 36 and 37, and setting data indicating the scroll mode in the latch circuit 60. All that is required is processing, and data shifting for scrolling display is then performed automatically, so the burden on the MPU can be significantly reduced.

Note that the present invention is not limited to the above embodiments. This will be explained below using scroll processing for down-scroll display as a representative example.

First, the starting point for updating the address is the coordinate value x, y of the display position.
For example, in the example of FIG. 7, the starting point is the coordinate value Xo.

It may be set to Yo+1. In this case, the addition number generating circuit 59 may generate all "0" data in the period Il, and generate all "1#" data in the period (2). , the output address of the counter 35 is outputted as ``!!'', and in period ■2, this output address is decremented by 1 and outputted.The address update form in this case is as shown in FIG. In this case, if the addition number generation circuit 59 is configured to output all '1' data when its B input is high level 4, pulse WT should be used as the B input. , and the pulse P16 becomes unnecessary.

Further, the address update form is not limited to updating in a zigzag pattern, but may be updating in parallel in a single direction. In this case, the repeated address update direction can be either horizontal or vertical.

FIG. 9 shows a representative case of repeated updating in the vertical direction. In this case, each time the counter 35 updates the vertical address once, the counter 35 may be set to "Yo" and the count value of the counter 34 may be incremented by one.

Further, the present invention is applicable not only to vertical scroll display but also to horizontal scroll display. FIG. 10 shows a representative case of left scrolling in the horizontal direction. In this case, the case where the address update form is zigzag is shown, but this is because the counters 34 and 3 in the address update are
5 may be reversed from that shown in FIG. Further, in this case, the adder 58 and the addition number generation circuit 59 may be provided on the color/receiver 34 side.

Furthermore, the present invention is of course applicable not only to scrolling by one line or one dot, but also to scrolling by multiple lines or multiple dots.

Also, if the counters 35 and 34 are not to update the address of the scroll area, but to update the address of a memory area of a size corresponding to this area, the address of a memory area other than the scroll area should be updated. You can do it like this. Even if you do this, the vertical at 1/
If only the scroll area is to update the address of an area different from the scroll area, it is necessary to add or subtract a predetermined value to the output address of the counter 35, or if the horizontal and vertical addresses are to update the address of an area different from the scroll area. For example, a data read address and a data write address can be obtained by adding or subtracting a predetermined value to the output address of the counters 34 and 35.

It goes without saying that various other modifications can be made without departing from the gist of the invention.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an image memory control device that can reduce the burden on the MPH for scroll processing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure shows an image display area configuration, etc. 58 of one embodiment... an adder,
59... Addition number generation circuit. FIG. 3 is a timing chart for explaining the display data read operation of one embodiment. FIG. 4 is a timing chart for explaining logical pixel processing of one embodiment. FIG. 5 is a timing chart for explaining the logical pixel processing of one embodiment. 6 is a timing chart for explaining the scrolling process of one embodiment, and FIG. 7 is a diagram showing the scrolling process of one embodiment on the scroll area. , 8th
10 are diagrams for explaining different embodiments of the present invention, and FIG. 11 is a diagram for explaining incremental point processing. 11... Image memory, 12, 13, 34, 35° 39
．． 47...Counter, 14,20.65-68...
Data selector, 151 to 154...Parallel/serial conversion circuit, 19, J6, 3.7, 60...Latch circuit, 21 to 24...Three speed pad, fa circuit, 25, 26, 31, 44, 55.62...D flip frozzo circuit, 33.38.52...Data decoder, 42.53...-match detection circuit, =52- Applicant's agent Patent attorney Takehiko Suzue No. 70
8th r-! 90th 10th r! Key B etc. inner axis--side ~ No. 111iZ1 Figure-]]]]yo I pc so-called ■]] lower "1

Claims (1)

[Scope of Claims] An image memory in which drawing data is accessed by horizontal and vertical addresses corresponding to horizontal and vertical coordinates of an image display area; An address generating means for generating an address and a vertical address, and an address for controlling the address output from this address generating means according to the scroll mode, and also for controlling the address of a memory area of a size corresponding to the scroll area. an address control means for controlling one update in the vertical direction (or horizontal direction) every time one update is made in the horizontal direction (or vertical direction); A scrolling address output means capable of outputting a data read address and a data write address for scrolling according to the output address, and two periods, a first and a second period, are set in a time-sharing manner in each address update period of the address generation means. , address switching means for causing the scrolling address outputting means to give the data read address to the image memory in a first period and giving a data write address in a second period; 1. An image memory control device comprising: data transfer means for writing drawing data read from the image memory according to a data read address given from the image memory into the image memory according to the data write address.