JPS5935476B2 - Hard copy device in multi-terminal display control device - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a cathode ray tube display device, a keyboard, a tablet,
The present invention relates to a hard copy device in a display control device including a plurality of input/output terminal devices, such as a hard copy device.

[Background and purpose of the invention] In the field of newspaper typesetting and general printing, in order to speedily perform text correction, proofreading, and various editing processes,
Recently, as shown in Figure 1, electronic computers and cathode ray tube display devices (
Typesetting processing systems including CRTs (hereinafter simply referred to as CRTs) have come into use.

In such a system, various articles and texts are temporarily stored in the storage device of an electronic computer (hereinafter simply referred to as CPU), displayed on a CRT terminal 1 for monitoring, and further stored on a keyboard input device 2 and a tablet input device. From 3rd class onwards, article corrections, proofreading, typesetting format specification, etc. can be specified by specifying changes, etc. and processing these commands with the CPU.
Various editing processes can be performed quickly and easily. However, when using such a system, it is common to use a plurality of input/output terminals, and these terminals are often installed at locations separated from each other.

However, in the case of Japanese text, the character generation unit that generates characters to be displayed on a CRT terminal has to handle a large number of characters, requires a large storage capacity, and is very expensive. Therefore, each CRT
It is not advisable to provide the terminal with a character generating section from the point of view of cost, and it is more convenient to control a plurality of CRT terminals with a display control device that includes one character generating section. Also, in this way, one CPU can handle multiple CPUs.
When controlling RT terminals, data transfer between each terminal and the CPU is time-sharing processing using interrupts, so it is difficult to transfer characters from the CPU to each CRT terminal in program processing. This results in wasted time. To prevent this, a character data buffer memory is prepared that can receive and temporarily store several character data (display character code, display position address, etc.) from the CPU for each CRT terminal. , and if this character data buffer memory, character generator, and refresh memory corresponding to each CRT are housed together in a display control device, C
Display character data can be transferred from the PU to each CRT terminal at once, which improves the effective speed of data transfer.Furthermore, the transfer speed of pixel data between the character generator and the refresh memory is increased, and the cost required for transfer is also reduced. Can be lowered. Furthermore, by accommodating the refresh memories of each CRT terminal in the same housing, the control elements of each refresh memory that can be shared can be shared by one control means, which helps reduce system costs. . In addition, the signal lines from each refresh memory to the corresponding CRT terminal are three for a video signal, horizontal and vertical synchronizing signals, two for a video signal and a mixed synchronizing signal, or just one mixed video signal. This also makes it easier to install a CRT terminal at a location several hundred meters away. In addition, if the system is configured with one character generator like this, each CR
Even if a T terminal issues a pixel data transfer request, it cannot immediately receive the data transfer; it must wait until the display control device allocates the character generation area to a predetermined CRT terminal; As described in detail in Japanese Patent Application No. 52-13718 previously filed by the present applicant, if it is configured with a random access memory and a shift note register, even if pixel data is transferred, it will not be possible to use it as is. It cannot be written to memory.

That is, the refresh memory disclosed in Japanese Patent Application No. 52-13718 is composed of a random access memory having a capacity for a CRT1 screen, and a shift register that is shifted in synchronization with the scanning lines of the CRT.

Pixel data to be displayed is read out from the random access memory to the shift register and displayed, and pixel data is also written to the random access memory via the shift register. Therefore, when writing pixel data to this refresh memory, it must be done in synchronization with the timing of writing data into the refresh memory, that is, with the timing with which data is written into the shift register. Therefore, a pixel data buffer memory is required to store the pixel data, but the time from when the terminal issues a pixel data transfer request until the data is sent, and the sent data can be stored in the refresh memory. Considering the time required to write to the CRT, if there is only one pixel data buffer memory, only one character can be written in one field time of the CRT, and displaying takes a very long time.

Therefore, it is preferable to prepare two pixel data buffer memories. On the other hand, the CRT display screen is 900 x 80
The above-mentioned patent application 1972
When a refresh memory such as that shown in No. 13718 is used, the shift register constituting the refresh memory must be operated at a frequency of 30 MHz or higher.

However, such a high-speed shift register is expensive and consumes a large amount of power, which inevitably increases the price of the entire system. Therefore, this problem can be solved by configuring the shift register with a plurality of relatively low-speed shift registers and composing the outputs of each shift register with a high-speed video composition circuit. However, in this case, depending on the writing position of the character, the pixel data sent from the character generation section cannot be sent as is to the shift register, and it is necessary to rearrange the pixel data in a form that is compatible with writing to the polyphase shift register. Yes.
Text displayed on a CRT and subjected to various editing operations is designed to be able to be directly applied to various typesetters, but there are also cases where it is desired to output the text as a document for proofreading or the like.

However, in such a system, it is not necessary to have one hard copy device for each CRT terminal; one hard copy device for every several CRT terminals is sufficient. In this case, it is preferable that the hard copy device is capable of outputting the image displayed on any CRT as it is, as well as being capable of outputting data directly sent from the CPU via the display control device. A first object of the present invention is to provide a low-cost, high-speed multi-terminal display control device that can drive multiple CRT terminals and hard copy devices with a single character generator.

A second object of the present invention is to accommodate the refresh memory of a CRT terminal, the image memory of a hard copy device, and other circuits in a single display control device, in order to provide a high-speed data processing and low-cost device. It is an object of the present invention to provide a device that speeds up data transfer time and allows only one control circuit to be shared among the terminals.

A third object of the present invention is to provide a device that can easily output as hard copies both images displayed on a plurality of CRT terminals and articles sent from a CPU through a display control device. be.

A fourth object of the present invention is to use a CRT terminal or a hard copy terminal as a display control device? It is an object of the present invention to provide a device that is driven by the same synchronization signal sent from both devices and can transmit and receive data between them at exactly the same timing.

In order to achieve such an object, the present invention is a multi-terminal display control device equipped with a plurality of input/output terminal devices such as a CRT and an input device. A sending CPU, a character data buffer memory that is provided corresponding to each CRT and stores a plurality of character data sent from the CPU, and character pixels according to character codes sent from the character data buffer memory. a single character generation section that generates data; a refresh memory control section that writes character pixel data sent from the character generation section into a refresh memory provided corresponding to each of the CRTs and displays the data on the CRT; , instructs to transfer the video data of a designated refresh memory among the refresh memories of the CRT to the image memory, or to assemble various data generated in accordance with instructions from the CPU as image data in the image memory. The present invention is characterized in that it includes an image memory control section, and a single hard copy device that outputs the video data and image data stored in the image memory.

[Display control device]

In order to achieve the object of the present invention, the display control device has a single character generator, a character data buffer memory capable of storing character data of several crosses corresponding to each CRT terminal and hard copy device, and two characters. It is composed of a refresh memory control section having a pixel data buffer memory capable of storing pixel data for 10 minutes, and a refresh memory having a storage capacity for one screen of a CRT.

The video data signal from each refresh memory consists of three lines: a video data signal line, a vertical synchronization signal line, and a horizontal synchronization signal line.
Alternatively, a mixed signal of these signals is sent to each CRT terminal or hard copy device through two or one signal line.
Specify display characters and edit processing commands as shown in Figure 1.
The information is sent to the display control device by a keyboard device 2 or tablet device 3 attached to or independent of the T terminal 1. In FIG. 2, 10 is a CPU connected to the outside of the display control device;
11 is the data line from CPUIO, 12 is CPUIO
A character data buffer memory that can store several cross characters of character data (character code, display position address data) sent from O; 13 is a character data buffer control unit that controls writing and reading of data in the character data buffer memory 12; , 14 is a transfer line for display position address data among the character data stored in the character data buffer memory 12, and 15 is an address data transfer line that converts the parallel data sent through the address data line 14 into serial data and transfers the data. 16 is a transfer line that transfers the character code to the character generation section 17, 17 is a character code transfer line 16
18 is a character generation unit having a readout control unit etc. that controls reading out character pixel data for one character specified by the character code sent by the character code; 18 is a data compression unit for character pixel data read out from the character generation unit 17; This is not necessary if the character pixel data in the character generation area is not compressed in the character pixel decoder that restores the data from the original state.

19 is a character pixel data line for transferring the character pixel data restored by the character pixel decoder 18, 20 is an address data line, and 21 is a synchronization signal generator for generating reference signals such as a vertical synchronization signal and a horizontal synchronization signal. Part, 2
2 is a synchronous signal transfer line, 23 is a bus driver, 24
are character pixel data line 19, address data line 2
A refresh memory control unit for writing character pixel data sent by 0 to the refresh memory in accordance with a write command sent via the CPU data line 11, and having the above-mentioned pixel data buffer memory. ing.

Of these, 24-1 is a control unit for the image memory of the DoCopy device, and 24-2, 24-3, etc. are CRs.
It is for T. 25 is a refresh memory, 26 is a CRT
27 is a hard copy device; 28 is a CRT; 27 is a hard copy device; 28 is a CRT; 29 is CR
An input device such as a keyboard or a tablet is provided along with T. Reference numeral 30 is a signal line for transmitting commands from the input device 29 to the CPUIO.

Among these components...-Docopy device 27, C
A display control device is constituted by the portions excluding the RT 28 and the input device 29. Also, the image memory 25-1, the image memory control section 24-1, the character data buffer memory 12-1 correspond to the docopy+ device 27, and the CRT 28-1
It is assumed that the refresh memory 25-2, the refresh memory control section 24-2, and the character data buffer memory 12-2 correspond in this order. Since all of the circuits associated with these individual CRTs or hard copy devices operate in a similar manner, the operation of the circuits associated with CRT 28l will be described below. Now, before writing characters to the refresh memory 25-2, the refresh memory 25-
If you want to delete all the contents of 2, first select C from CPU1O.
Refresh memory 25 through PU data line 11
An erase command is sent to the refresh memory control unit 242 of -2.

Then, the refresh memory control section 24-2 digitally sets all contents of the refresh memory 25-2 to "O". When writing the necessary characters in such a state,
First, a command ``write character'' is sent from the CPU 10 to the refresh memory control unit 24-2.

Then, the refresh memory control section 24-2 sets the refresh memory 25-2 to the "character writing state" and sends a character data transfer request signal to the character data buffer memory control section 13.Then, the CPU 10 Character data is sent to the character data buffer memory 12-2.This character data consists of the character code of the displayed character, the X coordinate, Y coordinate of the character display position on the CRT, etc.
In addition, the character data buffer memory 12 has a capacity of several crosses to prevent wasted time due to the waiting time that occurs when multiple CRT terminals are used. If there is, the character data buffer memory control unit 13 immediately issues a request to transfer the next character data, and the CPUIO sends the character data to the character data buffer memory 12 in the same order. In this way, character data is stored in the character data buffer memory 12-2, but as mentioned earlier, the character data buffer memory control unit 13 has already received character pixel data from the refresh memory control unit 242. Since a transfer request has been issued, when at least one character worth of data is written to the character data buffer memory 12-2, the character data buffer is The memory control unit 13 instructs reading of this character data.

Among the read character data, address data is transferred from the address data bus line 14 to the address data transfer unit 15.
The address data line 20 is converted into parallel to serial data by the bus driver 23, and then sent to the refresh memory control unit 2.
4-2 address register. On the other hand, the character code read from the character data buffer memory 12-2 is sent to the character generation section 17 through the character code bus line 16, and compressed character pixel data is read out. This character pixel data is restored to the original complete character pixel data by the decoder 18, and is sent from the pixel data line 19 through the bus driver 23 to the refresh memory 24.
-2 is received in the character pixel buffer memory. In this way, the ``character write command'' from the CPUIO,
When the "address data" and "character pixel data" are completed in the refresh memory control section 242, the refresh memory control section 242 transfers the character pixel data to the refresh memory 2.
52 to the specified address. When character pixel data for one character starts to be written to the refresh memory 25-2, the refresh memory control section 24-2 sends a transfer request for the next character pixel data to the character data buffer memory control section 13, and the CPU 10 If the next character data is stored in the character data buffer memory 12-2, that data is read out and the same operation is performed.

Writing character pixel data to the refresh memory 25,
The operation of displaying on the CRT 28 is as described above, but if the content displayed on the CRT 28 is to be output to the hard copy device, a command to that effect is sent to the hard copy image memory control unit 24-1 through the CPU data line 11. The contents (video data) of the refresh memory 25 of the desired CRT terminal are sent to the hard copy image memory 25-1 through the data transfer line 26.

When data is written to this hard copy image memory 25-1, the contents are sent to the hard copy device 27 using a synchronization signal suitable for the operation of the doco copy device 27, and a hard copy is output. In addition, when sending character pixel data directly from the CPUIO to take a hard copy, the data is stored in the hard copy image memory 25-1 in exactly the same manner as in the case of displaying on the CRT 28 described above.
They are sequentially sent to and assembled, and the results are output as... Therefore, the image memory 25-1 corresponds to a refresh memory. Also like this CRT
If the content displayed on 28 is to be corrected, the instruction is made using the input device 29 such as a keyboard or tablet, and the signal is sent to the CPUIO through the signal line 30, and the correction is made in exactly the same manner as described above. It will be done.

Furthermore, when displaying not only character pixel data from the character generating section but also other data such as ruled lines, the CPU 10 sends a ruled line command to the refresh memory control section 24 in the same manner as described above. Furthermore, the coordinates of the starting and ending points of the ruled lines are sent to the character data buffer memory 12.

Then, as described above, there is a data transfer request from the refresh memory control section 24, and if the address data transfer section 15 is not in operation, this ruled line data is sent to the refresh memory control section 24, and the ruled line is stored in the refresh memory 25. written. [Hard copy device] The doco copy device has an image memory 25-1 corresponding to the refresh memory of a CRT terminal, and stores character pixel data, ruled line data, and other data sent in accordance with instructions from the CPU. Various data (hereinafter referred to as image data) and C
By transferring the video data already written in the refresh memory of the RT terminal to this image memory 25-1, and then reading out the contents of this memory using the hard copy synchronization signal, the necessary information can be obtained at any time. It is structured so that it can be output as a hard copy.

In response to a hard copy request from the CRT, the data displayed on the CRT may be newly generated from the above-mentioned display control device and sent to the hard copy image memory, but in this case, data processing and character pixel data The transfer will take time and the burden on the software will increase accordingly. However, in the present invention, since the contents written in the refresh memory of the CRT are transferred to the image memory of the hard copy device, it takes only one field time, and there is no increase in the burden on the software. FIG. 3 shows an embodiment of the control circuit of the DoCopy device, which is included in the image memory control section 24-L and the image memory 25-1 shown in FIG.

In the figure, reference numerals 31 and 32 are image memories having the same configuration as the refresh memory of a CRT terminal; 31 is a shift register;
2 is a random access memory. Although not shown in the figure, 31 and 32 are connected so that data can be transferred to each other. 33 is a hard copy driver circuit, 34 is an input terminal for a match signal of an address for writing character pixel data, and 35 is a command from the CPU that is sent from the character generator through the character pixel data buffer memory in the refresh memory 24. Input signal line for character pixel data, 3
6 is the refresh memory 25-2, 253 of the CRT terminal.
, 25-4 through the transfer line 26, and 37 is a horizontal scanning line for writing the video data commanded by the CPU and the video data sent from the CRT terminal into the shift register 31. Input line for shift pulses to the shift register generated for each pixel unit of the line, 38
is a shift pulse input line for shifting the shift register 31 when outputting a hard copy, and 39 is a CPU or CRT input line.
40 is the input line for the horizontal sync signal when writing the data sent from the terminal to the memory 32, 41 is the input line for the horizontal sync signal when outputting a hard copy, and 41 is generated by character data commanded by the CPU. Character pixel data to image memory 3
42 is an input terminal for a hard copy command when transferring video data from the refresh memory of a CRT terminal to take a hard copy. An input terminal for the same vertical synchronization signal that is sent, 44 is an input terminal for a signal from the hard copy device to notify that hard copy has finished, 45 is an output terminal for a copy start signal, and 46 is a hard copy signal. output terminals, 47, 48
, 49 are flip-flops (hereinafter abbreviated as FF), 50 to 57 are AND circuits, 58 to 61 are OR circuits, and 62 to 64 are NOT circuits.

If the image data sent directly from the CPU to the image memory 32 is character data, the CPU sends the character data and address data, and the character pixel data is sent to the input terminal in the same way as when displaying characters on a CRT terminal. 3
It will be sent to 5.

When the write address data of the image memory and the write timing of the memory 32, which are similarly sent from the CPUIO, match, an address match signal is sent to the input terminal 34.
, the AND circuit 51 opens and the OR circuit 58
The data reaches the AND circuit 52 through. Since no hard copy command 42 has been received, the FF 48 has been reset, and since no signal has reached the NOT circuit 63, the AND circuit 52 is open, so the character pixel data passes through the OR circuit 59. The signal is sent to the shift register 31. This shift register 31 and memory 32 are FF4
9 is set, a display shift pulse 37 and a horizontal synchronizing signal 39 are sent from AND circuits 54 and 56, and character pixel data is written in exactly the same way as when displayed on a CRT terminal. When all the character pixel data is thus written into the image memory 32, a hard copy command 41 is sent from the CPU, the FF 49 is set, and a hard copy start signal 45 is output. Then, the display shift pulse 37 and the display horizontal synchronization signal 39 are closed by the AND circuits 54 and 56, and the AND circuits 55 and 57 for the hard copy shift pulse 38 and the hard copy horizontal synchronization signal 40 are opened. The memory 32 and the shift register 31 are operated by the docopy synchronization signal, and the video data in the shift register 31 is outputted from the hard copy output signal terminal 46 through the hard copy driver 33. When the hard copy is completed, a hard copy end signal 44 is sent.
comes, FF49 is set, and all operations are completed. When video data is transferred from the refresh memory of the CRT to the memory 32 to make a hard copy, a request for hard copy input from the console 29 of the CRT terminal requesting a hard copy is sent to the signal line 30 ( First, the CPU receives the data via the CPU (FIG. 2).

If the hard copy device 27 is not in use, or if it is in use, the CPU waits until the hard copy device 27 becomes free, and sends the device address of the CRT terminal issuing the hard copy command and request to the memory control unit 24-1 of the hard copy device. send. The video data in the refresh memory of the CRT selected by this address is sent to the input terminal 36. The hard copy command sent to the input terminal 42 sets the FF 47, and then its output reaches the FF 48, and this FF 48 is set in synchronization with the vertical synchronization signal 43. Then, the FF 47 is reset by the Q output of the FF 48, and the AND circuit 53 is opened by the Q output. Therefore, the transferred video data 36 from the CRT refresh memory that has reached the AND circuit 53 is sent to the shift register 31 through the OR circuit 59. In addition, at this time, the shift register 31
The shift pulse 37 for display and the horizontal synchronization signal 39 have reached the memory 32 as described above. In this manner, when the next vertical synchronizing signal 43 arrives, since FF 47 has already been reset, FF 48 is reset, and at the same time as AND circuit 53 is closed, FF 49 is set, and a hard copy is made in the same manner as above. This concludes the present invention...
We have explained about the docopy device, but by configuring the hard copy device in this way, it is possible to arbitrarily obtain a hard copy of the items currently displayed on the CRT, or even the displayed items that are instructed by the CPU. can be done and is very useful.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a device having multiple display terminals, and FIG. 2 is a block diagram of an embodiment of the multi-terminal display control device of the present invention.
FIG. 3 shows an embodiment of the hard copy control circuit of the present invention. 1...CRT, 2...Keyboard device, 3...Tablet device, 10...C
PU, 12...Character data buffer memory, 1
3...Character data buffer memory control section, 15
...Address data transfer section, 17...
Character generation section, 18... Decoder, 21...
... Synchronization signal generation section, 23 ... Bus driver, 24 ... Refresh memory control section, 25.
...Refresh memory, 27...Hard copy device, 28...CRT terminal, 29...
...Input/output device.

Claims (1)

[Claims] 1 In a hard copy device in a multi-terminal display control device equipped with multiple input/output terminal devices such as a CRT 28 and an input device 29, a CPU that sends data requested by each terminal.
10, a character data buffer memory 12 provided corresponding to each CRT and storing a plurality of character data sent from the CPU 10, and this character data buffer memory 12.
a single character generating section 17 that generates character pixel data according to the character code sent from the character generating section 17; and a refresh memory 25 provided corresponding to each of the CRTs 28 to store the character pixel data sent from the character generating section 17. -2, 25-3, 2
5-4 Write in ・・・・・・・・・・・・ and CR
Refresh memory control unit 24-2 to be displayed on T28
, 24-3, 24-5... and the above CR
T refresh memories 25-2, 25-3, 25-4
. . . Among them, the video data in the designated refresh memory is transferred to the image memory 25-1, or various data generated by instructions from the CPU 10 are transferred. It includes an image memory control unit 24-1 that instructs the image memory 25-1 to assemble the image data, and a single hard copy device 27 that outputs the video data and image data stored in the image memory 25-1. A hard copy device in a multi-terminal display control device, characterized in that: