JPS5926969B2 - Multi-terminal centralized display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multi-terminal centralized display control device that centrally controls the display of a plurality of cathode ray tube display devices.

Background of the Invention In fields such as newspaper typesetting and general printing, in order to speedily correct and proofread text, as well as various editing processes,
Recently, as schematically shown in FIG. 1, a typesetting processing apparatus including an electronic computer 5 (hereinafter simply referred to as a CPU) and a cathode ray tube display device 1 (hereinafter simply referred to as a CRT) has come into use.

In such a device, various articles and texts are
You can store it in the storage device of U, monitor it displayed on the CRTI, and also specify corrections, proofreading, formatting format designation or changes to the article from the keyboard input device 2, tablet input device 3, etc., and use the CPU to make these changes. By processing commands, various editing processes can be performed quickly and easily. However, when using such a device, it is common to use a plurality of the above-mentioned input/output terminals, and these terminals are often installed at locations separated from each other.

However, in the case of Japanese text, the character generation section that generates characters to be displayed on a CRT handles a large number of characters, requires a large storage capacity, and is very expensive. Therefore, it is not a good idea from a cost standpoint to provide each CRT with a character generation section, and it is better to centrally control these multiple CRTs with a display control device that includes one character generation section. convenient. Also, like this, one CPU can handle multiple CRs.
When controlling the T, data transfer between each terminal and the CPU requires multiple processing using interrupts, so transferring characters from the CPU to each CRT one by one would waste time in program processing. arise. In order to prevent this, it is necessary to store several cross-shaped character data (display character code, display position address code, etc.) for each CRT.
If a character data buffer memory that can be received from the PU and temporarily stored is prepared, and this character data buffer memory, character generator, and refresh memory corresponding to each CRT are housed together in the display control device, Display character data can be transferred from the CPU to each CRT at once, which improves the effective speed of data transfer.Furthermore, the transfer speed of pixel data between the character generator and refresh memory is increased, and the cost required for transfer is reduced. I get kicked. OBJECTS OF THE INVENTION Accordingly, a first object of the present invention is to provide a multi-terminal centralized display control device that is low-cost, high-speed, and rich in variety.

A second object of the present invention is to reduce wasted time in data transfer from the CPU to each terminal in a device in which multiple CRTs can be driven by a single character generator.
A display control device is provided with a character data buffer memory having a capacity of several crosses for each T, and a character data buffer memory control section that controls each terminal to use the character generating section equally. It is to provide.

Summary of the Invention In order to achieve the above object, a display control device of the present invention centrally controls a plurality of CRTs.
A CPU that sends out data requested by each CRT, a character data register provided corresponding to each CRT and temporarily storing character data sent from the CPU, and a character data register provided corresponding to the character data register. a plurality of character data buffer memories storing N pieces of character data stored in character data registers; and a CRT from the CPU.
Assembling the character data from the CPU into a character data register corresponding to the CRT selected by the selection command as a pair of display character code and display position address code on the CRT display screen; a character data buffer memory write control circuit that writes the data set to the character data buffer memory corresponding to the character data register; and a character data buffer memory write control circuit that writes the data set to the character data buffer memory corresponding to the character data register; one character generating unit that generates characters one by one and supplies them to each CRT; and cyclically reading a pair of data sets from the plurality of character data buffer memories according to the operating status of this character generating unit;
and a character data buffer memory read control circuit that supplies the character generating section.

Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

In Figure 2, 10 is a data line from CPUIO, 12 is a character data buffer memory I8 that can store several cross characters of character data (character code, display position address code) sent from CPUIO, and 13 is character data. A character data buffer control unit 14 controls writing and reading of data in the buffer memory 12;
Display position address code transfer line 15 is an address data transfer unit that converts parallel data sent through the address code transfer line 14 into serial data and transfers the serial data;
6 is a transfer line that transfers the character code to the character generation section 17, and 17 is a readout control section that controls reading out character pixel data for one character specified by the character code sent on the character code transfer line 16. The character generating section 18 is a character pixel decoder that restores the character pixel data read from the character generating section 17 from the compressed state, and is unnecessary if the character pixel data in the character generating section is not compressed. be. 19 is a character pixel data line for transferring the character pixel data restored by the character pixel decoder 18; 20 is a display position address code line; 21
22 is a synchronous signal transfer line, 23 is a bus driver, 24 is a character pixel data line 19, and a display position address code line 20. 24-1 is a refresh memory control unit for writing character pixel data sent from the CPU to the refresh memory 25 in accordance with a write command sent from the CPU via the data line 11. It is a control unit for the image memory of the copying device 27, and includes 24-2, 24-3, . . .
... is for CRT.

25 is a refresh memory; 26 is a transfer line for transferring the contents of the refresh memory 25 corresponding to each CRT to the hard copy image memory 25-1 in order to output the contents displayed on the CRT to the hard copy device 27; ,2
7 is a hard copy device; 28 is a CRT; 29 is an input device such as a keyboard or tablet attached to the CRT; 30 is a signal line for transmitting commands from the input device 29 to the CPUIO.

Among these components, the hard copy device 27 corresponds to an image memory 25-1, an image memory control section 24-1, a character data buffer memory 12-1, and a CRT 28.
-1 includes a refresh memory 25-2, a refresh memory control section 24-2, and a character data buffer memory 12-2.
They correspond in order of 2.

Since the circuits associated with each of these individual CRTs or hard copy devices all operate in the same way, we will refer to them below as CRTs.
The operation of the circuit related to 28-1 will be explained as a representative example. If you want to erase all the contents of the refresh memory 25-2 before writing characters to the refresh memory 25-2, first, the refresh memory control section of the refresh memory 25-2 is A deletion command is sent to 242.

Then, the refresh memory control section 24-2 digitally sets all contents of the refresh memory 25-2 to "0". When writing a necessary character in such a state, the CPU 10 first sends a command "write character" to the refresh memory control unit 24-2.

Then, the refresh memory control unit 24-2 sets the refresh memory 25-2 to ゜Character writing state'' and sends a character data transfer request signal to the character data buffer memory control unit 13.Then, the character data is transferred from the CPUIO. Character data is sent to the buffer memory 122. This character data consists of the character code of the displayed character, the address code of the X and Y coordinates indicating the display position of the character on the CRT, etc. Character data buffer memory 122
The character data buffer memory 12-2 has a capacity of several crosses in order to avoid wasted time due to the time that occurs when multiple CRTs are used. A request to transfer the next character data is immediately issued from the buffer memory control unit 13, and the character data is sent from the CPUIO to the character data buffer memory 12-2 in the same order. In this way, character data is stored in the character data buffer memory 12-2, but as mentioned earlier, character pixel data has already been transferred to the character data buffer memory control unit 13 from the refresh memory control unit 24-2. Since a request has been issued, when at least one character's worth of data is written to the character data buffer memory 12-2, the character data buffer is The memory control unit 13 instructs reading of this character data.

Among the read character data, the display position address code is converted from parallel to serial by the address code transfer unit 15 from the address code transfer line 14, and then transferred to the address code line 2.
0 through the bus driver 23 to the address register of the refresh memory control section 24-2. On the other hand, the character code read from the character data buffer memory 12-2 is sent to the character generation section 17 through the character code transfer line 16, and the character pixel data is read out. If this character pixel data is data compressed, it is restored to the original complete character pixel data by the character pixel decoder 18 and sent from the character pixel data line 19 through the bus driver 23 to the refresh memory controller 245.
It is stored in the character pixel buffer memory in 2. In this way, when the character pixel data 1 of the one-character write command "display position address code" from the CPUIO is completed in the refresh memory control section 24-2, the character pixel data is transferred to the address specified by O in the refresh memory 25-2. The character pixel data for one character is written to refresh memory 2.
5-2, the refresh memory control unit 24-2 sends a transfer request for the next character pixel data to the character data buffer memory control unit 13, and the next character pixel data is transferred from the CPUIO to the character data buffer memory 12-2. If character data is stored, that data is read out and the same operation is performed thereafter.

The operation of writing character pixel data into the refresh memory 25-2 and displaying it on the CRT 28-1 is as described above, but when outputting the content displayed on the CRT 28-1 to the hard copy device 27, the CPU data line A command to that effect is sent to the hard copy image memory control unit 24-1 through the data transfer line 26.
The contents of the refresh memory 25-2 of T28l are sent to the hard copy image memory 25-1.

When data is written to this hard copy image memory 25-1, the contents are sent to the hard copy device 21 using a synchronization signal suitable for the operation of the hard copy device 27, and a hard copy is output. In addition, when sending character pixel data directly from the CPUIO to take a hard copy, the display data is stored in the hard copy image memory 25-1 in exactly the same manner as in the case of displaying on the CRT 28-1 described above.
1 and a hard copy output is taken. Also CRT2
If the content displayed at 8 is to be corrected, an instruction is given using the input device 29 such as a keyboard or tablet, and the signal is sent to the CPU 10 through the signal line 30, and the correction is made in exactly the same manner as described above.

When displaying crossed lines, the CPUIO sends a line drawing command to the refresh memory control unit 24-2, and the coordinates of the start and end points of the lines are sent to the character data buffer memory 12-2.
send to

Then, as described above, there is a data transfer request from the refresh memory control section 24-2, and the address data transfer section 15
is not in operation, this ruled line data is sent to the refresh memory control section 24-2, and the refresh memory 25-2 is sent to the refresh memory control section 24-2.
2, and the ruled lines are displayed on the CRT 28-1. Next, details of the character data buffer memory 12 and the character data buffer control section 13 that controls writing and reading thereof will be explained using FIG.

The following explanation will be based on one character data buffer memory 12-2 according to the above example, but the other characters operate in exactly the same manner. In the figure, 101 is a character data register, 10
2 is a character data buffer memory control unit 103 is a character data buffer memory control unit, 104 is a character data line from the CPU shown as 11 in FIG. 2, and 105 is a character data register selection line (equipment address line). , 10
Reference numeral 6 denotes a signal line that sends a data acquisition pulse for loading the character data placed on the CPU data line 104 into the character data register 101; 107 a load sequencer for distributing the data acquisition pulse to each character data register; 108 is the signal line, 109 is 14,1 in Fig. 2
Output line of character code and display position address code from character data buffer memo January 02 shown as 6, 110
is a storage request flag indicating that character data has been transferred from the CPU data line 104 to the character data register 101 and can be stored in the character data buffer memory 102, 111 is an AND circuit, and 112 is a storage request flag from the storage request flag. 113 is a storage request flag set line; 114 is an input enable line that gives permission to store the contents of the character data register 101 in the character data buffer memory 102; a data capture pulse line for capturing data into the firmware memory 102;
Reference numeral 116 indicates an input date signal indicating that data can be stored from the character data register 101 to the character data buffer memory 102, and 117 indicates an output indicating that character data can be read from the character data buffer memory 102. Ready signal 118 is a read selection signal that sequentially selects character data buffer memories provided corresponding to a plurality of CRTs to enable reading; 119 is a character data buffer selected by read selection signal 118; 120 is a shift-out pulse signal line for reading character data from the memory 102; 120 is an input line for a character pixel data transfer request signal; 121 is a read flag set signal line for activating the read control section of the character generating section 17; An input line 123 for a read ready signal from the character generator indicating that the read controller of the character generator is not in operation and reading is possible is a character data buffer memory 102 to the character data register in the character generator.
This is the output line for the capture pulse for capturing character data from.

FIG. 4 shows an example of the write control circuit 103W of the character data buffer memory control section 103 shown in FIG. 3, and FIG. This is an example of the circuit 103R.

130, 131, 132, 133, 134 in both figures
, is a JK flip-flop (hereinafter abbreviated as FF), 1
35, 136, 137 are 3-bit binary counters, 1
38, 139, 140 are decoders, 141, 142, 1
43 is an OR circuit, and 144 to 148 are AND circuits.
The character data buffer memory 12 corresponding to each of the plurality of CRTs 28 has a separate device address for the CPU, and when character data is sent from the CPU to the character data buffer memory, register selection is required. line 1
A signal is sent to character data buffer memory 102.
Characters are written to .

Assuming that the character data currently being sent through the CPU data line 104 consists of 3 bytes (character code, XlY display position address code) and a selection signal is being sent to the register selection line 105, the character data that is being sent continuously is The coming 3-byte data acquisition (strobe) pulse is processed by the data acquisition pulse 106 which is sequentially distributed to the sequence pulse line 108 by the code sequencer 107, so that the 3-byte character data is stored one byte at a time in the character data register. 101. In this way, when all of the character data consisting of 3 bytes is taken into the character data register 101 and collected as data for one character, the third panores (
As a result, the data storage request flag 110 is set. Then, the storage request signal 112 of the flag 110 passes through the OR circuit 141 of the write control circuit 103W shown in FIG. Set. Then, the output Q of this FFl3O is 2
The reset state of the advance counter 135 is released and the signal is applied as an input enable signal (input enable signal) 114 to the AND circuit 111 in FIG. Now this AND circuit 11
Since a signal is sent to character data register 1 from storage request flag 110 through signal line 112, character data register 1 is opened.
The contents of 01 can now be stored in the character data buffer memo I river 02. On the other hand, the pulse CP
A pulse CPl with the opposite polarity of the pulse CPl with the same repetition frequency as 2 but with a phase shift of half a cycle is added,
This pulse starts counting. The three outputs QA, QB, QC of this counter 135 are sent to the decoder 13
8, the output YO~ of the decoder 138
A pulse that switches in synchronization with pulse CPl is obtained from Y7. Now, when an output is output from Y1 of this decoder 138, FFl3l is set in synchronization with the falling edge of pulse CP2, and then when the output from Y1 disappears and an output is generated from Y2, it is synchronized with the falling edge of pulse CP2. FFl3l is set, and the output 11 of this FFl3l
5, a positive pulse is obtained. This pulse is sent as a data take-in pulse 115 to the character data buffer memory 102 in FIG. 3, and the contents of the character data register 101 are stored in the character data buffer memory 102. When an output is output from Y4 of the decoder 138, it is sent to the signal line 113, and the storage request flag 110 in FIG.
The FF13O value is set in synchronization with the FF13O value. In this way, character data is sequentially written into the character data buffer memory 102, but character data for at least l characters is currently stored in the character data buffer memory 102, and the output ready signal 117 is output. Furthermore, a character pixel data transfer request signal 120 is received from the CRT's refresh memory control section 25, and a signal 122 indicating that the character generation section 17 and address data transfer section 15 are not in operation is also received. , character data buffer memory 102
Character data is read from. If at least one character data is currently stored in character data buffer memory 102, output ready signal 117 has reached AND circuit 144 in FIG.

This AND circuit 144 includes a refresh memory control section 2
Since the character pixel data transfer request signal 120 from 4 has also arrived, this gate opens and the signal reaches the OR circuit 142 and the AND circuit 147, and the signal that has reached the OR circuit 142 passes through this and goes to the AND circuit 145. reach As mentioned above, the read ready signal 122 from the character generation section has reached the AND circuit 145, and since FF133 is currently in the set state, the signal from this AND circuit is sent to the J of FF132.
It reaches the input terminal and is set by pulse CP2.
The output Q of this FF132 enables the binary counter 136 (countable state), and the counter 136 starts incrementing by the pulse CP1 as described above. The three outputs QA, QB, QC of this counter 136 are connected to the decoder 139 as described above, and the decoder 13
Output pulses synchronized with pulse CPl are obtained from the outputs YO to Y7 of 9. Now, if an output is obtained from YO of this decoder 139, the signal will be output from AND circuits 146 and 147.
reach. And the AND circuit 147 has the AND circuit 14
Since the signal from 4 has arrived, this is opened, and the signal passes through the OR circuit 143 and reaches the AND circuit 148. As described above, this AND circuit 148 receives the character pixel data read enable signal 122 from the character generating section, so it is also opened, and the signals reach FF132 and FF133, and the next pulse CP2 sets FF132 and FF133. is set. When FFl32 is reset, the output Q disappears and the counter 136 is prohibited from advancing, and FFl32 is reset.
33 is set, AND circuit 145 is also closed, so the output YO of decoder 139 remains held. On the other hand, the output Q of FFl33 is output from the AND circuit 146.
, reaches the counter 137, and sends a character data read selection signal to the character data buffer memo January 02 in FIG. Allows you to step forward with CPl. FF133, counter 137, and decoder 140 are character data buffer memory 1
It constitutes a sequence circuit for reading character data from Y1 of the decoder 140. First, when an output is output from Y1 of the decoder 140, it is transmitted to the character generation section via the signal line 123, and is first output by the readout selection signal 118. This signal is used to take in the character data that has been placed on the character data line 109 from the character data buffer memory 102 into the character data register in the character generation section.

Next, when an output 121 is output from Y2 of the decoder 140, this becomes a start signal for setting a flag in the readout control section of the character generation section and reading out the character pixel data of the desired character. When the section starts operating, the read ready signal on the signal line 122 disappears. Therefore, AND circuits 145 and 148 are closed, and even if other CRs
Even if an output ready signal and a character pixel data transfer request signal are received from the character data buffer memory 12 corresponding to T, the desired character pixel data is transferred to the refresh memory controller 25 by the character data output from the character data buffer memory 102. The next character data will not be read until the next character data is transferred. Furthermore, the output terminals Y3 and Y of the decoder 140
When the outputs are output in order from 4, the FF134 is set and reset by the pulse CP2, and the pulse for shifting out the character data that has just been sent from the output terminal 119 to the character generation section is output from the character data buffer memory 102. Let it fall on the edge. Finally, when an output is output to the output terminal Y6 of the decoder 140, the FF133 is reset, and when the character pixel data has been sent to the refresh memory control section, the read ready signal 122 of the character generation section is sent. Incidentally, the FF132, counter 136, and
The decoder 139 constitutes a check circuit for cyclically allocating the use of the character generation section to a plurality of CRTs, and when the character data transfer from the character data buffer memory 102 is completed, the AND circuit 144 On the diagram,
When the output ready signal and the character pixel transfer request signal are sent from another character data buffer memory to the AND circuit shown below, counter 1 is activated by the same operation as described above.
36 advances, an output is output from the output terminal Y1 of the decoder 139, and character data is read from the character data buffer memory of another CRT.

Effects of the Invention Since the present invention is constructed as described above, character data for several crosses can be transferred from the CPU at once, and the execution speed of high-speed data transfer can be improved at low cost.

Furthermore, a plurality of CRTs can equally use one character generating section, and also has great effects such as being able to display data at high speed.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a conventional device with multiple display terminals;
FIG. 3 is a block diagram showing an embodiment of the multi-terminal centralized display control device of the present invention, FIG. 3 is a block diagram of the character data buffer memory and its control unit shown in FIG. 2, and FIGS. 4 and 5. is a partially detailed explanatory diagram of FIG. 3; 10...CPUll2...Character data buffer memo 18 13...Character data buffer memory control section, 17...Character generation section, 24.
...Refresh memory control section, 25...
・Refresh memory, 28...CRTllO
l...Character data register, 102...
・Character data buffer memory, 103...Character data buffer memory control unit, 103W...Character data buffer memory write control circuit, 103R...
...Character data buffer memory read control circuit.

Claims (1)

[Claims] 1. In a display control device that centrally controls multiple CRTs 28, a CRT that sends data requested by each CRT 28
PU 10 and a CPU provided corresponding to each of the CRTs.
A character data register 101 that temporarily stores character data sent from 10, and this character data register 1
A plurality of character data buffer memories 102 are provided corresponding to 01 and store N pieces of character data stored in the character data register, and a character data buffer memory 102 corresponding to the CRT selected by the CRT selection command from the CPU 10 is provided. The character data from the CPU 10 is assembled in the data register 101 as a pair of display character code and display position address code on the CRT display screen, and the character data corresponding to the character data register 101 is assembled. A character data buffer memory write control circuit 103W writes the set of data to the buffer memory 102, and a character data buffer memory write control circuit 103W generates characters one by one based on the pair of data sets written to the character data buffer memory 102 and writes the data set to each CRT.
one character generation unit 17 that supplies the character generation unit 1 to
a character data buffer memory read control circuit 103R that cyclically reads out a pair of data sets from the plurality of character data buffer memories according to the operating status of the character data buffer memory 7 and supplies the data sets to the character generation section 17; Device.