JPH0126073B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for displaying characters on a screen in a character display device using a cathode ray tube (hereinafter abbreviated as CRT).

Configuration of Conventional Example and its Problems First, a CRT character display device according to the present invention will be described with reference to FIG. In the figure, 1 is a CPU that performs processing according to instructions written in memory 2. As an example, a keyboard (not shown) is connected to terminal 12, and according to data from the keyboard, the display monitor The process of displaying characters on the screen will be explained. In order to display on a CRT screen, a synchronization signal for synchronization and a video signal for displaying characters are required, and the synchronization signal is transmitted to the CRT controller (hereinafter referred to as
This is assumed to be generated by an LSI called CRTC (abbreviated as CRTC). It is assumed that the synchronizing signal k and the video signal n from the CRTC 5 are outputted to the terminal 13, and displayed on a CRT (not shown) screen via an amplification circuit (not shown) or the like.

Now, when data from the keyboard is input to the terminal 12, it is input to the CPU 1 by the input/output circuit 4 through the data bus a. The CPU 1 temporarily stores the input data in the memory 2, and then writes the data to the display memory 7 in a one-to-one correspondence with the CRT screen. That is, this is done by outputting the address of the display memory 7 corresponding to the position to be displayed on the CRT screen (usually the position of the cursor) through the address bus b, and the data to be displayed through the data bus a. In addition, the display memory 7
is constantly read out at a certain period (usually about 17mS) to display static characters on the CRT screen, and the control for this is done by CRTC5.
is being carried out. Then, the select circuit 6 switches the address of the display memory 7, and at the same time, the buffer 8 switches the data so that the read operation of the CRTC 5 and the write (or read if necessary) operation of the CPU 1 are performed in a time-sharing manner. Perform switching. That is, during the read operation of the CRCT5, the control line m from the timing circuit 3
The address line c from the CRTC 5 is connected to the address line d of the display memory 7, and at the same time, the buffer 8 separates the data bus a from the data line f of the display memory 7 by means of the control line e from the CPU 1. In this state, the read contents of the display memory 7 are loaded into the latch 9 and then supplied to the character generator 10, where a pattern to be displayed on the screen is selected. Then, a display pattern for one raster line of display characters on the screen is outputted to a display data line h by a raster position address line c' from the CRTC 5. The display data is converted into serial data by a parallel-serial conversion circuit 11, and outputted as a video signal to a video signal line n.

In such a configuration, erasing the screen display means writing data that is not displayed in the display memory 7, and conventionally, the CPU 1 writes one piece of data to all of the display memory 7. For this reason, the process of screen erasing consumes CPU 1 for a long time, and
This caused the usage efficiency of CPU1 to decrease. Also,
When displaying input data from a device other than a keyboard (for example, data from another computer device), inconveniences arise when the input data is high speed and large in amount. In other words, if there is input data while CPU 1 is performing screen erasing processing (because screen erasing processing takes time), CPU 1 temporarily suspends screen erasing processing and temporarily stores the input data in memory 2. It is necessary to save the data and write it into the display memory 7 after the screen erasing process is completed. Therefore, an extra memory is required to temporarily save input data.

OBJECTS OF THE INVENTION The present invention aims to eliminate these conventional drawbacks and to perform screen erasing processing at high speed with a simple configuration.

Structure of the Invention In the present invention, the CPU writes data indicating the screen erase start position to the display memory, and when the erase start position is reached during the CRTC read operation, the erase data is thereafter written to the display memory during the CRTC read operation. The same data is output as a video signal at the same time as the data is written to the screen, and when the CRCT reading reaches the final position on the screen, the erasing operation ends and the normal operating state is restored.

DESCRIPTION OF EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of the present invention, and the same numbers as in FIG. 1 represent the same elements. FIG. 3 is a timing diagram for explaining the operation of the present invention. In FIG. 2, first, the CPU 1 transfers erase start data (for example, if the display memory has an 8-bit configuration, any one bit of it, for example, bitφ
data) is written, and at the same time one of the flip-flops 21 of the erase control flip-flops 20 and 21 is set. That is, by changing the control line p from "L" to "H", the Q output of the flip-flop 21 is set to "H". At this time, the erase control line q connected to the output terminal Q of the other erase control flip-flop 20 remains at "L" and is in the normal operating state. When the read operation of the CRTC 5 reaches the erase start position, the erase start data, which is the content thereof, is read out, and when set in the latch 9, it is detected by the erase position detection circuit 22.
As a result, the erase position detection control line s becomes “L”→
The erase control flip-flop 20 changes to “H”.
is the level of the input terminal D (that is, the level of the output Q of the flip-flop 21 is "H")
The erase control line q becomes "H" and enters the erase operation state. In this state, during the reading period of CRTC5, address line c is connected to address line d.
Since the control line q is connected to each terminal t, the read/write control line t of the display memory 7 is “H”.
Therefore, read operation in normal state (“L” level)
A write operation (“H” level) begins. The write data at this time is given by the erase data supply circuit 23, and is set in the latch 9 at the same time as the data is written into the display memory.
Needless to say, the erased data set in latch 9 is not displayed on the screen. Also, once the erase operation state is entered, the erase position detection circuit 2
Even if the erase position detection control line s, which is the output of the erase control flip-flop 20, changes, the output Q of the erase control flip-flop 20 does not undergo any change and remains at the "H" level.
The erase operation ends when the reset terminals R of the erase control flip-flops 20 and 21 become "L", and in the embodiment shown in FIG. 2, the synchronization signal (vertical synchronization signal) of the CRTC 5 is used. In other words, the synchronization signal k goes to "L" level after the character display operation on the screen ends, and goes to "H" before the next display starts, so the erasing operation ends only when the character display operation ends. It's time.

Incidentally, the erase position detection circuit 22 can be constituted by, for example, a gate circuit as shown in FIG. 2b. Control lines 1, 2 and 3 are connected to address line c', and control line 4 is connected to one of data lines q which is the output of display data latch circuit 9. Now, if we consider that the character display consists of eight vertical scanning lines per character, in order to realize the "H" character display as shown in Figure 3a, it is necessary to display the character once for each scanning line. , the display memory 7 is read a total of eight times, and the address line c' is used to select one of the scanning lines in each vertical direction. When using the erase position detection circuit 22 of FIG. 2b, the control lines 1, 2,
3 are all at “H” level, that is, Fig. 3a
The erasing position will be detected during scanning (H8), making it possible to start erasing from any position. If you use the scanning times of (H1) to (H7) in Figure 3a, all the rows will be erased during (H8) scanning, so
The erasure start position is in line units.

Figure 3b shows the operation timing, where time 0 to t _C indicates one character time, of which time t _B is
During the display operation period of CRTC5, the time (t _C - t _b ) is
This shows that the CPU 1 is time-divided into the period in which it reads and writes to the display memory 7. A indicates the control line m in Figures 1 and 2, and the <CRTC> period is
Address line c and control line q from CRTC 5 are connected to address line d and read/write control line t of display memory 7. <CPU> The period is CPU1
An address line b and a control line e from the address line b and a control line e are connected to an address line d and a read/write control line t, respectively. Now, during the <CRTC> period, when the address is supplied to the display memory 7, the display memory 7
After the access time t _a , the contents of the memory 2 are output to the display memory data line f as shown in FIG. 3B. This data is set to latch 9 at time t _b.
The data line g, which is the output of latch 9, is set to
is as shown in Figure 3C. And data line g
is input to the character generator 10, and the access time (t _C
-t _b ), the display data, which becomes a video signal as shown in FIG. 3D, is output on data line h, which is captured by the parallel-to-serial converter 11 at time t _d and as shown in FIG. 3E. , which is converted into a serial signal and output as a video signal.

Effects of the Invention As shown above, in the past, since erase data was written from CPU 1 to display memory 7 using only the <CPU> period, CPU 1 could not perform any other processing during the erase operation, and It is generally difficult to write one erase data with only
Even if it were possible, it would require the use of a very high-speed CPU, which would increase costs, and the erasing operation would take a long time. According to the invention
The CPU only needs to write the erase start data once to the erase start position and set the erase control flip-flop, and the CPU can perform other processing operations even in the erase operation state. It is particularly effective when displaying and processing large amounts of input data at high speeds, and when the display on the CRT screen becomes full, it is easy to erase the display and start anew from the beginning.

In the embodiment shown in FIG. 2, the erasure end position is the end of the screen display, but an erasure end position detection circuit may be provided in the erasure position detection circuit 22 in the same way as the erasure start position detection circuit. Needless to say. There are also 256 types of data to start erasing (8
It is also possible to allocate one of the data (in the case of bit data).

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a character display device using a cathode ray tube, FIGS. 2a and b are diagrams showing the configuration of a cathode ray tube display device in an embodiment of the present invention, and FIGS. FIG. 3 is a timing chart showing the operation of the device of the present invention. 1...CPU, 2...Memory, 3...Timing circuit, 4...I/O circuit, 5...CRT controller, 6...Select circuit, 7...Display memory, 8...Buffer, 9...Latch Circuit, 10...
... Character generator, 11 ... Parallel-serial converter, 20, 21 ... Flip-flop, 22 ... Erase position detection circuit, 23 ... Erase data supply circuit.

Claims (1)

[Claims] 1 has a CPU, a display memory corresponding one-to-one with a screen display screen, and a display control circuit, and the CPU controls approximately half of the first period for the display memory, and controls the remaining approximately half period for the display memory. a select circuit is provided so that the display control circuit can access each of the contents, and the display control circuit is configured to read out and display all contents of the display memory in a second period, and the display control circuit a first detection circuit that detects erased data on the screen among the display contents read out by the display; and an output that generates an output based on the output signal of the first detection circuit and stops the output at the second periodic signal. and a control circuit for changing a read access signal of the display memory of the display control circuit to a write access signal during a period when the output of the output control circuit is generated, and writing screen erase data to the display memory. A cathode ray tube display device.