JPS63254537A - Data comparator for data processor - Google Patents

Abstract

PURPOSE:To obtain a data processor having the fail-safe properties by securing such a constitution where the data received from processors are compared with each other via a comparator for each bit and an error detecting circuit stops the transmission of an alternating signal by a coincidence signal received in response to the discordance of said data comparison. CONSTITUTION:If some discordant bits are detected out of the data on data buses DB5 and 15, a discordance signal UAS is produced before generation of an end bit signal BES and a flip-flop FFC40 kept set is reset. Therefore an FFC39 is kept reset under such conditions and both outputs (g) and (h) are set 0. Hereafter an output (h) is not set at 1 but fixed at 0. Thus the transmission an alternating signal is stopped. if the FFC40 is kept reset when the signal UAS is produced, the FFC39 is kept set and the output (g) is kept at 1. Then the FFC40 is changed to a set state to set the output (h) at 1. Thus both FFC39 and 40 maintain the reset states hereafter and fix the output (h) at 1 to stop the transmission of the alternating signal. In such a way, the fail-safe properties are secured for a data processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data comparator for a data processing device that requires high reliability and fail-safe performance.

[Conventional technology]

Processor-based data processing equipment does not have fail-safe properties against the occurrence of failures or errors, and is used in data processing equipment for railway signal control, etc., which requires high reliability and fail-safe properties. is at least 3
A multi-processor system is used, which compares each data indicating the processing status of each processor, obtains a majority vote on the same data, and only data that satisfies this condition is valid. Japanese Patent Publication No. 60-24975 and Japanese Patent Application Laid-Open No. 61-13 filed separately by the present applicant.
No. 363, etc. are disclosed.

[Problem that the invention seeks to solve]

However, in the past, at least three processors were required, and each part related to these processors was also required.
It is necessary to provide multiple units, which results in a problem that the configuration becomes complicated and expensive.

Means for Solving Problem L] In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in a data processing device that includes two processors and each processor performs the same processing of the same human data in synchronization with each other, a ratte enable signal is sent out from one of the processors prior to sending out data. A timing circuit that delays the load signal and sends out a load signal instructing data loading, and a timing circuit that sends out a comparison end signal indicating the point in time when data loading and comparison based on the load signal in parentheses is completed, and Each piece of data is taken in and held individually, and each data is compared bit by bit until the comparison end signal is generated. If the comparison result does not match, a mismatch signal is sent out and the end is completed almost in synchronization with the comparison end signal. It includes a comparison circuit that sends out a bit signal, and an error detection circuit that sends out an alternating signal in response to a comparison end signal and an end bit signal, and stops sending out the alternating signal in response to a mismatch signal.

[For production]

Therefore, the data sent from each processor is compared bit by bit by the comparison circuit, and the error detection circuit stops sending out the alternating signal due to the mismatch signal sent in response to the mismatch. Based on this, the coincidence or mismatch of each data is indicated, and the two processors perform data processing with high reliability and fail-safe properties.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 2 is a block diagram of the entire configuration, including a processor such as a microprocessor (hereinafter referred to as CPU) 1. jj, fixed memory (hereinafter referred to as ROM) 2.12, variable memory (hereinafter referred to as R
AM) 3.13, input/output circuit (hereinafter referred to as l10) 4,14
, and a data bus (hereinafter referred to as DB) that connects them.
5.15, two systems of data processing circuits are configured, and a clock pulse generator (hereinafter referred to as
CPG) 21, frequency divider (hereinafter referred to as D■) 22, data comparator (hereinafter referred to as DCP) 23, amplifier (hereinafter referred to as A) 24, rectifier circuit (hereinafter referred to as REC) 25, reset circuit (hereinafter referred to as R
ES) 26 etc. are provided, and the CPUs 1 and 11 are provided with RES
26 generated reset pulse (hereinafter referred to as R8P) K!
After being cleared, each instruction stored in ROM2.12 is executed and the required data is transferred to RAM3.12.
13, processes the input data Di given via l104.14, and only the CPU 1 sends out the result as output data Do via l104.

In addition, the clock pulse (hereinafter referred to as C
The CPG21 generates a clock pulse (hereinafter referred to as 4CP) having a frequency four times that of the frequency of DV22K and the frequency of V2 (hereinafter referred to as 2CP). The CPUs 1 and 11 perform the above-mentioned data processing in synchronization with each other based on the 9.2CP provided to the CPU 11.

On the other hand, the address number enable signal (hereinafter referred to as AIJ) from CPU1 and CLK are sent to DCP23.
and each DB5, 15 is given to DCP23.
ALE is connected to DB5, and CPU1.11 is connected to ALE.
．． Initially, R8
DCP23 cleared by P takes in each data of DB5.15 according to ALFJ, and outputs CLK and 4C.
Each bit of data is compared bit by bit using the timing based on P, and while each bit matches, an alternating signal is sent from the output OUT, and if a mismatch occurs in any of the bits, an alternating signal is sent out. It is designed to stop sending signals.

Therefore, the alternating signal obtained from the output OUT of DCP23 is amplified by A24, and then passed through transformer T to REC25.
After converting it to DC, it drives relay RY, and its operating contact RYl is changed to output data D from 104.
By inserting o into the sending path, DCP
When the comparison result by 23 shows a mismatch, the output data DO can be invalidated.

In other words, while each data in DB5.15 is the same,
CPU1. Is the processing status of each time by ji accurate?
, DCP23 continues to send the alternating signal, and relay RY
While the contact RY is on due to the operation of
If an error occurs in any of the processing conditions in CPtJI, 11, any bit in each data in DB5゜15 will not match, and the alternating signal from DCP23 will stop, so the transformer T The secondary output disappears, and the relay RY is restored accordingly, but the transmission of the output data DO is blocked by turning off the contact RYI.

FIG. 1 is a block diagram showing details of the DCP 23, and FIG. 3 is a timing chart showing waveforms of each part in FIG.
MG) 31, a comparison circuit (hereinafter referred to as CMP) 32, and an error detection circuit (hereinafter referred to as EDP) 33, and a 7M
G31 has a shift register (hereinafter referred to as 5RG) 34.35
, CMP32 has 5RG36 with parallel input and series output.
．． 37 and exclusive OR (hereinafter referred to as EXOR) gate 3
8. EDT33 is provided with D-type flip-flop circuits (hereinafter referred to as FFC) 39° and 40, respectively, and 5RG34~
37 and FFC40 were initially shuffled by R8P,
FFC39 is preset by R8P.

In addition, in 7MG31, 5RG34 shifts ALE(c) according to the trailing edge of CLK(a), and shifts load signal (d) as CLK(a) repeats TI-TI. This signal (d) is sent to 5RG35 and also to 5RG36, 37 of CMP 32.
), and 40P(b) becomes P1
.about.Plθ is repeated as a comparison end signal (e).

Therefore, ALE(C) is delayed by the 5RG34 and sent as a load signal instructing the CMP32 to take in data, and this is further delayed to indicate the point at which the CMP32 finishes taking in and comparing the data. This signal is sent as a comparison end signal.

In CMP32, parallel input D of 5RG36.37
The parallel data of DB5.15 connected to each of O to D7 is taken in according to the load signal (d), held individually, and as the load signal (d) disappears, 4
Send each bit as serial data from output QO according to 0P(b), and EX each bit from 5RG36.37.
The signal is applied to an OR gate 38, where the logical value of each bit is compared.

Then, if each bit of each data in DB5.15 equally matches, the output (f) of the EXOR gate 38 is a logical value of "0", but if any bit does not match, then The mismatch signal υAS of "1" indicated by the dotted line is sent out as the output (f).

Yes, parallel input final bit D8 of 5RG36, 37
are connected to the power supply V and the common circuit, respectively, and are represented as "1" and "0". Therefore, until the comparison end signal (8) is generated, the parallel inputs DO to D7 and the corresponding tO to #
After the 7-bit comparison is done, Doujinshi D8 is “1”.
is compared with "0", and any mismatch between them always causes an end bit signal BES to be sent out as an output (f), which is generated in synchronization with the comparison end signal (e).

On the other hand, FFC39 of BDT33 has υ output (9) set to "1" by presetting by R8P,
The output color of FFC40) is cleared by R8P.
As the OJ becomes fi, the comparison end signal (e) is given to the clock input CK of the FFC39, and the output (f) is given to the doujinshi CK of the FFC40 at the same time.
data is "0", and FFC40 is doujinri is rl
J, the comparison end signal (6) and output (
According to the leading edge of f), FFC39 is reset, FFC
40 is set individually, the output (g) is "0", the output (g) is inverted to "1", and the next comparison end signal (e
) and output (f) occur, it is further inverted to the opposite state, and this inversion is repeated each time the comparison end signal (e) and output (f) occur.

Therefore, the data is sent from the CPUs 1 and 11 to the DB 5.

15, or ROM2.
12, read from RAM 3, 13, DB5゜15
The output (
company) becomes an alternating signal that repeats "1" and "o", and
24, thereby causing relay RY to operate.

In contrast to the above, if any focus in each data of DBS#15 does not match, the mismatch signal UAS is generated before the end focus signal BES is generated, and this causes 0 during setting.
FF040 must be reset, at this time FFC
39 is being reset and the outputs (g) and (h) are both V.
ζ becomes "0", and from this point on, the output does not become "1" but is fixed to rOJ, and transmission of the alternating signal is completely stopped.

Furthermore, if the FFC4Q is being reset when the mismatch signal UAS occurs, the FFC39 is set and the output (g) is 11'', and the FFC40 changes to the set state and outputs (h ) is set to "1", from this point forward both FFCs 39 and 40 maintain the set state, fix the output (h) to f:1-IJ, and stop sending out the alternating signal.

Therefore, if any bit in each data given via DB5.15 is inconsistent, the output (h) will be "
0'' is fixed to ``l'', the alternating current component disappears, and relay RY is restored.

In addition, if an abnormality occurs in any of the DCP23, or
Even if an abnormality occurs in any of A24 to relay BY, the contact RY 1 is always turned off and the output data Do' is invalidated, so complete fail-safe performance is achieved.

Alternatively, in FIG. 1, the TMG31 may be configured with a counter, etc., and the CMP32 may be configured with a latch circuit, a parallel comparison circuit, etc. The delay time of TMG31 is C
Various modifications can be made, such as being determined according to the configuration of the MP32 and the number of bits of data.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a data processing device with high reliability and fail-safe properties is realized with a simple and inexpensive configuration using two CPUs, and is used for railway signal control. Remarkable effects can be obtained in various types of data processing that require high reliability and fail-safe properties.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, in which Figure 1 is a block diagram of a data comparator, Figure 2 is a block diagram of the entire configuration, and Figure 3 is a block diagram of a data comparator.
3 is a timing chart showing waveforms of various parts in the figure. 1111...CPU (processor), 4゜14-
---Ilo (input/output circuit), 5, 15. DB (data bus), 21. ...REG (rectifier circuit), 31#.
Pot ITMG (timing circuit), 32...CMP
(specific blowing circuit), 33...EDT (error detection circuit), 34-37...SRG (shift register)
, 38-... EXOR (exclusive OR) gate, 3
9.40...FFc<, flip-flop circuit), ALE...address latch enable signal, CLK. 4CP---Clock bus/l/s, (d)---e
+- code signal, (e) life...comparison end signal, BgS
... End bit signal, UAS ... Mismatch signal.

Claims (1)

[Claims] In a data processing device comprising two processors, each of which performs the same processing of the same input data in synchronization with each other, a latch enable signal is transmitted from one of the processors prior to data transmission. a timing circuit that sends out a load signal that instructs the loading of the data to be delayed and sends out a comparison end signal that indicates the point in time when data loading and comparison based on the loading signal are completed; and each of the processors in response to the loading signal. Each piece of data sent out from the above is taken in and held individually, and each data is compared bit by bit until the comparison end signal is generated, and when the comparison result does not match, a mismatch signal is sent and the comparison end signal is generated. and an error detection circuit that sends out an alternating signal in response to the comparison end signal and the end bit signal and stops sending out the alternating signal in response to the mismatch signal. A data comparator for a data processing device, comprising: