JPS6040033B2 - cathode ray tube display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray tube display device, and particularly to a cathode ray tube display device, which is widely used as an important device that forms a contact point between an operator and a computer system. The present invention relates to a cathode ray tube display device.

Generally, in order to display graphics on a cathode ray tube without flickering, it is necessary to repeatedly apply the same signal at a rate of 40 to 6 sub/second, but the external input signal can only be applied once.

Therefore, a memory circuit is required that can store a one-time input and provide a repeated output. For this purpose, as shown in FIG. 1, the display screen is electrically divided into an nxm grid, and memory circuits corresponding to the grid points on a 1:1 basis are prepared, and figures are displayed according to the contents of the grid points. In this case, if you try to display the contents of a certain arbitrary point, the readout time that can be allocated to the memory circuit will be a very short time.For example, in the case of a general-purpose television receiver, one row is 63.5 This is Buddha S. If you try to display 512 points/example within this time, the Jikian shoes b assigned to one point will be tb = 63
．． Tsubo S/512 points = 124 nS/point. Therefore, the memory circuit must be configured using a memory element that can be read within 124 nS.

This puts a limit on the number of lattice points and means that even if a sufficiently high-speed memory element existed, it would be extremely expensive.

The purpose of the present invention is to solve the above-mentioned conventional problems.
In order to make the reading time of a memory circuit for displaying a figure longer than the display time of one point constituting the figure, memory elements are connected in parallel to freely change the contents of grid points on the screen. The object of the present invention is to provide a cathode ray tube display device that can perform the following functions.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a block diagram of a cathode ray tube display device. In FIG. 2, an interface section 2 with a computer system is connected to a control section 1, and these controller 1 and interface section 2 are connected to a keyboard. An interface section 3, a memory circuit control section 4, and a memory readout circuit 7 are connected. The memory circuit control section 4 is connected to the memory circuit section 5 and the memory readout circuit 7 . A signal level converter 8 is connected to the memory output circuit 7, and a cathode ray display section 9 consisting of 14-inch cathode ray tubes with n=256 points and m=240 is connected to the signal level converter 8. Since n=256 points are assumed to be 32×8, 8 lattice intersection points are considered as one unit. In other words, 256 points with 8 bits is
It can be selected, but it is divided into 3 low order bits and 5 high order bits. Furthermore, the capacity of the memory circuit section 5 is 256×240=6
It is 1440 bits. A memory circuit 5 is connected to the memory circuit control section 4, and this memory circuit 5 is connected to the timing generation section 6 and the memory readout circuit 7. FIG. 3 shows a detailed explanatory diagram of the main part. In FIG.
~A8 is supplied to the signal switching circuit 4a and the selection circuit 4b of the storage control unit 4, and a bit write signal (BITWT signal) for changing 1 bit unit or 8 bit unit is supplied.
is supplied.

4c is a storage control unit 4 that stores the address of the point to be changed;
The address register 4c is connected to the memory circuit 5, and the memory elements 5a to 5h are connected in parallel to the memory circuit 5.

4d is a storage circuit of the storage control unit 4 that stores the contents to be changed, and this storage circuit 4d stores the storage control unit 4 in units of 1 bit.
This signal switching circuit 4c is further connected to the data register 4f of the storage control unit 4, and
It is connected to the memory circuit 6.

Further, 7a is an output register which is a part of the storage logic output circuit 7, and signals 8 to 8 of this output register 7a are connected to the signal switching circuit 4a through the B route.

In the cathode ray tube display device having the above configuration, input signals input from the computer system interface section 2 and the keyboard interface section 3 are controlled by the controller 1 and sent to the storage circuit control section 4 via route A. The signal is supplied and written into the memory circuit section 5.

The output of the memory circuit section 5 is read out by a memory reading circuit 7, converted by a signal level conversion section 8 to a signal level suitable for the cathode ray display section 9, and sent to the cathode ray display section 9. In this case, the signal transmission from the memory readout circuit 7 to the cathode ray display section 9 is carried out regularly at a ratio of 6 to 6 according to the timing of the timing generating section 6, and a display screen with almost no flicker is obtained. Further, since a signal route B from the memory logic output circuit 7 to the memory circuit control section 4 is also prepared, the contents read by the memory circuit control section 4 can be written to the memory circuit section 5 again. Next, a method for changing the contents of the memory circuit section 5 will be explained using FIG.

The contents of the memory circuit section 5 can be changed in units of 8 bits,
There are two types of changes in 1-bit units, which are selected by the bit write signal controlled by the control unit 1 in FIG.
First, the case where the bit write signal is "H", that is, the change in units of 8 bits will be explained. Signals A, -A8 of the A route become output signals of the signal switching circuit 4a when the bit write signal is "H", and the bit write signal is also input to the selection circuit 4b at the same time. The eight signal lines which are the outputs of the selection circuit 4b all become "H", and the output signals of the signal switching circuit 4e, that is, the signals A, . . . of the A route, are obtained and stored in the data register 4f. In addition, the 8-bit memory circuit section 5 is provided with a data register 4 by a read/write control signal R/W.
The output of f is written, and its address is determined by the upper 13 bits of address register 4c. Next, the memory circuit section 5 specified by all bits of the address register 4c
A case will be explained in which the contents of the data are changed in units of 1 bit. The address register 4c stores the address for one grid point on the screen to be changed, and the output of the upper 13 bits of the address register 4c and the control signal R/
By W, 8-bit data is read from the storage circuit section 5 and stored in the output register 7a. The output signals B to & of the output register 7a are supplied to the input side of the signal switching circuit 4a through the B route, and since the bit write signal is "L", the signal switching circuit A B route signal is obtained as the output signal of 4a. On the other hand, the output signal of the lower three bits of the address register 4c is supplied to the input side of the selection circuit 4b together with the bit write signal, and since the bit write signal is "L", any one of the output signals of the selection circuit 4b The book becomes “L”. The output signal of the selection circuit 4b indicates the content of change when one bit is changed, both directly and via an inverting circuit. Along with the output signal of the storage circuit 4d and the output signal of the signal switching circuit 4a, the signal switching circuit 4
is supplied to the input side of e. The output signal of the signal switching circuit 4e is stored in the storage circuit 4d only for the "L" bit of the selection circuit 4b.
It becomes the output signal (B route signal) of the other signal switching circuit 4a, is stored in the data register 4f, and is written to the storage circuit 5 specified by the upper 13 bits of the address register 4c by the control signal R/W. . As a result, the one grid point on the screen to be changed is changed.
As described above, according to the cathode ray tube display device according to the present invention, the contents of the address to be changed in the memory circuit section 5 are first read out in units of 8 bits, and the data of only 1 bit out of the 8 bits to be changed is read out. By changing the contents of the data register and writing to the same address as the read address, the display time of the grid points on the cathode ray tube display section can be
It is possible to freely change the contents of a lattice point without changing the contents of other lattice points while using a memory circuit section for a memory element that requires a long loading time.

Furthermore, since the memory elements 5a to 5h are connected in parallel to the memory circuit section 5, the read time is 8×124 nS=99
or S. Therefore, the reading time from the memory circuit section 7 is longer than the 124 points/point of the slave described above. It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that the present invention can be applied regardless of the number of lattice points or the circuit configuration. As explained above, the present invention is capable of arbitrarily changing the content of one point without limiting the number of grid points by connecting the memory elements of the memory circuit section in parallel, and is inexpensive and highly efficient. have an effect.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram in which the display screen of a cathode ray tube is electrically divided into a grid pattern, FIG. 2 is a block diagram showing an embodiment of the cathode ray tube display device according to the present invention, and FIG. It is a detailed explanatory diagram of the section. 1...Control unit, 2, 3...Interface unit, 4...
...Storage control unit, 4a...Signal switching circuit,
4b...Selection circuit, 4c...Address register, 4d...Storage circuit, 4e...
...Signal switching circuit, 4f...Data register,
5... Memory circuit section, 5a to 5h... Memory element, 6... Timing generation section, 7...
Memory reading circuit section, 8...Level conversion section, 9...
...Cathode ray display section. Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. A storage circuit control section to which an input signal from an external device interface section is controlled and supplied by the control section, and an output signal of this storage circuit control section is written, and the lattice points of the cathode ray display section are a memory circuit section that corresponds in a 1:1 ratio to the memory circuit section, a memory readout circuit from which an output signal of the memory circuit section is read out and supplied to the memory circuit control section, and an output signal from the memory readout circuit is supplied; Moreover, the screen is electrically divided into n×m grids, and has the cathode display section that displays figures according to the contents of the grid points, and the memory circuit control section: controls the output of the memory readout circuit. a data register and an address register for storing the content and address of a grid point to be changed; a control signal generating means for representing a change in the grid point data; and a means for receiving the input signal and an output signal from the memory readout circuit and responding to the control signal. a switching circuit that outputs the input signal or a signal from the memory/read circuit; and a switching circuit that outputs the input signal or a signal from the memory/read circuit; A cathode ray tube display device comprising stored data and means for changing the data.