JPS5995589A - Crt display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a CRT display device that displays dot-structured characters or figures on a CRT using a scanning method.

In particular, the present invention relates to display control for efficiently displaying text and graphics.

<Prior Art> A general memory method for storing the content to be displayed on a CRT display device includes a memory that assigns and stores character codes to character information, and when displaying, a character generator (character generator)
It is equipped with a code refresh method that accesses and converts it into an actual character dot pattern and displays it, and a memory that stores bit patterns that correspond one-to-one to the displayed dot information, and when displaying, bits from that memory are stored. There are two methods: a bitmap method that directly displays the pattern.

When image information such as figures and graphs is to be displayed, the former code refresh method can only display character information, so the latter bit map method is used.

However, there are cases where you want to display character information in addition to image information, and if you try to display character information using the bitmap method, it requires a large amount of memory compared to the code refresh method. When displaying one character, the bitmap method requires 72 bytes, while code refresh requires only 2 bytes.

Therefore, when displaying characters using the bitmap method, it takes a lot of time to rewrite (refresh) the memory, and compared to the code refresh method, it takes a lot of time to display characters. Since it is necessary to provide a character spacing of about 1 to 4 dots between characters, the control process for sending character information to the bitmap memory becomes complicated, and this process requires a long time. However, the above processing is normally performed by the main processor, but in this case, the processor is occupied for a long time, causing a delay in other processing.

On the other hand, one method to solve the above problem is to provide two types of memory: a memory that stores the character code described above and a memory that stores image information such as graphics, and a code refresh system and a bitmap system. It has been proposed to configure these independently.

This stores character information in a memory that stores character codes, and stores image information in a bitmap.

The image information stored in the bit map stored in the memory is directly converted into a video signal and displayed, and the character code is converted into a character pattern by a character generator and then displayed.

However, this device requires two types of fresh memory to be installed independently, making it larger and larger.
This was inevitably expensive, and could hardly be called efficient display control.

<Purpose> The present invention uses one refresh memory to display text information and image information, and moreover, compared to the above-mentioned bitmap method, the memory capacity can be reduced, making it more compact and inexpensive. This is what has been realized.

<Embodiment> To explain the specific configuration of the present invention, FIG. 1 shows a control circuit configuration, 10 is a processing device, which outputs character code information and graphic information (code information), and also outputs character mode signals. CHARA and graphic mode signal G
RAPH is output according to the display information.

Reference numeral 21 denotes a CRT controller, which stores character information supplied from the processing device 10 in the refresh memory 22, develops graph ink information (code information) into desired pattern information, writes it into the refresh memory 22, and displays it on the CRT. In the second cycle, the refresh memory 22 is accessed and display data is read out in synchronization with the last scan of the CRT.

The CRT controller 21 has a concrete configuration shown in FIG. 2, and outputs a horizontal scanning synchronization signal H8YNC and a vertical synchronization signal VSYNC, and also outputs an address signal L1 of the refresh memory 22 and character pattern generation. Line counter (CG) 23 address control
LC) 26 control signal L2 is output.

As mentioned above, the fresh memory 22 has a storage capacity for at least one screen, and in character mode it stores character codes consisting of 16 bits, and in graphic mode it stores image patterns as one block of 16 bits. .

Therefore, when the CRT controller 21 receives information such as a code and the size of a circle regarding 6 yen from the processing device 1o in the graphic mode, it refreshes the bit pattern of the specified 6 yen in units of 16 bits. This is to write to the memory 22.

The bit pattern in the graphic mode is directly supplied from the refresh memory 22 to the multiplexer 24, and the character code in the character mode is supplied from the refresh memory 22 to a character pattern generator (CG) 23, which then supplies the character code to the character pattern generator (CG) 23. character patterns are supplied to the multiplexer 24.

The multiplexer 24 receives a graphic mode signal G.
RAPH and a character mode signal CHARA are input as control signals, and the image pattern is enabled in the graphic mode and the character pattern is enabled in the character mode.

25 is a parallel-to-serial conversion circuit which serially outputs the image or character pattern data selected by the multiplexer 24 as a video signal to the CRT driver.

On the other hand, the timing control and control configuration includes an fc pulse generator 28 that generates a reference pulse fc in the character mode and a reference pulse fi in the graphic mode (the frequencies of fc and fi have a relationship of fc:>fi). fi pulse generator 29 that generates a fi pulse generator 29, which becomes effective in the character mode and generates a reference pulse fc from an OR gate 32 to a frequency dividing circuit 2.
7 and the control gate 31 which is enabled in the 80° graphic mode and supplies the reference pulse fi to the frequency divider circuit 27 and the parallel-serial converter circuit 25 from the OR gate 32; It is mainly constituted by a circumferential circuit 27.

The frequency dividing circuit 27 receives a graphic mode signal GRAP.
H and the character mode signal CHARA are input as control signals, and in the character mode, the reference pulse fcme2
CRT controller 21 outputs one pulse every 8 pulses.
Also, in the graphic mode, a reference pulse f i (7) 1 (one pulse every three pulses is output to the clock terminal CLK of the CRT controller 2I).

The reason why the frequency is divided every 28 pulses is that the pattern configuration stored in the character pattern generator (CG) 28 has a character width of 2.
There are 4 dots and 4 dots between characters, and this corresponds to this. Therefore, the C, 8-, T controller 21 sequentially accesses the character codes in the refresh memory 22 at the timing input to this clock terminal CLK.

Furthermore, the reason why the frequency is divided every 16 pulses is because the graphic pattern is stored with one block as 16 bits, and the CRT controller 21 sequentially accesses the graphic pattern in the refresh memory 22 at this timing.

Here, the point in which reading of the refresh memory 22 is controlled by switching between the reference pulses fc and fi in the character mode and the graphic mode will be explained in more detail.

When displaying character patterns such as kanji, usually 24
Although it is displayed in a x24 matrix pattern, this matrix pattern is relatively large, and the number of characters that can be displayed per line is limited due to the display screen size.

Therefore, as shown in FIG. 3(A), by increasing the dot density in the horizontal direction relative to the dot density in the vertical direction, the number of displayed characters per line can be increased.

This figure 3 shows an example of the display of the characters "Kan", which is compressed in the horizontal direction.

Under such display control, a problem arises in that when image information such as graphics is displayed, the desired graphic pattern cannot be obtained. In other words, a perfect circular figure is displayed as an ellipse,
The figure becomes an isosceles triangle, as shown in () in Figure 3, which displays an equilateral triangle figure.

For this reason, in the case of graphic ink display, it is necessary to make the horizontal and vertical dot densities approximately equal to display as shown in FIG. 3(C).

Therefore, in the graphic mode, the readout cycle of the refresh memory is switched to a cycle (clock) different from that in the character mode to change the horizontal dot density between the graphic mode and the character mode, so that the reference pulses fc and fi mentioned above are changed. This is what we have in place.

In this case, the frequency of the fc pulse is higher than the frequency of the fi pulse, and the following relationship exists.

, + 1Nh lX
-= +Ts i = Nhc The rask scanning time is almost the same in any mode, and in order to change the display dot density, it is necessary to change the readout time of the refresh memory.

The size of a CRT screen is generally 4 horizontally and 3 vertically, so Nhi = "Nv."

Nvo Number of vertical dots Nhc 3 (H + (Tsc - Tsi)) Since Tsc and Tsi are almost equal, for example, in character display mode 1, 1I48 dots (row 41
If the reference clock is approximately 38 MH2 on a display screen of dots (24 character lines), the relationship is approximately 32 MHz in the graphic display mode.

Next, the specific configuration of the CRT controller shown in FIG. 2 will be explained.

FIG. 2 shows a block diagram of the controller 21, and 40 is a CHARA signal.

By outputting one of the GRAPH signals,
This is a horizontal address counter circuit whose count number is initialized, and counts the timing pulses from the frequency dividing circuit 27.

The above counter circuit 40AjJ count value is the number of horizontal dots, that is, 41 counts (row 4) in character display mode.
When one character is displayed), a carry signal is supplied to the H5YNC generation circuit 44 to control the horizontal return line.

Further, in the graphic display mode, the counter circuit 40 counts 60 (the number of dots on the l line based on the frequency i of fi), and derives a carry signal as described above.

A counter 41 counts the carry signal from the circuit 40 to obtain the horizontal retrace time.

42 is a vertical address counter circuit, in this example 72
When the count is 0, the carry signal is sent to the VSYNC generation circuit 4.
5 to perform vertical retrace control. 43 is a counter for obtaining the vertical retrace time.

46 is an address signal generation circuit for the refresh memory 22, which outputs the address of the refresh memory according to the count value of the circuits 40 and 42.

47 is a circuit that controls the line counter (LC) 26, which outputs a count pulse to the line counter (LC) circuit 26 at each timing of H5YNC of the horizontal address counter (which becomes the line address of the character pattern), and a vertical address counter. Each time the circuit 42 counts one row, it outputs a reset signal for resetting the line counter (LC) circuit 26.

The operation of the CRT display device of the present invention having the above configuration will be explained.

Character mode In the character mode, the character mode signal CHARA is output from the processing device 1o, and the frequency dividing circuit 27. of FIG.
It is supplied to the control gate 3o and the multiplexer 24. Therefore, the reference pulse fc is supplied to the frequency dividing circuit 27 via the get 30, and the frequency dividing circuit 27 supplies one pulse to the CRT controller 21 every 28 pulses.

The horizontal address counter circuit 40 of the CRT controller (see FIG. 2) is initialized to a counter that counts 41 pulses by the character mode signal, and counts the pulses from the frequency divider circuit 27. Then, the corresponding address data of the refresh memory 22 is read out based on the horizontal address counter circuit 40 and the vertical address counter circuit 42, and the character pattern generator (CG) 23 reads out the corresponding address data of the refresh memory 22.
supplied to

This character pattern generator 23 is connected to the refresh memory 22.
A corresponding pattern is selected based on the 16-bit character code output from the line counter circuit 2.
6 to the multiplexer 24 according to the line address. At this time, the multiplexer 24 selects the character pattern generator 23 side.

Therefore, the character pattern is supplied via the multiplexer 24 to the parallel-to-serial conversion circuit 25, where it is serially output as a video signal in synchronization with the reference pulse fc. In this case, as shown in FIG. 3(A), the display is a compressed pattern in the horizontal direction compared to the vertical direction.

At the time of graph ink mode In the graphic mode, the graphic mode signal GRAPH is output from the processing device IO, and the frequency dividing circuit 2 of FIG.
7. Control gate 31. A multiplexer 24 is provided.

Therefore, the reference pulse fi is supplied to the frequency dividing circuit 27 through the gate 31, and one pulse is supplied to the CRT:1 controller 21 for every 16 pulses of the frequency dividing circuit 27Lt.

The horizontal address counter circuit 40 of the CRT controller (see FIG. 2) is initialized to a counter that counts 60 pulses using the character mode signal, and counts the pulses from the frequency dividing circuit 27.

Then, based on the horizontal address counter circuit 40 and the vertical address counter circuit 42, the refresh memory 2
The corresponding address data of 2 is read out, and this image pattern is supplied to the multiplexer 24. At this time, the multiplexer 24 directly selects the refresh memory 22 side.

Therefore, the image pattern is transmitted to the multiplexer 24.
The signal is supplied to the parallel-to-serial conversion circuit 25 via the reference pulse fi, where it is serially outputted as a video signal in synchronization with the reference pulse fi.

In this case, since the frequency of the reference pulse fi is set lower than the frequency of the reference pulse fc as described above, the display is displayed at approximately the same intervals both horizontally and vertically, as shown in FIG. 3(C). The correct shape is displayed.

Note that although the above embodiment shows a configuration in which the reference pulse generators fc and fl are provided separately, f
Of course, it is also possible to adopt a configuration in which c and fi are frequency-divided.

<Effects> As described above, the CRT display device of the present invention can efficiently display character information and image information using a single fresh memory, and has advantages over the bitmap method described above. Not only can the memory capacity be reduced, but also one fresh memory can be shared for text information and image information, so the device can be made more compact and inexpensive.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a control configuration of a CRT display device of the present invention, FIG. 2 is a block diagram showing a specific configuration of the CRT controller shown in FIG. 1, and FIG. 3 is a diagram showing an example of display. 10; Processing device, 21: CRT controller, 22
: Refresh memory, 23: Character pattern generator, 2
4: multiplexer, 25: parallel-serial converter, 26: line counter, 27: frequency divider, 28: reference pulse fc generator, 29: reference pulse fi generator, 30 and 3I: control gate. Agent Patent Attorney Aihiko Fukushi (and 2 others) (C) No. 3 r4 49 1;

Claims (1)

[Scope of Claims] 1. In a CRT display device which has a display screen refresh memory and displays characters, figures, etc. by a scanning method, 1. the refresh memory common to character code information and image pattern information; A character pattern generator for converting the character code information read from the refresh memory into a character pattern, and a parallel controller for outputting the character pattern generator from the character pattern generator and the image pattern read from the refresh memory as a video signal. - a control circuit for controlling the introduction into the serial conversion circuit; and the parallel-to-serial conversion circuit; a first read timing control means for reading out image pattern information in the refresh memory in response to a graphic mode signal; and a second read timing for reading out image pattern information in the refresh memory using a second reference pulse signal having a lower frequency than the first reference pulse. control means, and controls the first read timing control means, the refresh memory, the character pattern generator, and the parallel-to-serial conversion circuit based on a character mode signal instructed and output from a processing device connected to the CRT display device. The second read timing control means, the refresh memory, and the parallel-to-serial conversion circuit are operated based on the graphic mode signal from the processing device to display character information and image information. A CRT display device characterized by: