JP3115634B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device using a display such as a CRT or LCD used in a computer or various terminal devices, and more particularly to an image display device using a parallel data input / output type frame memory. The present invention relates to an image display device which reads data as parallel data and sequentially transfers the data to a display.

[0002]

2. Description of the Related Art In an image display device (graphic display device) for displaying characters and patterns on a display such as a CRT (cathode ray tube) or LCD (liquid crystal display), an arbitrary portion (region) of a display screen is selected. In order to perform special processing on the area, for example, erasing display data or replacing the display data with other display data, the following various methods have been used in the conventional image display apparatus.

(1) With the frame synchronization signal as a starting point, in the vertical direction of the screen, the count value n1,
Using a divided signal based on n2 and using a divided signal based on the count values n3 and n4 of display data (characters) in the horizontal direction, a rectangular area as shown by hatching in FIG. 12 is designated ( Japanese Patent Publication No. 2-176695).

(2) Starting from a frame synchronization signal, using divided signals based on the count values t1, t2, t3, and t4 of the timer in the vertical and horizontal directions of the screen in the same manner as in (1). A rectangular area as shown by hatching in FIG. 12 is designated (see the same publication).

(3) A memory for setting a window start (designated area start) position and a window width of each horizontal line is provided, and an area having an arbitrary shape as shown in FIG. No. 63-27954).

(4) There are a plurality of frame memories each having a storage area for image data and its mask information or priority display information for one pixel address, and a plurality of graphic images are synthesized and displayed according to the priority display information and mask information (particularly). See JP-A-2-146092).

(5) In addition to a storage area for image data (frame memory), a storage area for width data based on the number of pixels in the horizontal direction is provided to perform a shadowing process as shown in FIG. 226297).

(6) In a character display method using a character generator, mask information, priority display information, and the like are provided as attributes in units of characters.

(7) A plurality of means for moving out display data are provided, and in accordance with a predetermined priority, the movement of other display data is prohibited so that only one display data is displayed. The replaced area is replaced with other display data (see Japanese Patent Application Laid-Open No. 2-293792).

[0010]

However, the above-mentioned (1) and (2) in such a conventional image display device.
In the method described above, since only a rectangular area can be specified, a graphic area including a curve cannot be specified.

In the method (3), it is necessary to provide a memory for setting the start position and width of the designated area for each horizontal line, and the memory capacity increases as the number of horizontal lines and the number of designated areas increase. However, the scale of the hardware becomes large.

In the method (4), since the area can be specified in units of one pixel, the degree of freedom of the area specification is maximized. However, since the mask information and the priority display information are provided for each pixel, the memory capacity is enormous. In other words, the scale of the hardware becomes larger than in the case of the method (3).

In the method (5), since there is only one type of width specification in the horizontal direction, there is no degree of freedom in area specification, and it can be applied only to specific applications such as shadowing processing. In the method of (6), since the area is specified in character units,
As in the methods (1) and (2), the area cannot be specified by a graphic including a curve.

The method (7) is an effective method in the case of color display. However, in the case of monochrome display, it becomes the same as a display obtained by simply performing a logical sum synthesis of a plurality of display data. That is, if there is only one combination of the display data indicating the inside of the designated area and the outside of the designated area (in the case of monochrome display), there is only an effect of erasing or replacing the data in the area, and the display such as fill synthesis is not performed I can't. In other words, it can only be expressed as a silhouette.

As described above, in the conventional display device, an arbitrary region of the display screen is selected, and the degree of freedom in performing a special process on the selected region and an increase in hardware such as a memory capacity are increased. There was a problem.

The present invention has been made in view of such a conventional problem, and an image display apparatus which reads a plurality of image data from a frame memory of a parallel data input / output system, synthesizes the data, and sequentially transfers the read image data to a display device. It is an object of the present invention to minimize the increase in the capacity of the frame memory and display an image on which any special processing has been performed on an arbitrary portion of the display screen.

[0017]

In order to achieve the above object, the present invention provides an image display apparatus as described above, wherein a certain area is included in attribute data set for each character of image data read from a frame memory. Means to have a combination that indicates the end of the area and a combination that indicates the end of the area, and decodes the two attribute data, selects an arbitrary area on the display screen, and erases or fills the selected area with data. And means for continuously performing operations for performing such processing in synchronization with the display cycle.

[0018]

According to the image display device configured as described above, attribute data having a combination indicating an arbitrary designated area and a combination indicating the end of the area is set for each character of the image data read from the frame memory. By decoding the two attribute data, a specified area of the display screen is selected, and operations such as data erasing and filling are performed on the selected area continuously in synchronization with the display cycle. Therefore, it is possible to display an image subjected to special processing on an arbitrary portion of the display screen while suppressing an increase in the capacity of the frame memory.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 shows a display example according to the embodiment of the present invention .
As shown in FIG. 5 (C), this example is a synthesis of monochrome display, and the display of (A) is filled with a figure surrounded by black lines of (B). If the display by the logical sum synthesis is to display both black parts as in (D), it is not possible to paint with white parts as in (C).

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Although a display such as a CRT and an LCD is not shown, the image display device of this embodiment is configured to include the display.

In FIG. 1, a CPU 1 is a central processing unit for controlling the entire apparatus, and executes a program stored in a ROM (Read Only Memory) 2.
The ROM 2 also stores graphic codes (pattern data) for graphic display in addition to the programs.

GC. RAM (random access memory for graphic code) 3 and CC. The RAM (random access memory for character code) 4 includes upper bytes D8 to D8 of the CPU data bus 5, respectively.
CPU 15 is a frame buffer (video RAM) connected to D15 and lower bytes D0 to D7.
M3 and M4 are also used as a work area and a stack area.

On the other hand, the display control circuit 6 responds to the timing signal generated by the timing generator
It has a function of repeating a cyclic (regular) display operation asynchronously with PU1.

Therefore, GC. RAM3 and CC. RA
The access of M4 has priority in the display control circuit 6,
When U1 rewrites the display data or accesses the work area or the stack area, the timing generator 7 controls the display control circuit 6 to perform the access in the non-access state timing (“cycle steal access control”). ). In this embodiment, a graphic display and a character display are superimposed and displayed as follows.

[Graphic Display] The display control circuit 6 mainly comprises a display address generator. CPU1
Supplies a display start address,
Set the number of characters in the horizontal and vertical directions. These set values are also sent to the timing generator 7,
The timing generator 7 generates various synchronization signals for display according to those set values.

The CPU 1 sends a graphic code from the ROM 2 to the GC. The data is transferred to a predetermined address of the frame buffer in the RAM 3. In the case of graphic display, GC. The data written in the RAM 3 becomes display data as it is. The display control circuit 6 operates according to a frame synchronization signal generated by the timing generator 7.
The graphic display addresses GA0 to GA14 are output on the graphic display address bus 12. The data (graphic code) according to the address is GC. RA
It is output from M3 and loaded into the synthesis circuit 11.

[Character Display] The CPU 1 sets a display start address, the number of characters in the horizontal direction, the number of characters in the vertical direction, and the like for the display control circuit 6. The set values are also sent to the timing generator 7, and the timing generator 7 generates various synchronization signals for display according to the set values.

The CPU 1 converts a character code into a GC. The data is transferred to a predetermined address of the frame buffer in the RAM 4. The display control circuit 6 outputs the character display addresses CA0 to CA14 on the character display address bus 13 and simultaneously outputs the raster addresses RA0 to RA2 according to the frame synchronization signal generated by the timing generator 7.

In this embodiment, a character code having a 16-bit width is used. Since the RAM 4 has 8-bit data input / output, the display control circuit 6
When reading a character code for a character, the address is incremented so that the lower 8 bits and the upper 8 bits are read out continuously, and are latched by the lower latch 14 and the upper latch 15, respectively.

As attribute data for designating the attribute of the character in the 16-bit character code, 3
Bits are provided, and the remaining 13 bits are CG. R
OM (character generator) 8 is set. At the same time, the raster addresses RA0 to RA2 are set, and data (display data) according to those codes and the raster addresses are stored in the CG. The output from the ROM 8 and the synthesis circuit 1
Loaded into 1.

The two kinds of display data loaded in the synthesizing circuit 11 in this way are synthesized by the OR operation of the synthesizing circuit 11. Then, the combined display data is transferred to a display (not shown). In the case of a display using a CRT, parallel-to-serial conversion is necessary. In the case of using a line scan type dot matrix LCD,
In some cases, it is necessary to output the upper four bits and the lower four bits separately, but they are not directly related to the present invention and will not be described.

Next, the operation of the synthesizing circuit 11 will be described. FIG. 2 shows the configuration of the synthesis circuit, and FIGS. 3 to 8 show timing charts. In these figures, FIG. 3 and FIG.
4, 5 and 6, FIGS. 7 and 8 are originally
It is one figure, but for the sake of illustration, it is divided into two figures.
Is shown. The basic display timing of the examples are as follows, there are three types of clock pulses CLK1, CLK2 and CLK3 shown in FIGS. 3-8. One cycle of the clock pulse CLK3 is a display timing for one display data (1 byte) in the horizontal direction, and one cycle of the clock pulse CLK2 is a display timing of one dot.

An FLM (first line marker) is a timing pulse indicating one section of the screen. The timing pulse FLM is output from the timing generator 7 shown in FIG.
Is output, the display control circuit 6 outputs the display start address to capture the first display data, and sequentially repeats the display operation.

In this embodiment, memory access is performed by cycle stealing as described above .
As shown in FIG. 8 , the CPU 1 can access while the clock pulse CLK3 is "L", and while the clock pulse CLK3 is "H", the display control circuit 6
Is assigned to a period during which display data is transferred to the display. Switching of each address is performed by multiplexers 18 and 19 as shown in FIG.

At the rise of the clock pulse CLK3, the display address becomes GC. RAM3 and CC. The graphic code and the character code are set in the RAM 4 and output. In the case of a graphic code, the data is sent as it is to the synthesizing circuit 11, but the character code is a CG. ROM
8 and the currently set raster address R
The display data according to A0 to A2 is sent to the synthesis circuit 11.

CG. ROM8 or GC. The display data output from the RAM 3 is output from the synthesizing circuit 11 at the falling edge of the clock pulse CLK3. SR (parallel in serial out shift register) 25 and 2
6 is loaded. Clock pulse CLK3 is supplied to SP. SR22 and the serial signal input terminal of F.R. It is also input to a clock input terminal of an F (flip-flop circuit) 23 and the like.

The shift clock (27) synchronized with the clock pulse CLK1 generates the PS. SR25, 26 and SP. SR
28, the 8-bit display data is shifted according to the shift clock (27), and SP. The output data of SR28 becomes a video output. The above operation is when merely a graphic display and character display of the OR composite display as shown (D) in FIG. 15.

Next, a description will be given of the operation of the composite display of the character display with an arbitrary pattern shape. As the 3-bit attribute data in the character code, there are paste ON (29) and paste END (30), which are data for specifying a fill-in composite display area.

In the case of performing the composite display shown in (C) as if the circular figure shown in (B) of FIG . 15 is pasted on the display of (A), the paste method as a hardware method is as follows. The display data in the designated area on the side to which the image is attached may be erased (set to "0"), and the display data and the circular figure may be combined and displayed.

In this embodiment, the above operation is sequentially performed in synchronization with the display timing. Normal (CRT also LC
D), the display data is sent in the order of one line horizontally from left to right on the screen, and the entire screen is displayed by sequentially displaying the display lines from top to bottom. Therefore, the start and end of the painting operation are repeatedly performed for each line, and the painting composite display according to the two-dimensional area designation is realized.

Here, the operation of pasting the diamond figure shown in FIG. 9 will be described. At first,
The operation will be described focusing on the display line L1. The diamond-shaped figure in FIG. 9 is composed of 19 characters as shown in FIG . Characters related to the fill synthesis area in the line L1 of interest are: ,,,
It is. The attribute (attribute data) of each character is set as follows.

Character paste ON Paste END ON OFF ON OFF ON ON OFF OFF (ON: “H”, OFF: “L”)

The characters on the left side of the display line L1 are pasted ON (29) and pasted END.
Since both (30) are OFF, the graphic data erasing signal (31) maintains the state of the high level "H", and a simple logical sum display is performed.

FIGS. 3 and 4 show how the character begins to be painted. Since the attribute data is included in the upper byte of the character code / latch data, the paste ON (29) becomes "H" at the timing shown in FIG. In response, the paste ON-1D2 (33) becomes "H" at the falling edge of the clock pulse CLK3.

On the other hand, serial character data (34)
Means that "H" is 3 after low level "L" continues for 5 dots.
Since there is a dot (L1 in FIG. 9 ), it becomes "H" at the timing shown in FIG . Paste ON-1D2 (33)
Then, at the rising edge of the AND of the serial character data (34), the erasure symbol (31) becomes "L", and three dots of the serial graphic data (35) are erased. Therefore, the logical sum combined display data is data in which a diamond-shaped figure is pasted.

Since the erasure signal (31), which has become "L" in the character, maintains "L", the serial graphic data (35) is entirely erased. In the character, the paste END (30) becomes "H" while the paste ON (29) maintains "H" (see FIG. 5 and FIG. 5 ) .
6 ). In response, paste END-1D (3
6) is "H" at the falling of the clock pulse CLK3.
become.

On the other hand, the serial character data 34
After "L" has continued for two dots, there are three "H" dots, and then there are three "L" dots (L1 in FIG. 9 ) . L "
become.

Since the erase signal (31) becomes "H" at the rise of the NAND (fall of AND) of the paste ON-1D2 (33) and paste END-1D (36) and the serial character data (34), the serial The first five dots of the graphic data (35) are erased. Therefore, the logical sum combined display data is data in which only the rhombic figures are pasted.

Next, the operation will be described focusing on the display line L2 in FIG. Characters related to the filled composite display area on the line L2 of interest are,,, like the display line L1, and the attribute (attribute data) of each character cannot be set separately for each line. Therefore, it is set as described above. The action of the character on the display line L2 is the same as that on the display line L1.

The serial character data (34) is a pattern of 00011110 (L in FIG. 9 ) .
2) Therefore, once it becomes "H", it becomes "L" again. However, since the paste END (30) is at "L", the erase signal (31) is maintained at "L". Therefore, all the serial graphic data (35) is erased.

The operation of the character is the same as that of the display line L1. As can be seen from the operation of the line L2, the paste ON (2
For a character with 9) “H” and paste END (30) “L”, the painting operation is not terminated with any display data. Conversely, even if the paste END (30) is "L", if the paste ON (29) is "L", the filling from that character is stopped.

Next, the operation when there are a plurality of painted areas will be described. However, when the interval between the painted areas is one or more characters, the above-described operation is repeated, and the description is omitted.

As shown in FIG . 11 , a case will be described as an example where the boundaries of a plurality of painted areas are within the same character. Focusing on the display line L3, the characters related to the fill composite display area are (a),
(B), (c), (d), and (e). The attribute (attribute data) of each character is set as follows.

Character paste ON Paste END (a) ON OFF (b) ON OFF (c) ON ON (d) ON OFF (e) ON ON

Character (a) on display line L3
Is the same as the above-mentioned operation with the character. The operation of the characters (b) and (d) is the same as the operation of the character described above. The operation of the character (e) is the same as the operation of the character described above.

FIGS. 7 and 8 show timing charts for the character (c). The paste END (30) remains at "H" while the paste ON (29) maintains "H".
become. In response, paste END-1D (36)
Becomes "H" at the falling edge of CLK3.

On the other hand, serial character data (34)
Has a pattern of 01100110 ( FIG. 11 ) .
L3). Since the erase signal (31) becomes "H" at the rise of the NAND (fall of AND) of the paste ON-1D2 (33), the paste END-1D (36) and the serial character data (34), the serial graphic data The first three dots of (35) are erased.

At this time, F.S. The output Q (40) of the F (flip-flop circuit) 37 becomes "L". Next, the serial character data (34) becomes "H" again after "L" continues for two dots, so that the erasure signal (31) becomes "L" at this rising edge.

However, at the falling edge of the next serial character data (34), F.F. The output Q of F37 (4
Since 0) is "L", the erase signal (31) does not become "H" but maintains "L". Therefore, the latter three dots of the serial graphic data (35) are erased. Therefore, the OR combined display data is composed of two figures ( FIG. 1 ) .
Only 1 ) becomes the pasted data.

In the above description of the operation, an example is shown in which the fill-in display (paste display) is performed by erasing the graphic data in the specified area. It is possible by change. In this embodiment, the graphic display and the character display are combined. However, the same effect can be obtained by combining the character display and the character display.

[0061]

According to the present invention, an operation of selecting an arbitrary portion (region) of a display screen and performing a special process such as erasing or filling (replacement) on the selected region is synchronized with a display cycle. This can be performed continuously, and can be realized without increasing the memory for storing data for designating an area. Therefore, an image display device with high display quality can be constructed with a minimum circuit configuration.

Further, even when a plurality of areas to be subjected to the special processing as described above are specified, the present invention can be realized without increasing the memory for storing data for specifying the areas.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image display device showing one embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing a circuit configuration example of a synthesis circuit 11 in FIG.

FIG. 3 is a diagram showing a left half of a timing chart for explaining the operation of the combining circuit of FIG. 2;

FIG. 4 is a diagram showing the right half thereof.

FIG. 5 is a diagram showing a left half of a timing chart of another operation of the synthesis circuit of FIG. 2;

FIG. 6 is a diagram showing the right half thereof.

7 is a diagram showing a left half of a timing chart of still another operation of the synthesis circuit of FIG. 2;

FIG. 8 is a view showing the right half thereof.

FIG. 9 is an explanatory diagram of a pattern for explaining an example of processing of display data according to the embodiment shown in FIGS. 1 and 2;

FIG. 10 is an explanatory diagram of the character configuration.

FIG. 11 is an explanatory diagram of another pattern.

FIG. 12 is an explanatory diagram of an example of a display data processing method in a conventional image display device.

FIG. 13 is an explanatory diagram of another example of the conventional display data processing method.

FIG. 14 is an explanatory diagram of a processing example according to a conventional display data processing method.

FIG. 15 is an explanatory diagram of a processing example according to the display data processing method of one embodiment of the present invention.

[Explanation of symbols]

1 CPU 2 ROM 3 GC. RAM 4 CC. RAM 6 Display control circuit 7 Timing gemulator 8 CG. ROM 11 synthesis circuit 14, 15 latch 18, 19 multiplexer 20 bus driver 22, 28 serial in parallel out shift register (SP.SR) 25, 26 parallel in serial out shift register (PS.SR) 23, 37 flip-flop circuit ( FF)

Claims (2)

(57) [Claims] 1. An image display apparatus for reading image data from a frame memory of a parallel data input / output system as parallel data and sequentially transferring the data to a display, wherein a character of the image data read from the frame memory is provided. Means for giving a combination indicating a certain area and a combination indicating the end of the area in the attribute data set for each, and decoding the two attribute data to select an arbitrary area of the display screen, An image display device comprising means for continuously performing an operation of performing processing such as data erasing or painting on the selected area in synchronization with a display cycle. 2. The image display device according to claim 1, wherein
An image display device, wherein the number of units of designated areas provided in attribute data set for each character is plural.