JPS6365153B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character/figure signal generating device, and more particularly to a type of device suitable for personal computers that can display superimposed characters and figures in a raster scan method.

Currently, personal computers, which are rapidly becoming popular, can generally be connected to a raster scan type CRT display device. In order to enable personal computers to be used for multiple purposes, many personal computers can display both text and graphics on the CRT screen, and among these, the types that can display text and graphics overlapping each other have improved display effects and ease of use. is highly rated. Conventionally, a circuit having the configuration shown in FIG. 1 has been commonly used to realize such a function.
In FIG. 1, 1 is a clock signal generation circuit, 2 is a clock signal generation circuit;
3 is a display address generation circuit for graphics, 4 is a display address generation circuit for characters, 5 is a synchronization circuit, 6 is a display address bus for graphics, 7 is a display address bus for characters, and 8 is a scanning line number signal. Road, 9
and 10 are read/write memory for display (below
(abbreviated as RAM) 11 is a character generator, 12 is a horizontal
Vertical synchronization signal path, 13 and 14 are parallel to serial conversion circuits,
15 is a synthesis circuit, and 16 is a video signal path. Next, the operation of this conventional example will be explained. A clock signal generating circuit 1 generates a display clock 2 which is the basis of display, and supplies it to a graphic display address generating circuit 3 and a character display address generating circuit 4 via a synchronizing circuit 5. The synchronization circuit 5 controls the two display address generation circuits 3 and 4 to simultaneously start giving display addresses to each field, and at the same time generates horizontal and vertical synchronization signals. The display address generation circuits 3 and 4 repeatedly generate display addresses in frame cycles using the display clock 2 as a basic clock, and generate display addresses via address buses 6 and 7.
It is given to RAM9 and 10. Three of these display address generation circuits are for graphics, and the RAM for graphics
A graphic display address 6 to be given to 9 is generated. On the other hand, the character display address generation circuit 4 generates a character display address to be given to the character display RAM 10 and a scanning line number signal to be given to the character generator 11. The character display RAM 10 stores character codes written from a central processing unit (hereinafter abbreviated as CPU) (not shown), and in response to input of the character display address, the character code of the address is transmitted to the character generator 11. Output to. The character generator 11 is
Using the character code and the scanning line number signal as input information, prerecorded character patterns are output in parallel.

On the other hand, the graphic display RAM 9 records the graphic patterns themselves written by the CPU (not shown), and the graphic patterns are sequentially read out in parallel according to the content of the graphic display address.
This parallel figure pattern is processed by the parallel-to-serial conversion circuit 14.
The parallel character patterns mentioned above are converted into serial signals by the parallel-to-serial conversion circuit 13, and inputted to the synthesis circuit 15 where they are synthesized or superimposed.
The signal is then output as a video signal to a CRT display device, etc.

Figure 2 shows a typical example of the relationship between display position and address when characters are actually displayed on a CRT screen. In Figure 2, 17 is a single character display area, and 18 broken lines are scanning lines or 1 character display areas each.
The number shown with $ within 7 is the corresponding hexadecimal read address of the display RAM 10. In the example in Figure 2, there are 80 characters horizontally and 80 characters vertically.
There are 25 lines, each line consisting of 8 scan lines.

Next, FIG. 3 shows the relationship between the display of graphic patterns and addresses. In the figure, 19 is one address area, and 20 is one dot display area. The number in each one address area is the hexadecimal read address of the graphic display RAM 9 corresponding to that position. In this example, 80 addresses horizontally and vertically
With 200 scanning lines, each address is assigned 8 dots in the horizontal direction and 1 dot in the vertical direction to each scanning line, so figures can be displayed with a fineness of 640 dots horizontally and 200 dots vertically on one screen. .

Since the character screen in FIG. 2 and the graphic screen in FIG. 3 have the same number of scanning lines, they can be superimposed if the horizontal and vertical synchronization signals and display periods match.

By the way, when displaying graphics and text in an overlapping manner using this method, it is necessary to prepare display RAM for text and graphics that is multiple times the memory capacity required to display one screen. The display start address of the display address generation circuits 3 and 4 is
The advantage is that paging, which switches and displays multiple display screens, can be performed independently of graphics and text by reconfiguring the settings on the CPU. On the other hand, it has the disadvantage that it requires two display address generation circuits, one for graphics and one for characters, and a synchronization circuit for both, resulting in an increase in circuit scale.

An object of the present invention is to improve the disadvantage of the conventional technique in that the circuit scale is large, without impairing the advantages of the conventional technique described above, and to make it easier to share the graphic display RAM and the character display RAM. The object of the present invention is to provide a character and graphic display device that displays images.

To achieve the above purpose, by using the display address for characters for one screen and the scanning line number signal as the display address for graphics, the display address generation circuit for graphics and the character/graphics address are synchronized. The idea is to omit the circuit and obtain a separate register for graphics that can be set by the CPU for the upper display address that controls paging, and to provide the output thereof.

An embodiment of the present invention will be described below with reference to FIG. In FIG. 4, 1 is a clock signal generation circuit, 2 is a display clock, 4 is a display address generation circuit, 8 is a scanning line number signal path, and 9 is a graphic display.
RAM, 10 is character display RAM, 11 is character generator, 12 is horizontal/vertical synchronization signal path, 13, 14
15 is a parallel-to-serial conversion circuit, 15 is a synthesis circuit, 16 is a video signal path, 21 is a display lower address bus, 22 is a display upper address bus, 23 is a graphic display page designation signal path, 24 is a CPU data bus, and 25 is a graphic display This is a page setting register. Among the above-mentioned components, 1 to 16 have the same content as the components labeled with the same numbers in FIG. 1, so the explanation will be omitted. The newly added display lower address has a minimum number n of bits that can specify a 2 ⁿ (n is a positive integer) address that is larger than the number N of character addresses for one screen, and is In the case of the screen configuration as shown in the figure, N=2.000<2 ¹¹ =2.048, and n=11 bits. The 0th to 10th address bits are connected to the graphic display RAM 9 and the character display via the address bus 21.
It is applied to both RAMs 10 in parallel. The display upper address is the 11th to 15th address other than the display lower address among the display addresses outputted from the display address generation circuit 4, and is applied only to the character display RAM 10 via the address bus 22. Graphic display page designation signals are not shown.
A 2-bit signal that can be set in the graphic display page setting register 25 by writing from the CPU via the CPU data bus 24 is input to the graphic display RAM 9 as the 14th and 15th display upper address bits. Furthermore, the graphic display
The RAM 9 also contains the scanning line number signals 11th to 13th.
It is input as the display upper address bit.
The display data read out according to these display address inputs is converted into a serial signal via the character generator 11 and parallel-to-serial conversion circuits 13 and 14,
The combination circuit 15 superimposes the signals and outputs them as a video signal, as described in the explanation of FIG. 1 above. At this time, the relationship between the character display screen and the display address is the same as in FIG. 2 in the case of 80 columns and 25 lines display. On the other hand, the relationship between the graphic display screen and the display address is determined so that, as shown in FIG. 5, the address is determined by adding 800 in hexadecimal for each scanning line in the vertical direction in units of 8 scanning lines. Now, display for said character
Increase the capacity of RAM10 to 16K bytes, graphics display RAM
Assuming that the capacity of 9 is 64K bytes, the display RAM required for one character screen is just under 2K bytes in this example.
Since the display RAM required for one graphic screen is just under 16K bytes, it is possible to have 8 and 4 page display screens respectively. In the case of the character display RAM 10, these pages can be switched and displayed instantly by resetting the display start address register (not shown) in the display address generation circuit 4 by the CPU. By setting the start address every 2K bytes, which is the address for one screen, only the upper bits of the display address line change when the page is changed, and the
Since it does not affect the lower 11 bits of 10, it does not affect the display address given to the graphic display RAM 9. On the other hand, page switching on the graphic screen is performed using the graphic display page setting register 25.
This is done by setting 2-bit data from the CPU and changing the graphic display page designation signal, which is the upper 2 bits of the graphic display RAM. At this time, the address of the character display RAM 10 is not affected at all. Therefore, according to this embodiment, the display address generation circuit for characters and graphics can be shared, and the synchronization circuit 5 described above can also be omitted. Furthermore, while the character display screen and the graphic display screen are displayed in a superimposed manner, it is possible to page any one of them completely independently.

Next, a second embodiment of the present invention will be described with reference to FIG. In Figure 6, 1, 2, 4, 8,
9, 11, 12, 13, 14, 15, 16, 2
1, 22, 23, 24, and 25 have the same names and functions as the components shown in FIG. 4 with the same numbers. The newly added 26 is the character/figure shared display RAM, 2
7 is an upper address switching circuit, 28 is a composite upper address bus, 29 is an upper address switching signal path,
30 is a composite display data bus. In this example,
The configuration is such that the graphic display RAM 9 and character display RAM 10 in the first embodiment are shared.

The operation of this embodiment will be explained below. In FIG. 6, the upper address switching circuit 27 switches between the display upper address, which is the upper address for characters from the display address generation circuit 4, in response to the upper address switching signal output from the clock signal generation circuit 1. , the graphics display page designation signal, which is an upper address for graphics, and a signal obtained by combining the scanning line number signal are applied to the text/graphics shared display RAM 26 as the composite upper address. The character/figure shared display RAM 26 uses eight of the most common 64K-bit dynamic RAMs, such as Hitachi's HM4864, which input column-related addresses and row-related addresses in a time-sharing manner, and has a capacity of 64K bytes. This configuration block also includes a switching circuit for column-related addresses and row-related addresses. The display data for characters and graphics are alternately outputted as composite display data 30 from the character/figure shared display RAM 26, and the display data for characters is outputted to the character generator 11, and the display data for graphics is outputted to the parallel/serial display data. The signal is input to the conversion circuit 14. The output of the character generator 11 is converted into a serial signal of a character pattern by the parallel-to-serial conversion circuit 13, and superimposed with the serial signal of a graphic pattern, which is the output of the parallel-to-serial conversion circuit 14, by the synthesis circuit 15 to form a video signal. It is output to a CRT display device (not shown) as .

Next, how to give a display address in this embodiment will be explained. The display screen configuration is the same as in the first embodiment described above, with characters being 80 columns x 25 lines and graphics being 640 dots x 200 dots. As with the first embodiment, 11 bits of the 0th to 10th bits of the lower display address are directly applied to the character/figure shared display RAM 26. The display upper address, which is the upper address for characters, consists of the 11th to 15th address bits, of which the 15th bit is always at the "H" level in order to select the character area. On the other hand, the upper address for graphics is the 11th to
The graphics display page designation signal, which is the output of the graphics display page setting register 25, is assigned to the 14th address bit. The 15th address bit always maintains the "L" level in order to select the graphic area. The results of such address assignment are summarized in the memory map shown in FIG. As is clear from Figure 7, the first 32K bytes of the 64K byte display area is the graphics area.
It can have 2 pages. In addition, the latter 32K bytes is a text area that can hold 16 pages. The relationship between the display screen and the address in this case is exactly the same as in FIG. 5 in the case of the 0th page for graphics. For the 0th page for text, send $ to the address shown in Figure 2.
It is the same as adding an offset of 8000.

Next, regarding the timing relationship of this example, the eighth
This will be explained using figures. In FIG. 8, a is the signal waveform of the upper address switching signal, b is the display address input to the 64K-bit dynamic RAM, 31 is the row-related address, 32 is the column-related address for characters, and 33 is the column-related address for graphics. , c is the signal,
d is a signal, 34 is a character address capture edge, 35 is a graphic address capture edge, e is a signal waveform of the composite display data 30, 36 is character code data, 37 is graphic pattern data, and f is the output of the character generator 11. Data and g are parallel data input signals to the parallel-to-serial conversion circuits 13 and 14. The row-related address 31 contains a total of 8 bits from the 0th to 7th bits of the 11 bits of the display lower address.
The remaining 3 bits of the display lower address and 5 bits of the composite upper address are assigned to the row-related address. The signal is generated by the clock signal generation circuit 1 and is a signal that takes in the row-related address 31 at its rising edge. The signal is also generated by the clock signal generation circuit 1, and the column-related addresses 32 and 33 are taken in at its falling edges 34 and 35. In general dynamic RAM, the use of assigning two or more column addresses to one row address is called page mode, and when the row addresses are the same, RAM access per address is It has the advantage of saving time. The character code data 36 read out at the given address in this manner is taken into the character generator 11 and outputs character pattern data at the timing shown in FIG. 8f. On the other hand, the graphic pattern data 37
is determined at the timing shown in the figure, and the parallel-to-serial conversion circuit 1 is loaded at the same timing as the character pattern data is taken into the parallel-to-serial conversion circuit 13 by the parallel data take-in signal (FIG. 8g).
Incorporated into 4.

According to this embodiment, in addition to the effects obtained in the first embodiment, RAM for characters and graphics can be shared, and the character code data can be displayed in a superimposed manner at the same position using graphic pattern data. Since the data can be outputted at a timing earlier than 37, there is no need for a circuit to hold the graphic pattern data for the access time of the character generation circuit 11, making it possible to reduce the circuit scale and cost. Furthermore, it becomes possible to relatively flexibly allocate the ratio between the graphic area and the character area.

In addition, although this embodiment and the first embodiment describe only the case of black and white display, the above-mentioned display
It is obvious that when the RAM has a plurality of parallel series and performs color display, the same processing can be performed for each series.

According to the present invention, it is possible to omit a graphic display address generation circuit and a synchronization circuit without impairing the conventional advantage of being able to display characters and graphics in a superimposed manner and simultaneously perform independent paging. It is possible to more easily share display RAM and character display RAM using inexpensive, large-capacity dynamic RAM.The majority of display address lines can be shared, resulting in circuit simplification and cost reduction. It is very economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the prior art, FIGS. 2 and 3 are conceptual diagrams for explaining the prior art, and FIG. 4 is a block diagram for explaining the first embodiment of the present invention. Fig. 5 is a conceptual diagram for explaining the first embodiment, Fig. 6 is a configuration diagram showing the second embodiment, and Fig. 7 is a conceptual diagram for explaining the first embodiment.
The figure is a memory map for explaining the second embodiment, and FIG. 8 is a timing diagram for explaining the operation of the second embodiment. 4...Display address generation circuit, 9...Graphic display
RAM, 10...Character display RAM, 21...Display lower address, 22...Display upper address, 23...Graphic display page designation signal, 25...Graphic display page setting register, 26...Character/figure shared display RAM, 2
7... Upper address switching circuit, 28... Composite upper address.

Claims (1)

[Claims] 1. Graphic data for m×M dots in the horizontal direction and n×N dots in the vertical direction are stored, and the horizontal direction is divided into M.
Output of graphic display RAM that can read graphic data for m dots divided in one access, and character display that stores M rows and N columns of character codes.
A character/graphics display device that receives the output of a RAM and synthesizes it with the output of a code pattern converter that outputs an m-row, n-column dot pattern.
A set of RAM addresses and code pattern converter addresses is generated from a common display address generation circuit, and access control is performed in synchronization with the set of graphic display RAM, character display RAM, and code pattern converter. Characteristic graphic display device.