JPS645310B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to a device that executes processing using a plurality of memories with different addressing systems.

Conventionally, there is an image processing device as such a device. Here, a raster scanning cathode ray tube (hereinafter referred to as CRT) is used as the display device, and the image processing device has the function of performing display processing based on information stored in memory (for example, refresh memory using dynamic memory). This is one of the important functions of There are two types of memory that are handled; the first is a memory that stores the image data itself that is supplied to the CRT. The second is a memory in which an address for a pattern generator (character generator) in which image data is preset is stored. By using these two types of memories, for example, characters and images can be combined and displayed on one screen. However, the addressing schemes for these first and second memories are different, as will be described later. Therefore, as shown in FIGS. 1 and 2, address control circuits for each memory had to be provided completely independently. That is,
The address control circuit for the first memory includes:
As shown in FIG. 1, it includes an address generation circuit 2, a refresh memory 1 (hereinafter referred to as video memory) in which video data is stored as is, and its peripheral circuits. First, before starting the display, the central processing unit (CPU) sends the display start address (hereinafter referred to as SAD) to the video memory 1 via the system data bus 6 to the display address address of the address generation circuit 2. It must be set in a register (hereinafter referred to as DAD register). After that, from address generation circuit 2
SAD is output to the address bus 5 and applied to the address terminal of the video memory 1. The data thus read from the video memory 1 is set in the parallel-to-serial conversion shift register 3 under timing control by the load clock 9. This is shifted in accordance with the shift clock 10 and becomes a video serial signal 11, which is supplied to the CRT. In the address generation circuit 2, DAD is generated every time the above series of operations are completed.
+1 → DAD (Add 1 to the contents of the DAD register
Display is performed by repeating the above operation based on the newly created address.

Next, the address control circuit for the second memory will be explained with reference to FIG. This memory is mainly used for displaying characters, figures, etc., and the video memory 21 stores character code addresses for specifying characters to be displayed, for example, for one screen. Before starting display, the SAD of the video memory 21 is set in advance in the DAD register of the address generation circuit 22 from the CPU via the system data bus 26.
Note that each character specified by the character code address stored in the video memory 21 is generally composed of multiple lines in the vertical direction on a CRT, so the line address for specifying this is the line counter 3.
2 is set separately. For display, SAD is outputted from the address generation circuit 22 to the address bus 25 and given to the video memory 21. The character code address read from the video memory 21 is stored in the character generation memory (character generator) 33.
given to. At the same time, the line counter 32
The line address output from the character generation memory 33 is also given to the character generation memory 33. Display character data is accessed from the character generation memory 33 based on the character code address and line address. The data output from the character generation memory 33 is transferred to the parallel-to-serial conversion shift register 2 by the load fluff 29.
3 and is converted into a video serial signal 31 by a shift flop 30 and supplied to the CRT. In the address generation circuit 22, DAD+1→DAD
Perform address calculation (increase the contents of the DAD register by 1 and set it in the DAD register), and repeat the above operation. Here, depending on the address of the DAD register, the character string (N
When accessing and displaying the Nth character code of the character string of is accessed again, and at the same time, the value of the line counter is incremented by 1, and display of the next line of the same character string is started. In this way, when the specified number of lines of the horizontal character string have been displayed, the contents of the line counter are reset, and the value of the DAD register is also set to the first character code of the next character string to be displayed horizontally. Display is performed by changing the content to be accessed (SAD+N→DAD).

As explained above, the first memory and the second memory have different address formats. If multiple video memories are accessed using the same address format, the upper address bits are used to select the memory when writing to the video memory, and when displaying, the upper address bits are ignored and the remaining addresses are used. By simultaneously applying to multiple video memories, it is easy to display each piece of information stored in multiple video memories on a CRT at the same time.
directly corresponds to the data supplied to the a first video memory storing image data;
In order to perform simultaneous display using a character generator (second memory) in which the character data to be displayed is coded and stored in advance, two types of address generation circuits are required because the display address formats are different. This made the equipment complicated.

An object of the present invention is to provide an information processing device that accesses at least two memories with different address formats using common address data.

That is, in an image control device, a character code address and a line address are required based on consecutive addresses given to a memory containing image data that directly corresponds to data supplied to a CRT. To provide a device that can read out information in at least two types of video memories having different address formats by accessing a character generation memory having a character generation circuit and using continuous display addresses output from an address generation circuit. It is something to do.

The present invention includes a first memory in which image data is stored, a second memory in which character information is stored, and a third memory in which information for selecting an arbitrary character in the second memory is stored. and a system of address generation circuits for generating addresses for the first, second, and third memories, and applying the addresses output from the address generation circuit to the first memory. However, the intermediate bit group excluding the upper bit group and the lower bit group of the address is applied to the second memory, and the upper bit group excluding the intermediate bit group is applied to the third memory. and the lower bit group are applied.

According to the present invention, at least two memories having different address formats can be easily accessed based on a common address.

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 3 is a block diagram showing one embodiment of the present invention.
The first memory 41 and the second memory 42 are used as video memories, the first memory 41 stores character code address data, and the second memory 42 stores images directly corresponding to data supplied to the CRT. Data for each screen is stored. In the write cycle for writing data into these two video memories 41 and 42, the most significant bit signal 58 (hereinafter referred to as A _H ) of the address generated by the CPU is used.
A selection of two memories is made by . A _H
If =0, the read signal of the first memory 41 is activated by the read signal control circuit 54, outputted to the data bus 46 of the first memory, and taken into a device that processes image information. After the data has been processed, the first
The write signal of the memory 41 is activated, and the processed data is stored in the first memory 41. A _H
In the case of =1, the second memory 42 is similarly selected and image data is written.

During the display cycle, the most significant bit signal (A _H ) of the address is ignored and the remaining address signals are output to address bus 47. As shown in Figure 4, the address output is the second address output.
The address information is given to the memory 42 as it is, but the address information A, A, is given to the first memory 41 by the address control circuit 56 as shown in FIG.
It is separated into A′ and line information B, address information A,
A' is provided to the first memory 41. Data read from the first memory (character code address)
and line information are given to the character generation memory 57, and the output data from the character generation memory and the output data from the second memory are simultaneously sent to the load float 50.
Parallel-to-serial conversion shift register 44, 4
5 and shifted by a shift flop 51 to become video serial signals 52 and 53, which are mixed by a mixer 60 and supplied to a CRT 61.

According to this embodiment, the address control circuit 56 separates the address output into addresses A and A' necessary for the video memory 41 and line information (address) B necessary for the character generation memory, etc. Therefore, the display address output from the address generation circuit may be a continuous display address so that the video memory 42 can be accessed as is.
Moreover, there is no need to provide separate address generation circuits for the two memories 42 and 57, and the function of simultaneously displaying the contents of two types of video memories can be realized very easily and at low cost.

In Figure 4, of the address information A and A', A' has bits corresponding to the number of characters displayed horizontally on the CRT screen, and A has bits displayed vertically on the CRT screen. Bits corresponding to the number of characters are assigned. Furthermore, bits corresponding to the number of lines in the vertical direction of the dot matrix representing each character are assigned to B sandwiched between A and A', that is, line information. As a result, desired characters can be selected and displayed in sequence simply by sequentially increasing the address output by +1 from 0.

Furthermore, the mixer 60 may mix both, or may display one of them with priority.

Further, the present invention can be widely applied not only to image processing but also as a memory access method for ordinary information processing devices.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional display control device, FIG. 3 is a block diagram of a display control device in an embodiment of the present invention, and FIG. 4 is a block diagram of an address generation circuit in an embodiment of the present invention. FIG. 3 is a configuration diagram showing an address code output from an address control circuit. 1, 21...Memory, 41...First memory, 4
2... Second memory, 2, 22, 43... Address generation circuit, 3, 23, 44, 45... Parallel-to-serial conversion shift register, 54... Read signal control circuit, 55... Write signal control circuit, 4,2
4, 46...data bus, 5, 25, 47...
Address bus, 6, 26, 47... System data bus, 7, 27, 48... Read signal, 8,
28, 49...Write signal, 9, 29, 50...
...Load block, 10,30,51...Shift block, 11,31,52,53...Video serial signal, 32...Line counter, 33,57...
Character generation memory, 56...address control circuit,
58...Most significant address signal, 60...Mixer,
61...CRT.

Claims (1)

[Claims] 1 A first memory in which image data is stored, a second memory in which character information is stored, and a third memory in which information for selecting an arbitrary character in the second memory is stored. , a system of address generation circuits that generate addresses for the first, second, and third memories; an address output from the address generation circuit is applied to the first memory; An intermediate bit group excluding the upper bit group and lower bit group of the address is applied to the second memory, and the upper bit group and the lower bit group excluding the intermediate bit group are applied to the third memory. An information processing device characterized by applying a side bit group.