JPS58123583A - Information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to a device that executes processing for a plurality of memos IJ-i having different addressing systems.

Conventionally, there is an image processing device as such a device.

Here, the Rusk scanning cathode ray tube (hereinafter CR, T
One of the important functions of an image processing device is to use it as a full display device (called "dynamic memory") and to perform display processing based on information stored in a memory (for example, dynamic memory (e.g., dynamic memory)).

There are two types of memory that are handled; the first is CB;
This is a memo 11 in which the image data itself supplied to T- is stored. The second is a memory in which an address for a pattern generator (character generator) is stored in which image data is preset. By using these two types of memory kumquats, for example, characters and images can be combined and displayed on one screen. However, the addressing schemes for these first and second memories are different, as will be described later. Therefore, as shown in FIGS. 1 and 2, address control circuits for each memory had to be provided completely independently. That is, the address control circuit for the first memory includes an address generation circuit 2 as shown in FIG.
It includes a refresh memory 1 (hereinafter referred to as video memory) in which video data is stored as is, and its peripheral circuits. First, before starting the entire display, the central processing unit (CPU) sets the display start address (hereinafter referred to as SAD) for the video memory 1 as system data.
The display of address generation circuit 2 via bus 6
It must be set in the address register (hereinafter referred to as the DAD register). After that, address generation circuit 2
The SAD is output from the address bus 5 to the address terminal of the video memory 1. The data thus read from the video memory 1 is set in the parallel-to-serial conversion shift register 3 under timing control by the load clock 9. This is shifted in accordance with the shift clock 10 and is supplied to the fi CIILT as a video serial signal 11. In the address generation circuit 2, each time the series of operations described above is completed, the address calculation is performed as follows: DAT) + l → DAD (the contents of the DAD register are increased by +1 and reset to the DAD register), and based on the newly created address, Display is performed by repeating the above operations.

Next, the address control circuit for the memory of fJJJ2 will be explained with reference to FIG. This memory is mainly used for displaying characters, figures, etc., and the video memory 21 stores character code addresses for specifying characters to be displayed, for example, for one screen. Before starting the entire display, the CPU sends the system data bus 26'! 5Ai) of the video memory 21 is set in the 1→Al) register of the address generation circuit 22 via i1''.

Incidentally, each character stored in the video memory 21 and specified by the character code address b is generally CI? - Since it is composed of multiple lines in the T upper knitting direction, a line address for specifying this is separately set in the line counter 32. When displaying, the address generation circuit 22 outputs the SAD
is output to the address bus 25 and applied to the video memory i) 21. The character code address read from the video memory 21 is given to a character generation memory (character generator) 33. At the same time, line counter 3
The line address output from 2 is also the character generation memory 3.
given to 3. Display character data is accessed from the character generation memory 33 based on the character code address and line address. The data output from the character generation memory 33 is loaded into the parallel-if column conversion shift register 23 by the load clock 29, and
0, the video serial signal 31 is supplied to the pcIIT. In the address generation circuit 22, I) AD+1→DAD
Perform address operation (add 1 to the contents of the DAD register and set it in the DAD register), and repeat the above operation. Here, when the Nth character code of the character string (N characters) to be displayed horizontally on the CRT is accessed and displayed using the address of the DAD register, the value of the AD register is set again to 81LDVC ( Separate → DAD)
, CRTh again accesses the first character code of the character string to be displayed in the horizontal direction, and at the same time, the value of the line counter is incremented by 1, and display of the next line of the same character string is started. In this way, the display of the specified number of lines of the horizontal character string is completed. 5- The contents of the line counter are reset, and the value of the DAD register is also set to the first value of the next character string to be displayed horizontally. Change the character code to the content to be accessed (SAD+N →
The display is performed as follows.

As explained above, the first memory and the second memory have different address formats. If the address format for accessing multiple FLL+memories is the same, the upper address bit is used to select the memory when writing to the video memory, and the VC ignores this upper address bit when displaying. By giving remaining addresses to multiple video memories at the same time, it is easy to display each piece of information stored in multiple video memories on a CRT at the same time. A first video memory in which image data is stored, and a character generator (in which character data to be displayed is pre-coded and stored) correspond directly to data supplied to CI (T). In order to perform all displays at the same time using the second memory (second memory), two types of address generation circuits are required because the display address formats are different, and the device becomes complicated.

An object of the present invention is to provide an information processing apparatus that accesses at least two memories with different address formats using common address data.

That is, in the image control device tJC, the character code address and the line address are determined based on the continuous atto vs w given to the memory having the image data that directly corresponds to the data supplied to the CRTIC. By accessing character generation memory that requires All equipment is provided.

The information processing device of the present invention includes at least a first memory and a second memory storing image data, and a part of the address information necessary for reading the image data of the second memo 1). the third memory in which the data is stored, and the first
an address generation circuit that generates an address for sequentially reading out the image data stored in the memory of the address generator; and an address control circuit that separates the address output from the address generation circuit into first and second portions of the address. The third memory is accessed by the first part separated by the control circuit, and the read address information and the address of the second part are used to access the third memory. The entire feature is that it accesses memory.

According to the present invention, it is possible to easily access at least two memories having different address formats using a common address.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention, *I
J -e +14□1.2・)'y -e +) 4
゜Work 1, 1. The first memory 41 stores character code address data, and the second memory 42 stores character code address data.
One screen worth of image data that directly corresponds to the data supplied to each is stored. In a write cycle in which data is written to these two video memories 41 and 42, the two memories are selected by a signal 58 (hereinafter referred to as AH) of the most significant bit of the address generated by the CPU at ff. When NH=O, the read signal of the first memory 41 is activated by the read signal control circuit 54, outputted to the data bus 46 of the first memory, and taken into a device that processes image information. After the data is processed, the write signal control circuit 55 activates the write signal of the first memory 41, and the processed data is stored in the first memory 41. When AH=1, the second memory 42 is similarly selected and image data is written therein.

Beyond the display cycle, the most significant bits (AI) of the address are ignored and the remaining address signals are output to the address bus 47. The address output as shown in FIG. 4 As shown in Figure 4, address information A, A' and line information B are separated, and address information IL, A' is the first
It is applied to memory 41. The data (character code address) and line information read from the first memory are given to the character generation memory 57, and the output data from the character generation memory and the output data from the second memory are transferred to the same load flow. Parallel-to-serial conversion shift register 44 by F5o
, 451C are loaded, shifted by the shift flow rough 51, and mixed into video serial signals 52, 53 by the mixer 6o and supplied to the CRT 61.

According to this embodiment, the address control circuit 56 separates the address output into addresses A and A' necessary for the video memory 41 and line information (address) B necessary for the character generation memory, etc. Therefore, the display address output from the address generation circuit may be a continuous display address that allows the video memory 42 to be accessed as is.

Moreover, it is not necessary to provide separate address generation circuits for the two memories 42 and 57, and the function of simultaneously displaying the contents of two types of 10-video memories can be realized very easily and at low cost.

In addition, in Fig. 4, 5% of the address information A, A'
Bits corresponding to the number of characters displayed horizontally on the CR'l' screen are assigned to A', and bits corresponding to the number of characters displayed vertically on the CRT screen are assigned to IK. Further, bits corresponding to the number of lines in the vertical direction of the dot matrix displaying each character are assigned to B1, that is, line information sandwiched between & and A'. As a result, one desired character can be sequentially selected and displayed by simply incrementing the address by +1 from the address output 'kO.

Furthermore, the mixer 60 may mix both, or may display one of them with priority.

Further, the present invention can be widely applied not only to image processing but also as a memory access method for ordinary information processing devices.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of conventional display control devices, Figure 3 is a block diagram of a display control device according to an embodiment of the present invention, and Figure 4 is a block diagram of an address generation circuit according to an embodiment of the present invention. FIG. 3 is a configuration diagram showing an address code output from an address control circuit. 1.21...Memo+1,41...1st
Memory, 42...2nd memo 182, 22.43
...Address generation circuit, 3.23, 44.45
...Parallel-serial conversion shift register, 54...
... Read signal control circuit, 55 ... Input signal control circuit, 4, 24° 46 ... Data bus, 5, 25.47 ... Address bus, 6
,26.47...System data no.,7,
27.48... Read signal, 8,28°49
...Write signal, 9,29.50...
・Roadflock, xo,, '14o, 51...
・・Shift flock, 11, 31, 52.53・・・・
...Video serial signal, 32..., ...Line counter,
33.57...Memory for character generation, 56...
. . . address control circuit, 58 . . . 1 is upper address signal, 60 . . . mixer, 61 . . .
C.R.T. Agent Patent Attorney Susumu Uchihara 13- #1 Diagram

Claims (1)

[Claims] a first memory, a second memory and a third memory; means for generating an address for accessing said fourth memory; and means for separating said address into at least a first and a second portion; - means for accessing said second memory using said first portion and data read thereby; and means for accessing said third memory using said second portion. Information processing equipment.