KR0170754B1 - Dram usage for cdg and cdeg system - Google Patents

Abstract

In the CDG and CDEG systems, the present invention relates to a DRAM usage method for using one 1M DRAM without significant modification to a DRAM address block designed with two 256K DRAMs.

According to the present invention, in the CDG and CDEG systems that use one or more DRAMs for graphics in the CDEG mode, a data write classification step for distinguishing according to an instruction when data is written, when the instruction is a write font and an exclusive ora font, Write data to be written to the Even column of the same row and Write data to the Od column of the same row, and Write to the exclusive Oa font, Free if the instruction is a scroll screen of the preset memory. A scroll screen write step of a preset memory that writes sequentially to an area to be set, and two registers each of which stores one data in turn depending on whether or not the column value is read or opened, one by one This is done by reading the data that creates the code for.

Description

How to use DRAM in CDG and CDEG systems

1 is a format diagram of pack data in the case of a writing font and an exclusive-OR FONT instruction.

2 is a diagram showing a match between a position of a screen displayed on a monitor and an address of a DRAM.

3 is a flowchart of a DRAM usage method of a CDG and CDEG system according to the present invention.

4 (a) and (b) show an 8-bit code formation process when reading data.

* Explanation of symbols for main parts of the drawings

1: 8-bit register 2, 3: 4-bit register

The present invention relates to a DRAM use method for using a single 1M DRAM in a CDG and CDEG system without major modifications to a DRAM address block designed as two 256K DRAMs.

CDG and CDEG have a function of displaying a still picture on a monitor such as a TV by using a subcode area of the CD data format.

The data format of the sub code is defined in packs. A pack consists of 24 symbols including 6 parity symbols. The CDG / CDEG mode is selected with the MODE / ITEM symbol, and the Instruction Symbol defines the detailed functions such as the Write FONT and the Scroll FONT.

In the CDG mode, the color is defined as 4 bits and the screen is displayed in 16 colors. In the CDEG mode, 256 colors are displayed with 8 bits including the 4 bits of the CDG mode.

Since the screen area of the CDG / CDEG is 300 × 216 = 64800 pixels, and color values of 4 bits must be stored for each pixel, one 256K DRAM (= 65536 × 4 bits) is required for CDG, and for CDEG Two 256K DRAMs will be required.

In other words, the minimum size of DRAM required for CDG is one 256K DRAM, and the minimum size of DRAM required for CDEG is two 256K DRAM.

However, if a set is made using only one DRAM having a size of 1M bit or more, the conventional method does not implement CDEG. In other words, 8 bits for representing 256 colors of CDEG are not defined at one time using one pack data, and 4 bits for CDG and 4 bits for CDEG are combined to form 8 bits. There is this.

Accordingly, an object of the present invention is to provide a method of using a DRAM in which a CDEG can be normally implemented while using only one DRAM of 1M or more without large modifications to a DRAM-related address block designed for 256K DRAM in a CDG and CDEG system. have.

In order to achieve the above object, a DRAM using method of the CDG and CDEG system according to the present invention is a CDG and CDEG system for performing graphics in the CDEG mode by using one or more 1M DRAM, the data writing according to the instruction when writing data Classification step, if the instruction is a write font and an exclusive ora font, write and exclusive ora to write data to be used in PM in the Even column of the same row and write data to be in odd column of the same row in the same row Writing of the font, scrolling of the preset memory sequentially writing to the area to be preset when the instruction is a scrolling screen of the preset memory, and column value upon reading the data according to even or odd Two registers to store one data are opened one by one, one code It is characterized in that performed by the data reading step of making a.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a format diagram of pack data in the case of a writing font and an exclusive-OR FONT instruction, and FIG. 2 is a diagram showing a match between a position of a screen displayed on a monitor and an address of a DRAM. FIG. 4 is a flowchart illustrating a DRAM usage method of a CDG and CDEG system according to the present invention. FIG. 4 is a diagram illustrating an 8-bit code formation process when reading data.

In the case of CDG and CDEG writing font instructions, the pack data has color 0 (COLOR0) and color 1 (COLOR1) in symbols 4 and 5, and ROW in symbols 6 and 7 as shown in FIG. And a column (COLUMN), where the font (FONT) is located from the symbol 8 to the symbol 19.

The screen is positioned according to the ROW and COLUMN values of symbols 6 and 7, and the color 0 and color 1 values are written into the DRAM according to the font values from symbols 8 to 19. . That is, if the font value is '0', four bits of color 0 are written to the DRAM. If the font value is '1', four bits of color 1 are written to the DRAM.

In the implementation of CDEG using 256K DRAM, the color value of the CDG write font is written to the first DRAM and the color value of the CDEG write font is written to the second DRAM.

The matching between the position of the screen displayed on the monitor and the address of the ORAM is as shown in FIG.

That is, 300 addresses from the address (0,0) of the DRAM to (0, 255) and the addresses (1, 0) to (1, 43) become the first line of the screen, and the address of the DRAM (1, 300 addresses from 44) to (1, 255) and addresses (2, 0) to (2, 87) become the second line of the screen.

In this manner, 300 addresses are sequentially divided to match 216 lines on the screen, and the divided 300 addresses are matched to each pixel of the line.

3 illustrates a DRAM usage method of a CDG and CDEG system according to the present invention with reference to the following.

First, in the case of the CDG mode by selecting the graphics mode, as in the conventional case, the interface between the primary memory (PM) and the secondary memory (SM) is enabled to read and write data for the CDG.

When the graphics mode is the CDEG mode, there are two ways to operate according to the DRAM mode.

First, when two 256K DRAMs are used, they are represented by PM and SM, thereby enabling the PM and SM interfaces, respectively.

Here, 8 bits of address, 4 bits of data, and write enable (WE) for the PM and 8 bits of data, 4 bits of data for the SM, and a pin for write enable (WE) are required. The pins are required for output enable (OE), row address strobe (RAS), and column address strobe (CAS), which are common to both the and SM.

In case of using 2 DRAMs, it decides whether to store PM or SM with the same address value and two write enable signals (WE) at the time of writing. At the same time, it reads 8 bits of 4 bits of the most significant bit (MSB) and 4 bits of the least significant bit (LSB) to make an 8-bit code.

Next, in the case of using one 1M DRAM, that is, implementing the CD / CDG using only one DRAM, the address bits require at least 9 bits, and data, write enable, output enable, and row address scrubs are required. Only one pin for each of the, and column address strobes is required.

That is, the address for writing and reading data consists of 9 bits, and the data consists of 4 bits.

The DRAM usage method of the CDG and CDEG system according to the present invention is performed by data writing classification step, writing and exclusive OA font writing step, scroll screen writing step of preset memory, and data reading step according to the interface of writing and reading. do.

First, the data write classification step is classified according to an instruction when writing data when using a single 1M DRAM, and the instruction is a write font and an exclusive X-OR font and a scroll screen of the preset memory. There is a case.

As described above, when the instruction is a writing font and an exclusive ora font, a writing and an exclusive ora font writing step are performed. When the instruction is a scroll screen of the preset memory, a scroll screen writing step of the preset memory is performed.

If the instruction is a write or exclusive ora font, the PM and SM writes are separated, so there is no need to change the operating frequency of the DRAM interface.However, if the instruction is a scroll screen of the preset memory, the PM and SM writes are not possible. Since this happens at the same time, when writing with one memory, the operating frequency of the DRAM interface unit should be doubled.

Write and Exclusive Oa Font The Write step writes data to be used for PM in the Even Row of the same row if the instruction is a write font and an exclusive Oa font. Write to Odd Column At this time, the operating frequency is the same frequency as when using two 256K DRAM.

That is, the row address does not change and only the column address changes. The column address corresponding to the data to be written in the PM becomes an even column multiplied by 2 and the column address corresponding to the data to be written in the SM It is an odd column that multiplies the existing address by 2 and adds 1 again.

For example, data to be written to the addresses 10 and 10 of the PM is written to the addresses 10 and 20, and data to be written to the addresses 10 and 10 of the SM is written to the addresses 10 and 21.

Next, the scroll screen write step of the preset memory writes sequentially to an area to be preset when the instruction is a scroll screen of the preset memory. At this time, the operating frequency is twice the frequency when using two 256K DRAM.

That is, the preset scroll screen writing step is sequentially written to an area to be preset using a frequency twice as fast. The total memory area used is from (0, 0) to (253, 63).

The data read step is performed by making a code by opening two registers, each of which stores one data in turn depending on whether the column value is even or odd. The operating frequency is twice that of two 256K DRAMs.

In addition, the register is composed of 4 bit registers, and one code is composed of 8 bits.

Therefore, the data read step reads at twice the frequency of using two 256K DRAMs, and alternately opens two 4-bit registers, each of which stores one data depending on the even or the odd. By making a single code of bits.

In other words, reading from DRAM simultaneously reads from two memories to produce an 8-bit code in which each 4-bit data is the least significant part and the most significant bit part.

Here, an 8-bit code formation process when reading data will be described with reference to FIG. 4.

FIG. 4 (a) is a diagram illustrating an 8-bit code formation process when data is read when two existing 256K DRAMs are used. FIG. 4 (b) is a case where one 1M DRAM according to the present invention is used. 8 is a diagram illustrating an 8-bit code formation process when reading data.

In the case of using two 256K DRAMs, 4 bits of data are output according to addresses 1 and 2 respectively input from the PM and SM memories as shown in FIG. The bit data becomes the most significant bit portion and the least significant bit portion and is output as 8-bit code data through the 8-bit register (1).

Here, addresses 1 and 2 are the same address, and the size of the address is from (0, 0) to (0, 255), (1, 0) to (1, 255) ......... (253, 0) (253,31).

Next, when one or more DRAMs are used, as shown in FIG. 4 (b), when the data is read, 8-bit data is achieved by doubling the frequency according to the address input from the DRAMs of 1M or more. The output 8-bit data is outputted as 8-bit code data through the two 4-bit registers (2, 3), being the most significant bit and the least significant bit.

That is, since data is read using one memory, the frequency is doubled, and the 4-bit register 2 is turned on when the even column data is read by interfacing the DRAM, and the 4-bit register 3 is read when the odd column is read. The 8-bit code data is output by turning on and outputting the data of the even and odd columns sequentially in the 4-bit registers (2, 3), respectively.

Here, the size of the address is from (0, 0) to (0, 511), (1, 0) to (1, 511) ... ... (253, 0) to (253, 63).

As described above, the present invention has an effect that CDEG can be normally implemented without using a large modification to DRAM-related address blocks designed for a plurality of 256K DRAMs but using only one DRAM of 1M or more.

Claims (8)

In a CDG and CDEG system that uses one or more DRAMs to perform graphics in CDEG mode, a data write classification step of classifying data according to an instruction when writing data, and when the instruction is a write font and an exclusive ora font, data to be used in a PM is selected. Writing data to the Even column of the same row and writing SM to the odd column of the same row, and writing an exclusive ora font, and the instructions are scroll screens of the preset memory. In this case, the scroll screen write step of the preset memory that writes sequentially to the area to be preset, and the two registers each storing one data depending on the even or the odd value of the column when reading data alternately CDG, characterized in that it is performed by a data read step that opens a code DRAM how to use the CDEG system. The method of claim 1, wherein the writing and the exclusive ora font writing step is performed at the same frequency as when using two 256K DRAMs. The method of claim 1, wherein the scroll screen writing of the preset memory is performed at twice the frequency of using two 256K DRAMs. The method of claim 1, wherein the data reading step is performed at twice the frequency of using two 256K DRAMs. The method of claim 1, wherein the register is a 4-bit register. The method of claim 1, wherein the code consists of 8 bits. The method of claim 1, wherein the address for writing and reading the data is 9 bits. The method of claim 1, wherein the data consists of 4 bits.