JPS6126085A - Image display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] - (a) Industrial application field The present invention is applied to image display terminals such as personal computers and videotex, teletext receivers, etc., and is used for image display using a bitmap type image memory. Regarding the method.

(b) Conventional technology In each device as described in the introduction, pixels on a display screen such as a CRT, etc.
When displaying images and graphic patterns using a so-called dot map type image memory corresponding to one-to-one image memory, especially when displaying the above-mentioned patterns in color, 3 memory planes are provided,
Each of R, G, and H data (color data) corresponding to pattern data output from a CPU or the like is written into each memory plane.

By the way, conventionally, writing color data to such memory planes involves placing three memory planes in common at the same address specified by the CPU, etc., and performing panning, rotation, switching, etc. for each plane. Each method was done individually. Such a method is described, for example, in Japanese Patent Publication No. 59-3795.

However, in the method described above in which color data is inserted into each memory plane individually, the so-called cycle stealing method (thus, writing to each plane uses the idle time of reading that plane) do it (
Tunchi Communication Society Journal Vol.

67, Nα4, pp. 360-661), there is a limit to speeding up the operation, and it is difficult to speed up the operation when a large number of memory planes are handled or when displaying advanced geometric figures such as captain stems. However, there was a problem in that the operating speed could not be adequately addressed.

Note that C is described above for the case where figures etc. are displayed in color with the specified color, but in addition to this, for example, when displaying in monochrome at the specified a light gradation (hereinafter simply referred to as gradation), The same is true for the case where patterns are displayed with 2R types of colors or gradations, assuming that N memory planes that can store data of 1 bit per pixel are generally used. I can say that.

1'S Problems to be Solved by the Invention The present invention provides a method for displaying images using a bitmap type image memory having N memory planes as described above. The purpose is to perform the overflow in a short time, thereby speeding up the display operation.

2) Means for solving the problems In the present invention, 1. In order to solve the above problems, each of the N memory planes is configured with a group of memory elements that can be written in at least one pixel unit, and N bits are set with data representing 2R types of colors or gradations. A rewritable register is provided, and a means for controlling the operation of writing the output of each bit of this register to a corresponding memory plane according to pattern data, and this control means allows each corresponding memory plane stored in each of the planes to be written. The configuration is such that data can be read out simultaneously.

(e) Operation: By controlling the data filling into each of the memory planes according to the pattern data, a set of data representing the color or gradation set in the register is simultaneously written into each of the planes. As a result, access to the same address in the image memory is completed in one go.

(F) Embodiment The drawing shows a schematic configuration of the essential parts of an embodiment of an image display device using the present invention. This is an example in which color data is written all at once. In the drawing, (1) is C
A display address code generator (2) that derives an address code by obtaining the horizontal and vertical synchronizing signals of the RT display, etc. input a
This is an address selector that switches and derives an embedded (drawing) address code.

Next, (4) is an image memory constituted by RAM, and this memory is accessed simultaneously by the address code output from the selector (2).
It has a third memory plane (4R) (4G) (4B), and each plane has four unit memory elements (M-(M4)) corresponding to the same address. Memory block (BR+) (BN2)...
, (BG+) (BG2)..., (BB+) (BBz
)..., there are many. However, in order to avoid complexity, the figure only shows each memory plane and 62 blocks.

On the other hand, (5) is a 3-bit color setting register, and this register stores color data N-4 representing 8 colors, 1 bit each from the CPU mentioned above, and its R, G, B The arrangement is such that each bit output is commonly applied to the data input terminal (DI) of each storage element in the first to third memory planes (4R) (4G) (4B). In addition, each output terminal (DO) of the corresponding same storage element of each memory block in the first to third memory planes (4R) (4G) (4B) is 4
Bit parallel input shift register (6R06G) (
6B) is connected to the input side.

Further, (7) is a memory controller, which not only switches the Ail address selector 1 but also switches 'M' (]1 level) when the selector is deriving the address code on the CPU side. It is designed to output a memory write signal, and this memory write signal is a 4-bit parallel signal derived from the CPU.
Nantes gate (8) ~ by pixel pattern data
It is gated at 0D, and the output of each of these Nant gates is
The third memory plane (4R) (4G) (4B) is commonly introduced into the third memory plane (4R), (4G), and (4B), and within each plane, it is commonly connected to the write enable terminal (WE) of the corresponding memory element of the same order in each block as shown in the figure. It seems like 111 words are being spoken.

Now, in this embodiment, the CPU now has the image memory (
4), the CPU generates an address code for the image memo 4) corresponding to the display position 1, and gives an instruction to the memory controller (7). Then, this controller (7) affects the display operation.
The selector is switched so that the address code on the CI) U side is derived from the address selector (2) at a timing when the CI U side is not given, and a memory write signal is output at the timing described above. In addition, here, now, the above selector (
2) Address code or image memo output from θ) January 4
) each 7? - The first block in the ring (BR (BG+)
(BI3+) shall be indicated.

Further, the CPU simultaneously derives pattern data for 4 pixels (4 bits) in parallel, and each data is input to a Nant gate (8 bits) with the memory write signal as one input.
) to (111). Therefore, of the pattern data for the above four pixels, only the 21% stitch data (Dl) or 1# (corresponding to characters and figures) and all others are "0'' (corresponding to the background), only the output of the Nant gate 19) becomes 0''. Therefore, in this case, the first block (BR
+ ) (BG+) (24th memory element (M
Only 2) is in the write state.

On the other hand, prior to this operation, the color setting register (5) contains C.
Color data (8) IG representing a predetermined color by PU
ICBl is stored. That is, when displaying a figure represented by pattern data from the CPU in red, for example, color data C% (i5θ) is stored in the register (5) in advance. Therefore, f7i
As mentioned above, the first block (BR+
) Q3G (second memory element (M
2) is in a snoring state, the data (ioo) is written (rewritten) to each storage element.

Next, the second block (B
B2) If the data of the 1st and 3rd pixels of the next 4 pixels of pattern data corresponding to (BG2) (J3B2) are 1", the 1st and 6th 9 in the above 2nd block are This means that the aforementioned color data (100) is embedded into the 6-memory element (+vi+) and (M).

In this way, /f is written to the first to third planes (4R) (4G) (4B) of the image memory (4) one memory block at a time, but this memory block has already been written. Reading is performed by accessing the display address generator (1).

Then, color data for 4 pixels of each block read from the first to third planes (4R) (4G) (4B) through one access are transferred to shift registers (6 techniques) (6G) ( 6B), the data is converted into serial data for each pixel, and then output to a display unit such as a CRT display.

Note that to change the color of the displayed figure pattern, it is better to change the color data stored in the color setting register (5), but in the above embodiment, for the purpose of high-speed processing, each brain of the image memory Since writing is performed for four pixels in one block, in order to change the color of each of the four pixels, the write operation must be performed four times to the same memory block. However, since it is extremely rare that it is necessary to change the color on a dot-by-dot basis in the middle of a graphic pattern, the method C described above is not particularly inconvenient. Rather, in the case of the present invention, it is possible to directly change only the data to be changed among the data of the plurality of pixels, so it is possible to shorten the access time when partially changing the display pattern, and it is more convenient to do so. Good. Of course, if it is not necessary to access at such high speed, the first to third memory planes may be accessed one pixel at a time using one address.

Furthermore, in the embodiment described above, the memory write number rH to the image memory is gated based on the pattern data.
In addition to this, it is also possible to configure the element selection signal of the image memory to be controlled by the pattern data.

(g) Effects of the Invention According to the 1flj i4 table display method of the present invention, N memory planes in the image memory can be accessed simultaneously, compared to the conventional method I which accesses i planes for each plane. This has the advantage that the access time can be significantly shortened, and the access time remains constant regardless of the increase in the number of memory planes.

[Brief explanation of the drawing]

The drawing is a block diagram showing a main part of an embodiment of a display device to which the image display method of the present invention is applied. (1)...Display address generator, (2)...Address selector, (4)...Image memory, (4R) (4G
)(4B)...Memory plane, (5)...Color setting register, (6 wands) (6G) (6B)...Shift register, +71...Memory controller, (8) to (11
1... Nantes Gate.

Claims (1)

[Claims] (1) Has N (an integer greater than or equal to 2) memory planes and 2
In a method for displaying an image pattern using a bitmap image memory storing data representing ^N types of colors or gradations, the memory plane is divided into at least one
It is composed of a group of memory elements that can be written in pixel by pixel, and includes an N-bit rewritable register in which data representing the 2^N types of colors or gradations is set, and the output of each bit of this register is means for controlling the writing operation to the corresponding plane of the image memory according to the pattern data, and by simultaneously reading the corresponding data in each plane, the image pattern is selected from among the 2^R types. An image display method that can display colors or gradations.