JPS6231886A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a display control device), and particularly to a display control circuit suitable for reduction in cost and compactness.

[Background of the invention]

A block diagram of a conventional character display control device is shown in FIG. 5, and control timing of the conventional device is shown in FIG.

In FIG. 5, 1 is the MPU, 21 is the MPU address bus, 22 is the MPU f-tabus, and 2 is the CR for display control.
This is a TC (cathode ray tube controller). CRTC2 has a CRTC memory address n for sequentially displaying characters,
A CRTC raster address 8 for vertically scanning a character pattern in a character generator memory 5, which will be described later, is output. The address bus selector 6 switches the character code memory address 4 input to the character code memory 4 between the MPU address bus 21 and the CRTC memory address n. In other words, MPU 1 uses character code memory 4 when changing display contents, etc.
When accessing, go to the MPU address bus 21 side.

When performing other normal display, the display is switched to the CRTC memory address 23 side. The character generator memory 5 stores character patterns of various characters. 6 is a parallel/serial data converter which creates serial display data 29; 7 is a display timing generator that generates various timing signals.

This operation will be explained below with reference to FIGS. 5 and 6.

In the conventional character display control device, the CRTC memory address 23 selects the character code to be stored in the character code memory 4.

The selected character code becomes the 1 display character code.

CRTC) i memory address 23 c. When the address bus select signal 31 is "L6w', it becomes valid at the character code memory address. When the display character code is read from the character code memory 4, it is latched by the latch circuit 9, and the character generator memory address It will be 27.

Character generator memory address 27 and CRTC
The character font selected by RaskAddress is displayed in parallel display data.

Parallel display data 4 is converted to serial display data 2 under the control of display data parallel/serial conversion control signal 33.
It becomes 9. The serial display data 29 is sent to the CRT 8 to display characters.

The character code memory 4 is a memory that stores the character code of the character to be displayed, and since the character code read from the character code memory 4 becomes the address of the character generator memory 5, the character code memory and the character generator memory are It was impossible to configure the memory elements with the same memory elements.

[Purpose of the invention]

An object of the present invention is to reduce the number of parts of a display control device for character display, in other words to provide a display control device that makes this possible.

[Summary of the invention]

In recent years, random access memory has increased in storage capacity and
Access times are becoming faster, and it can be expected that the current trend will continue in the future.

If a memory with a fast access time is used in the display control device, the display memory can be accessed twice within the time required to display one character.

The character code and the character generator are stored in the memory element of the same package, the character code is accessed in the first half of the cycle to display one character, the character generator address signal is created from the character code in the second half of the cycle to display the character, and the character font is created. I read it out.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG. 1 below. Further, the control timing of this embodiment is shown in FIG.

In FIG. 1, 10 is a conventional character code memory 4.
This is a character code and character generator 4 memory in which the character generator memory 5 and the character generator memory 5 are the same memory. Furthermore, in the past, the output of the latch circuit 9 was given to the character generator memory 5, but in this embodiment, the difference is that the output is given to the character code & character generator memory 10 via the address bus selector 3. There is. The operation will be explained below.

When the address bus select signal 31 is "Low" and the character code select signal U is "Low", the CRTC memory address 23 is selected as the character code and character generator memory address 25. Further, when the address bus select signal 31 is "Low" and the character code select signal is "High", the character generator memory address 27 and the CRTC raster address are selected as the character code and character generator memory address section.

When the CRTC memory address 23 is selected as the character code and character generator memory address 4, the character code in the character code memory is read out from the character code memory and character generator memory 10 and becomes valid on the character code and parallel display data bus 30. . The character code latch signal 32 causes the latch circuit 9 to latch the character code and becomes the character generator memory address 27.

In synchronization with the character code latch timing, the character code select signal 34 becomes "H x N".
Character generator memory address 27 and CRTC
Select raster address 8 as character code & character generator memory address 25. As a result, the character code table character generator memory 1
The character font in the character generator memory is read from 0 and becomes the character code & parallel display data 30.

The parallel display data is converted into serial display data 29 and sent to the CRT 8 as in the conventional example.

FIG. 3 shows an example in which Kanji characters can be displayed in an embodiment of the present invention.

Character code table Character generator memory 0
When the kanji code is read from the kanji font generator memory, the display kanji font is read from the kanji font generator memory. The character font selector selects a kanji font under the control of the character font selection signal 35 at the timing when kanji should be displayed. The kanji font is converted into serial display data 29 in the same way as in the previous embodiment.

FIG. 4 shows an example of memory allocation of the character code clear character generator memory IO.

- As an example, if the character 7 ont is 8X*8 dots horizontally, 25
If it is 6m, 256 bytes of memory will be required. Also, if the number of characters displayed on a CRT a is 40 characters horizontally x 25 lines vertically, then there are 1000 characters, and if each character is represented by 1 byte, it is 10 characters.
00 bytes are required. ◎Character code & character generator memory 10, for example, Hitachi HM611
If a static RAM of 6 is used, the capacity of this memory is 2048 bytes i, so the first half 1024
The bytes, ooooH to 03FFH, are placed in the character code area 41, and the second half, 0400H to Q41FH, is 25.
It is preferable to allocate 6 bytes to the character generator area 42 and the remaining osooh to 07FFH to the extension area 43.

Note that the memory capacity and memory allocation may be changed as appropriate depending on the system. Alternatively, a dynamic RAM may be used as the character code table character generator memory 10.

The above is a case where the character font is a general alphanumeric character or kana, but the present invention can also be applied to a case where these characters and kanji which require a large memory capacity are displayed in a mixed manner.

According to the present invention, by giving the character generator memory address n as an address for accessing the character generator stored in the character code table character generator memory 10, the character code memory 4 and the character generator memory 5, which were required in the conventional example, can be used. It is possible to integrate and replace the character code table character generator memory lO,
This has the effect of reducing the number of display memories.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the number of memories in a display control device, and as a result, it is possible to reduce the number of parts constituting one display control device, and to make the entire system compact. It is possible to realize price reduction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a timing chart showing control timing of one embodiment of the present invention, and FIG. 3 is a block diagram showing the control timing of one embodiment of the present invention. 4 is an explanatory diagram showing an example of memory allocation of the character code table character generator memory. FIG. 5 is a block diagram showing a conventional display control circuit. FIG. 6 is a timing chart showing control timing of a conventional display control circuit. 1...MPU 2...CRTC5...
・Address bus selector 4...Character code memory 5...Character generator memory 6...Parallel/serial data converter 7...Display timing generator 8...CRT? ...Latch circuit 10.
・Character code table Character generator memory 21...hr p v address bus 22,..., MPU data bus 23...CRTC memory address 24...CRTC raster address Kuzu...Character code memory address 26...Character Code bus correction...Character generator memory address bus...Hararel display data bus 29...Serial display data 30...Character code & parallel display data bus

Claims (1)

[Claims] Cathode ray tube controller (hereinafter referred to as C) that controls the display address
(referred to as RTC), a character code memory that stores a display character code accessed by the CRTC, a character generator memory that stores a character font selected by the character code read from the character code memory, and a character generator memory that stores the character font selected by the character code read from the character code memory, and displays the above-mentioned character. In a display control device comprising a cathode ray tube (hereinafter referred to as CRT), the character code memory and character generator memory are configured as a character code/character generator memory comprising the same memory element, and the A display control device comprising an address signal obtained by multiplexing addresses and using the address signal as an address of the character code/character generator memory.