JPS5937510B2 - Dot pattern generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dot pattern generation circuit for a beam progressive scanning cathode ray tube character display device that displays characters in a dot pattern format.

In a character display device using a cathode ray tube (hereinafter abbreviated as CRT), one line is composed of dozens of beams (hereinafter referred to as rasters) that scan the CRT. rasters are assigned as constituent elements between the upper and lower rows. To display characters on this type of display device, a method is used in which dot patterns corresponding to the characters to be displayed are read out from a memory called a character generator that stores the dot patterns of all displayed characters, and outputted as a video signal to a CRT. . When reading a dot pattern from a character generator using this method, the conventional device directly accesses the character generator using the display character code and raster counter as an address, as shown in FIG. Therefore, for example, if one line consists of 32 rasters, of which the character components are 18 rasters, dot patterns called blanks should be stored in the character generator for the remaining 14 rasters between the lines. This has the disadvantage that the efficiency of the character generator is reduced. The present invention uses a method in which a display character code is input to an address conversion table, and the character generator is accessed using an address obtained by calculating the converted address and the output of a raster counter. An object of the present invention is to provide a dot pattern generation circuit that eliminates the drawbacks of the above.

According to the present invention, in a beam sequential scanning cathode ray tube character display device, there is provided an address conversion circuit having a storage start address (storage end address) in a character generator of a dot pattern corresponding to each display character code, and an address conversion circuit for the address conversion circuit. An arithmetic circuit that adds the output of the circuit and the output of the raster counter (an inverter that inverts the output of the raster counter and subtracts the output of the inverter from the output of the address conversion circuit), and a character generator that is accessed using the result of the operation. , a shift circuit that shifts the output of the character generator, a comparison circuit that compares the output of the raster counter with a predetermined value, and a gate circuit that gates the output of the comparison circuit and the output of the shift circuit. A dot pattern generation circuit is obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a first embodiment of the invention.

In FIG. 2, D3, D2, Dl, DO are each bit constituting the display character code, and the address conversion circuit 10
connected to the input terminal of The address conversion circuit 10 has a storage start address within the character generator of a dot pattern corresponding to each display character. The output of this address conversion circuit is connected to one input terminal of the adder circuit 20. The other input terminal of the adder circuit is the raster counter output RAS3, RAS2, RAS1,
RASO is connected. The output of the adder circuit is connected to the input terminal of a character generator 30, and the output of the character generator is connected to the input of a shift circuit 40. The shift circuit 40 converts the parallel input dot patterns into series using a clock pulse CLK synchronized with the display section of the CRT, and supplies the dot patterns to one input terminal of the gate circuit 50. The other input terminal of the gate circuit is connected to the output terminal of the comparison circuit. The comparator circuit obtains "1" as an output when the output of the raster counter is equal to or smaller than "1001".In other words, the dot pattern is used as a video signal only when the raster counter is in the character display area, and the dot pattern is displayed on the display section. otherwise, it supplies 10'' as a video signal no matter what the dot pattern is. A second embodiment of the invention is also shown in FIG.

Here, D3, D2, Dl, and DO are bits constituting a display character code, and are connected to input terminals of the address conversion circuit 10. The address conversion circuit 10 has dot pattern characters corresponding to each display character.
It has the storage end address within the generator. The output of this address conversion circuit is connected to one input terminal of the subtraction circuit 20. The other input terminal of the subtraction circuit receives the raster counter outputs RS3, RS2, RSl,
A signal obtained by inverting RSO through inverters 71, 72, 73, and 74 is connected. The output of the subtraction circuit is connected to an input terminal of a character generator 30, and the output of the character generator is connected to an input of a shift circuit 40. The shift circuit 40 converts the parallel input dot patterns into series using a clock pulse CLK synchronized with the display section of the CRT, and supplies the dot patterns to one input terminal of the gate circuit 50. The other input terminal of the gate circuit is connected to the output terminal of the comparison circuit. The comparison circuit obtains "1" as an output when the output of the raster counter is equal to or smaller than "100r." In other words, only when the raster counter is in the character display area,
The dot pattern is supplied to the display section as a video signal, and otherwise, "O" is supplied as the video signal, regardless of the content of the dot pattern.
As described above, the present invention has the effect of increasing the efficiency of the character generator by indirectly accessing the character generator.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional dot pattern generating circuit, FIG. 2 is a circuit diagram showing a first embodiment of the present invention, and FIG. 3 is a circuit diagram showing a second embodiment of the present invention. It is a circuit diagram. 10...Address conversion circuit, 20...
Addition circuit, 30...Character generator,
40...Shift circuit, 50...Gate circuit, 60...Comparison circuit, 71-74...
...Inverter.

Claims (1)

[Claims] 1. A character generator that stores a dot pattern of a display character, an address conversion circuit that converts the character code of a display character into a first address, and a second address that specifies the row or column of the first address and the dot pattern. an arithmetic circuit that accesses the character generator with an address; a circuit that converts the dot pattern read from the character generator into a video signal; and means that compares the second address with a predetermined address value. and gate means for prohibiting transmission of the video signal based on the comparison result of the comparison means.