KR890006505Y1 - Moniter mode conversion circuits in graphic - Google Patents

Abstract

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Description

Monitor mode conversion circuit in graphics

1 is a memory map in normal mode.

2 is a memory map in high resolution mode.

3 is a block diagram according to the present invention.

4 is a detailed circuit diagram of FIG. 3 according to the present invention.

* Explanation of symbols for main parts of the drawings

10: CRT controller 20: conversion circuit

30: Video RAM

The present invention relates to a mode conversion circuit of a monitor in graphic character processing of a personal computer, and in particular, a high resolution Hangul mode having 400 lines and a general mode having 200 lines are freely available as one hardware. A mode switching circuit of a monitor that can be selected and displayed.

In general, in order to display certain characters and images on the monitor, a memory having the same size as that of the monitor must be designed to correspond to 1: 1. Therefore, one dot on the monitor corresponds to one bit on the memory during character processing.

In general, the data structure of displaying one character in a general mode that can process English is 8x8 dots.

However, currently used business computers require a high-resolution screen to display Korean characters, and most personal computers have a resolution of 640 × 200 pixels, which makes the Hangul process unsuitable.

As described above, the number of dots for providing a 640 × 200 line is 640 × 200 = 128000 dots. As described above, one bit corresponds to one dot, and a unit of one byte that can be processed in graphics. Since is 8 bits, memory capacity of 128000 ÷ 8 = 16000 bytes (16K bytes) is required. For this purpose, the video RAM can be designed into two segments (SEGO, SEG1) so that 8K bytes can be divided and stored as shown in FIG. In other words, the segment (SEGO) can be designed to be 0000H-1FFFH. The value for this is as follows.

The value of 1FFFH is a hexadecimal value as a hexadecimal value, which is [(1 × 16 ³ ) + (15 × 16 ² ) + (15 × 16) + (15)] + 8191, so that sufficient 8K bytes are obtained. It can be seen. The segment SEG1 also has a value up to 2000H-2FFFH, which is the same size as the segment SEG1, and thus becomes 8K bytes, and the two segments SEGO-SEG1 total 16K bytes. When the data on the segment SEGO-SEG1 is read and displayed by the monitor, the first line reads the value of the segment SEGO every time according to the sequential scanning order of the monitor, and the value of every second line segment SEG1 is read. Read and scan on the monitor. In this case, it can be seen that in a monitor capable of displaying 25 lines of characters, one character takes 8 bits on the vertical line side, thus becoming 200 lines required for the calculation of 8 × 25 = 200. However, the 640 × 200 mode can be used to process Hangul in the same monitor, but the resolution of the Hangul is not enough and 25 lines cannot be displayed on the same monitor. For this reason, it is well known that Hangul uses 640 × 400 to use 16 × 16 dots.

Thus, calculating one monitor 16 bits x 25 lines, we can see that 400 lines are provided. Thus, 640 × 400 = 256,000.

The dot corresponds to a bit and 1: 1, and thus 256,000 bits, and since 1 byte capable of processing Korean characters is 16 bits, more than twice as much memory capacity (32K bytes) required for the 640x200 mode is required. This can be illustrated as in FIG.

FIG. 2 shows that the sum of each segment (SEGO-SEG3) into 8K bytes results in 32K (8 × 4 = 32) bytes by the same calculation method as in FIG. In general, 50HZ or 60HZ is used as the frame frequency for displaying one screen on a monitor. 50HZ is used in the United States and 60HZ is applied in Korea. For example, 200 lines in 640 × 200 mode have enough margin (α = 110) and 200 + 110 = 310 lines.

And 400 400 in 640 × 400 mode with enough spare (α = 50) to say 400 + 50 = 450 lines

As described above, it can be seen that the horizontal frequency varies depending on the mode.

However, since most monitors have a fixed horizontal frequency, they need to be replaced depending on the mode or the corresponding monitor whose horizontal and vertical frequencies are converted according to the mode.

In this case, however, it was difficult to develop a monitor, and there was a need to change the monitor frequently depending on the mode.

Therefore, an object of the present invention is to provide a circuit that can normally use the same monitor in the Hangul mode as well as the normal mode.

Another object of the present invention is to provide a high-performance system that is easy to apply the existing software to a single hardware and can perform mode conversion from time to time.

Therefore, the present invention for performing the above object outputs the row count horizontal, vertical synchronization signal, blanking signal, 14-bit refresh address and row address signal for the character generator, and also for scrolling and paging. A conversion circuit for generating an address value according to a mode conversion in accordance with a mode selection signal by a CRT controller CRTC having a function and a signal output from an internal row address signal generation counter of the CRT controller; It is composed of a video RAM having a capacity corresponding to the size of the CRT and 1: 1 so that the resolution is matched according to the normal mode and the Hangul mode by the output conversion address signal of the conversion circuit. do.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram according to the present invention, a CRT controller 10 for outputting a row counter horizontal and vertical synchronization signal, a blanking signal, a 14-bit refresh address and a row address signal for a video data buffer, and the CRT. A conversion circuit for outputting a conversion address value for conversion of Korean mode of high resolution 400 lines and normal mode of 200 lines by a bank selection row address output from the controller 10 and a mode selection signal input through the mode selection stage 21. And a video RAM in which each pixel is stored in a 1-bit memory so that data corresponding to CRT and 1: 1 can be stored according to the normal or high-resolution Hangul mode by the conversion address generated by the conversion circuit 20. 30).

Therefore, when the embodiment of the present invention is briefly described based on the configuration of FIG. 1 described above, a row address signal is output from the CRT controller 10 to scan the memory maps of FIG. 1 and FIG. The address signal is input to the conversion circuit 20, and when the normal and Hangul mode selection signals are input through the mode selection stage 21, the conversion circuit 20 selects a bank of the video RAM 30; The selection logic signal scans each segment (SEGO-SEG3) of the video RAM 30 configured as shown in FIG. 2 as a second address line in sequence. In the normal mode, the same segment is scanned twice.

In the high-resolution 400-line mode, " high " is applied to the mode selection stage 21, and a conversion address is generated in the conversion circuit 20 by the row address signal output from the CRT controller 10. From the segment SEGO of 30), one character is displayed by scanning the segment SEGO-SEG3 sequentially in the order of the scanning lines and scanning 16 times. Therefore, as one hardware (monitor) to be displayed, it is possible to normally process different modes, that is, a high resolution Hangul mode and a normal mode. The synchronization signal output terminal V / Hsync generates horizontal and vertical synchronization signals corresponding to mode selection.

The CRT controller 10 corresponds to "MC6845" of Motorola, a US semiconductor company, and uses the same reference numerals as in FIG. 3.

The output row address signals RA0 and RA1 of the CRT controller 10 are output through the first and second bank select terminals SA0 and SA1. The first bank select terminal SA0 is input to the NAND gate NA2, the second bank select terminal SA1 is input to the NAND gate NA1 and the AND gate AN1, and the mode select terminal 21 is input. The input signal of is inverted through the inversion gate (N1) is input to the NAND gate (NA1), while the NAND gate (NA2) and AND gate (AN1) is configured to be input directly, the output of the NAND gate (NA1, NA2) The portion configured to be input to the input terminal of the NAND gate NA3 corresponds to the conversion circuit 20 in FIG. The output terminal of the NAND gate NA3 of the conversion circuit 20 is connected to the first address line RA2 of the video RAM 30, and the output terminal of the AND gate AN1 is the second address line of the video RAM 30. It is connected to the video RAM 30 via EA13. The video RAM 30 uses the same reference numerals as in FIG. 3.

Therefore, a specific embodiment according to the present invention will be described in detail with reference to FIGS. 1, 2, and 4, and the low address of the CRT controller 10 for scanning the memory maps of FIGS. Whenever the (RA0RA1) signal is changed, the bank selection address values of the video RAM 30 as shown in Table 1 are output to the first and second bank selection stages SA0 and SA1.

At this time, this conversion sequentially selects the memory map segments SEGO-SEG3 of FIGS. 1 and 2, for example, the row address RA0 = low of the CRT controller 10 and the row address RA1. The line first bank selection stages SA0 and SA1 are in the same state when outputting "low".

At this time, in the Korean 400-line mode, the mode selection stage 21 becomes “high” and is input to the NAND gate NA1 as “low” through the inverter N1. Then, "low" of the first bank selection stage SA0 is input to the NAND gate NA2 so that the AND gates NA1 and NA2 output are "high" and the AND gate AN1 output is "low". Since the output of the NAND gate NA3 is "low" by the "high" output of the NAND gates NA1 and NA2, the first and second address lines EA12 and EA13 of the video RAM 30 are "low". do. At this time, every first line 1st is scanned in Table 1 in the first segment SEG0 of FIG. When the first bank selection stage SA0 = high and the second bank selection stage SA1 = low, the NAND gate NA1 is "high" and the NAND gate NA2 is "low". As shown in Table 1, the first address line EA12 is "high", the AND gate NA1 is "low", and the second address line EA13 is "low".

Every second line 2nd is scanned in the second segment SEG1 of FIG. Row address RA of CRT controller 10 ) Is "low", and the low address RA1 is "high", the first bank selection stage SA0 is "low", and the second bank selection stage SA1 is "high", and the NAND gate NA1, ( The output of NA2) becomes "high", the NAND gate NA3 output becomes "low", and the output of the AND gate AN1 becomes "high" so that the first address line EA12 of the video RAM 30 is Since the "low" and second address lines EA13 become "high", every third (3th) line is scanned in the third segment SEG2 of FIG. 2 as shown in Table 1 above.

Low address of the CRT controller 10 (RA ) Is " high ", and the low address RA1 is " low ", the first bank selection stage SA0 = high and the second bank selection stage SA1 = high.

Subsequently, the output of the NAND gate NA1 is "high", the output of the NAND gate NA2 is "low", and the output of the NAND gate NA3 is "high", and the output of the AND gate AN1 is also "high". Since the first and second address lines EA12 and EA13 of the video RAM 30 become "high", respectively. At this time, scan every fourth (4th) line from the fourth segment (SEG3).

In the normal 200-line mode, when "low" is input to the mode selection stage 21 and outputs as "low" at the row addresses RA0 and RA1 of the CRT controller 10, the first bank selection stage SA0 ) = "Low" Since the second bank select stage SA1 is "low", the outputs of the NAND gates NA1 and NA2 are "high" so that the NAND gate NA3 output becomes "low" and the AND gate. (AN1) It is also " low " so that the first and second address lines EA12 and EA13 of the video RAM 30 are output as shown in Table 1 above.

When the outputs of the first and second bank selection terminals SA0 and SA1 are "high" and "low" according to the outputs of RA0 and RA1 of the CRT controller 10, the outputs of the NAND gates NA1 and NA2 are "high". The output of the NAND gate NA3 is " low ". On the other hand, since the output of the AND gate AN1 also becomes "low", the first and second address lines EA12 and EA13 of the video RAM 30 become "low", so that the first segment SEGO of FIG. It's like scanning.

When the outputs of the first and second bank selection stages SA0 and SA1 are "low", "high", or both "high", the output of the NAND gate NA1 is "low", and the output of the NAND gate NA2 is " High ", and the output of the NAND gate NA3 is always" high ". Since the output of the AND gate AN1 is "low", the first address line EA12 of the video RAM 30 is "high", and the second address line EA13 is "low". The second 2nd segment SEG1 of the figure is scanned twice.

Accordingly, since the first and second address lines EA12 and EA12 of the video RAM 30 change twice according to the change of the first and second bank selection stages SA0 and SA1, the address entering the video RAM 30 is changed twice. Is repeated as 00,00,01,01, so that the value of the segment like FIG. 1 is scanned twice in FIG. 2 to process the display in the normal mode. Since the signals of the row addresses RA and RA1 of the CRT controller 10 are related to the vertical and horizontal synchronous signals for controlling the monitor, in order to maintain the synchronization signal at a constant value (when using one monitor), It is maintained in a constant sequence as shown in Table 1.

In the 640 × 200 mode, the Vsyne signal is 50 HZ and the HSyne signal is 15.5 KHZ in the 640 × 200 mode through the vertical / horizontal synchronization stage (H / Vsyne) of the CRT controller 10. In 640 × 400 mode, Vsyne is 50HZ and Hsyne signal is 22.5KHZ.

As described above, it is possible to operate modes with different resolutions (different memory maps) under the same hardware conditions, so that normal display function is possible in normal mode as well as high resolution Korean. And the vertical / horizontal synchronization is kept constant, which has the advantage of improving work efficiency in use.

Claims (2)

The CRT controller 10 which outputs the character generation row counter, the vertical synchronization signal, the blanking signal, the memory buffer address and the row address signal, and each pixel are 1-bit memory. In the system having the corresponding video buffer video RAM 30, the high-resolution 400-line and 200-line general mode conversion is performed by the output row address signal of the CRT controller 10 and the input signal of the mode selection stage 21. And a conversion circuit (20) configured to scan an address value according to the input into the video RAM (30). The NAND gate of claim 1, wherein the conversion circuit 20 connects the first and second bank selection terminals SA0 and SA1 to the row address terminals RA0 and RA1 of the CRT controller 10. And an input terminal of the AND gate AN1, and a mode selection terminal 21 is directly connected to the input terminals of the NAND gate NA2 and the AND gate AN1, and an inverter N1 from the mode selection terminal 21. ) Is connected to the input terminal of the NAND gate (NA1), the input terminal of the NAND gate (NA3) is connected to the output terminal of the NAND gate (NA1, NA2), and the NAND gate (NA3) and the AND gate (AN1) The output mode of the monitor mode conversion circuit for graphics, characterized in that the video RAM (30) is connected to the first and second address lines (EA12, EA13).