JP3005220B2 - Scanning display controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning display device, and more particularly, to a system for reading and writing speed of a memory, that is, a memory speed (access speed), a memory cost, a display color and the like. The present invention relates to a scanning display control device capable of flexibly adapting to characteristics. [Prior Art] As a conventional memory access method, for example, in one character cycle (for example, 8 dots), the first four
In some cases, dots are assigned to access to a VRAM (video memory) by the CPU, and the latter four dots are assigned to access to a character generator of the VRAM. According to this memory access method, the writing of data to the VRAM and the reading of data from the VRAM by the CPU, and the reading of the display pattern by the access of the character generator are performed in a time-division manner. It is possible to prevent flickering of the screen caused by, for example, writing data to the VRAM during the operation. [Problems to be Solved by the Invention] However, according to the conventional memory access method, the access timing is fixed such that the latter four dots of one character are allocated to the access of the character generator. The access timing cannot be changed according to the memory speed. In a personal computer or the like, the processing time per pixel greatly changes from 40 ns to 139 ns, for example, depending on the screen resolution.
If the access timing is fixed, the high-speed memory will not be able to take full advantage of the characteristics of the memory, and the low-speed memory will not be able to be used even for low-speed memory. Occurs. [Means for Solving the Problems] Accordingly, an object of the present invention is to provide a scanning display control device capable of setting a dot width as a memory access time according to a memory speed. Another object of the present invention is to provide a scanning display control device capable of changing the access timing of the memory according to the memory speed. Another object of the present invention is to provide a scanning display control device which can flexibly correspond to a memory speed. A first area of the image memory is accessed based on the raster signal, and an address signal of a second area of the image memory in which a pattern signal is stored is read from the first area, and based on the read address signal A scanning-type display control device that accesses the second area of the image memory, reads the pattern signal from the second area, and displays a pattern on a screen based on the read pattern signal; A storage unit having data of a dot width as an access time of a memory; and accessing the first and second areas to transfer data between a unit outside the image memory and the first and second areas. Performing a first access operation, a second access operation for accessing the first area and reading the address signal from the first area; And the allocation of the dot width as the access time within one character cycle of the third access operation for accessing the second area and reading the pattern signal from the second area is read from the storage means. A dot width setting circuit that determines the pattern based on the dot width data as the access time; and executes the first to third access operations based on the allocated dot width as the access time to change the pattern. There is provided a scanning display control device comprising a control unit for displaying on the screen. [Embodiment] Hereinafter, a scanning display control device of the present invention will be described in detail. FIG. 1 shows an embodiment of the present invention, in which an original signal output from an oscillation circuit 1 is divided by a frequency dividing circuit 2 into multiple stages.
A clock signal having a predetermined frequency is input to a dot width setting circuit 3 for setting a dot width as a memory access time. The dot width setting circuit 3 is connected to a memory width register 4 for setting a memory width as contents according to a memory access speed. Based on the memory width, the VRAM area 5a and the VRAM area 5a in one character cycle of 8 dots are set. A timing for accessing the VRAM 5 having the character generator area 5b is allocated. When the timing to access VRAM5 is allocated,
The address selector 6 determines whether the VRAM 5
And access to VRAM5. The access at this time is performed to an address specified by the CPU address signal 7, the DMA address signal 8, and the CG (character generator) address signal 9. CG address signal 9
When the display data is read from the character generator area 5b of the VRAM 5, the display data is latched by the data latch circuit 10. The address in the VRAM attribute table of the character of the virtual screen is shown in the VRAM area 5a of the VRAM 5 (32 × 32 characters). Each character is composed of, for example, 8 × 8 pixels. FIG. 2A shows the memory width register 4 from the lower order.
VM bit (2 bits), SM bit (2 bits), SCREEN
Bits (3 bits) and CM bits (1 bit). Among them, the VM bit is used to set a dot width as an access time determined according to a read / write speed (memory speed) of the VRAM 5, and a VRAM attribute table and a character generator during a horizontal display period are set. Access, DMA and C
What dot width, for VRAM access by PU (MPU)
That is, the access time is set. Also, the SM bit defines how many dot widths the sprite generator accesses, the SCREEN bit sets the number of characters in the X and Y directions of the virtual screen,
The CM bit selects CG0 or CG1 when the VRAM dot width is 4 dots. When the bit is “0”, CG0 is selected, and when the bit is “1”, CG1 is selected. FIG. 2 (b) shows the access timing of the VRAM 5 allocated by the dot width setting circuit 3 in one character cycle (8 dots) based on the contents of the VM bit of the memory width register 4. Among them, "MPU" is access to VRAM5 by CPU, "VRAM" is access to VRAM attribute table based on the address of VRAM area 5a of VRAM5, "CG0"
And "CG1" indicate that the character generator area 5b of the VRAM 5 is accessed based on the address given by accessing the VRAM attribute table. FIG. 3A shows a VRAM attribute table,
The access is made by the address of the VRAM area 5a of the VRAM 5 in FIG. 1, and the pattern number of the character generator is specified by the lower 12 bits of the character code, and the area color code is specified by the upper 4 bits. This VRAM
The attribute table is not shown in FIG. 1, but is stored in a predetermined area of the VRAM 5. FIG. 3B shows a character generator in the character generator area 5b of the VRAM 5 shown in FIG. 1, and one character has four faces of 8.times.8 dots CH0, CH1, CH2, CH3.
A pattern of one character is defined by a total of 16 words, 8 words for CH0 and CH1, 8 words for CH2 and CH3. The address of each character is determined by the head address A ₀ , A _1, ... Of the plane CH ₀ , and this head address is defined by the character code of the VRAM attribute table in FIG. Hereinafter, the operation of the present invention will be described. When the horizontal display of raster number 0 starts, the dot width setting circuit 3 searches the memory width register 4 for the VM bit. Now, assuming that the VM bit is "00", FIG. 2 (b)
Accordingly, the dot width as the access time when accessing the VRAM 5 becomes “1”. Therefore, at the first dot in one character cycle (8 dots), the address selector 6 supplies the CPU address signal 7 to the VRAM 5 to transfer data between the CPU and the VRAM 5, and then, at the second dot, the CG address The address 9 of the VRAM area 5a is accessed by the signal 9. At this time, the VRAM attribute table at address “0” (FIG. 3A)
And check the character code and CG color. Next, in the third and fifth dots except for the fourth dot, data transfer is performed between the CPU and the VRAM 5 in the same manner as in the first dot, and the sixth dot is checked by the second dot. The character generator in the character generator area 5b is accessed based on the character code. At this time, the pattern number determined by the character code checked by the second dot is the CG address signal 9, which is used as an address for CH0 and CH1.
Read the display data of the two surfaces. Next, at the seventh dot,
CPU and VRAM5 as well as 1st dot and 5th dot
After the data transfer is performed, the display data of the remaining two sides CH2 and CH3 of the character generator are read out by the same address signal 9 at the eighth dot to form one character pattern on the four sides. Then, the data is latched in the data latch circuit 10. That is, the two faces CH0 and CH1 are read by the sixth dot “CG0”, and the other two faces CH2 and C1 are read by the eighth dot “CG1” based on the same address.
Read H3. The four planes CH0 and CH thus read
A pattern is formed by superposition of 1, CH2 and CH3. Based on the latched data, display of the address 0 of the CRT (not shown) is performed. That is, the display area of raster number 0 at address 0 of the CRT is displayed by eight pixels located in the horizontal direction. This display shows four 8 × 8 planes CH0, CH1, CH2, CH3 read from the character generator area 5b.
Is performed by a combination of data of 8 pixels corresponding to each raster number 0. The color is determined by the CG color in the VRAM attribute table. The subsequent horizontal display of raster number 0 is repeated in the same manner as described above, and the process sequentially shifts to the lower raster. Also, if the VM bit of the memory width register 4 is “01”, “1”
If it is "0" or "11", as shown in FIG. 2 (b), the access to the VRAM 5 is performed at a dot width as the access time of "2", "2", or "4" according to the content. Will be The content of this VM bit may be set based on the memory speed of VRAM5. When the VM bit is “11” and the dot width as the access time is “4”, the CM bit of the memory width register 4 is “0” from the fifth dot to the eighth dot.
As a result, CG0 is executed first, and then the CM bit is set to "1".
Executes CG1. [Effects of the Invention] As described above, according to the scanning display control device of the present invention, the dot width setting circuit sets the access time for accessing the first and second areas of the image memory based on the data of the storage means. First access operation to the first and second areas for performing data transfer between the unit outside the image memory and the first and second areas by setting the dot width of For reading address signal from
Is configured to determine the allocation within one character cycle of the second access operation to the second area and the third access operation to the second area for reading the pattern signal from the second area. Therefore, it is possible to flexibly cope with a change in the speed of the image memory, and to fully utilize the characteristics of the image memory while suppressing the load on the CPU.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view showing an embodiment of the present invention. FIGS. 2A and 2B are explanatory diagrams showing a change in a memory width register and a dot width. FIGS. 3A and 3B are explanatory diagrams showing a VRAM attribute table and a character generator. Description of reference numeral 1 ... Oscillation circuit 2 ... Frequency dividing circuit 3 ... Dot width setting circuit 4 ... Memory width register 5 ... VRAM 5a ... VRAM area 5b ... Character generator area 6 ... Address selectors 7 and 8 , 9 ... address signal 10 ... data latch circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 1/00 G06F 13/00 G09G 5/00 G06F 12/00

Claims (1)

(57) [Claims] A first area of the image memory is accessed based on the raster signal, and an address signal of a second area of the image memory in which a pattern signal is stored is read from the first area, and based on the read address signal A scanning-type display control device that accesses the second area of the image memory, reads the pattern signal from the second area, and displays a pattern on a screen based on the read pattern signal; A storage unit having data of a dot width as an access time of a memory; and accessing the first and second areas to transfer data between a unit outside the image memory and the first and second areas. Performing a first access operation, a second access operation for accessing the first area and reading the address signal from the first area; And the allocation of the dot width as the access time within one character cycle of the third access operation for accessing the second area and reading the pattern signal from the second area is read from the storage means. A dot width setting circuit that determines the pattern based on the dot width data as the access time; and executes the first to third access operations based on the allocated dot width as the access time to change the pattern. A scanning display control device, comprising: control means for displaying on the screen.