KR880001082B1 - Low table adressing method - Google Patents

Abstract

No content.

Description

Low Table Addressing Method Using Reset Function of Low Level CRTC

1 is a video RAM configuration diagram for explaining a sequential addressing method.

2 is a video RAM configuration diagram for explaining a row table addressing method.

3 is a circuit block diagram showing an example of the present invention.

4 is a circuit diagram embodying FIG.

5 is a waveform diagram according to FIG.

* Explanation of symbols for main parts of the drawings

1: central processing unit 2: decoder

3: CRTC 4: Row detector

5: Interrupt signal generator 6: Reset signal generator

Vs: Vertical Synchronization Signal Hs: Horizontal Synchronization Signal

RA: Scan Line Address MA: Memory Address

NMI: Interrupt signal AD1, AD2: And gate

FF1, FF2: D flip-flop OR1, OR2: Oagate

INV: Inverter

The present invention improves the data processing efficiency of a computer terminal device by reducing the time for accessing the CRT display control device from the central processing unit when displaying the output of the computer main body on the screen of the CRT with a CRT display control device composed of a low-level CRTC. The present invention relates to a low table addressing method using a reset function of a CRTC that enables low table addressing using a reset function of a lower level CRTC.

In the CRT terminal, a computer terminal device, a raster scan method is generally used to display characters on the screen of the CRT, which is repeatedly scanned on the screen of the CRT by repeating the dot pattern of the characters by the CRTC. As you do this, the effect is as if the characters were still being written on the screen of the CRT. In order to display characters on the CRT frame by CRTC, a memory location for storing the character code is required so that the CRTC can repeatedly output the code data for the character. This is generally called a video RAM or a display RAM. . That is, the video RAM outputs code data of characters stored from the keyboard or the computer main body according to the address repeatedly designated by the CRTC repeatedly, thereby displaying the characters on the CRT screen. In order to input code data of characters inputted from keyboard or computer to the video RAM, the CPU is controlled by the central processing unit. Thus, the video RAM is shared and accessed by the central processing unit and the CRTC. The data processing efficiency of the computer terminal device depends on the time allotted to control the CRT display control device in the. In other words, the more time the central processing unit accesses the CRT display control device, the less efficient the data processing efficiency of the computer terminal device is. The data processing efficiency of the computer terminal device is further deteriorated since the device allocates time for moving the remaining data after recording or removing data for one row from the video RAM of the CRT display control device. However, as described above, the video RAM shared and accessed by the CRTC and the central processing unit is present in the addressing method in the CRTC. First, the sequential addressing method will be described with reference to FIG.

The sequential addressing method is to supply the address signal sequentially when the CRTC supplies the address signal to the video RAM, and this method is commonly adopted in the general lower CRTC. The video RAM as shown in FIG. 1 is symmetrical with the screen of the CRT as 1: 1, and a part corresponding to one page between the address start point FA and the address end point LA is one screen of the CRT. To lose. In addition, since a normal CRTC has a built-in memory start designation register indicating the video RAM start point (FA), low-level CRTCs supply the video RAM sequentially from the address specified in this memory start designation register, and are sequentially assigned. According to the address, the character code data of the video RAM is sequentially output and displayed as characters on the screen of the CRT.

This sequential addressing method does not significantly affect the data processing efficiency of the computer terminal device when the video RAM is only one page.

For example, if you want to delete one line or insert one line from the text lines displayed on the screen of the CRT, delete or add the line to be deleted from the RAM in the central processing unit. The rest of the rows must be moved up or down. If the video RAM consists of one page, only up to 12 rows of data will be moved. Since the entire page must be moved in addition to the maximum 12 lines corresponding to the page, the time for accessing the CRT display control device in the central processing unit becomes longer, and thus the time for processing data in the computer terminal device becomes shorter. This decreases the data processing speed of the data input from the keyboard or the computer main body in the computer terminal device, and thus is an important factor in reducing the data processing efficiency of the computer terminal device.

Next, the low table addressing method will be described with reference to FIG. The low table addressing method improves the data processing efficiency of the computer terminal device by improving the problems associated with the sequential addressing method described above. The low table addressing method does not sequentially supply addresses to the video RAM in the CRTC. If the row tables (A1 to An-1) are set in order and the row tables are accessed sequentially, the addresses corresponding to each row of the video RAM are in the row table. The data for each line is output so that characters are displayed on the screen of the CRT. Therefore, when removing the character line displayed on the screen of the CRT or inserting the character line, it is necessary to adjust the address of the corresponding line in the row table without changing the contents of the video RAM. The access time is shortened, and even if the video RAM is more than two pages, only the address of each row needs to be stored in the row table. Therefore, if only a maximum of 12 rows of data are transferred regardless of the number of pages, one row is displayed on the screen of the CRT. Deleting a file or inserting a single row is a simple process. Therefore, the data processing efficiency of the computer terminal device is improved. To realize such low table addressing, first, a register to store the head address of each row is needed, and a row is output each time data for one row of video RAM is output. An interrupt signal is required to classify, a memory designated register indicating the capacity of the video RAM is required, and the advanced CRTC includes such circuits to realize not only sequential addressing but also low table addressing. However, the use of such CRTC increases the price of the product, there is a function that is not necessary in the computer terminal device, there is an inefficient side to produce the product.

The present invention has been invented in view of the above situation, and generates an interrupt signal for each line displayed on the screen of the CRT, resets the CRCT each time an interrupt signal is generated, and stores the system in the system memory at the central processing unit. By changing the memory start designation register in the CRTC according to the data set in the low table, the low-level CRTC can be displayed on the screen of the CRT in order to display characters by the character code data of the video RAM in the order of the low table in the system memory. The purpose is to provide a low table addressing method using the set function.

Hereinafter will be described in detail with reference to the construction method and its operation, the effect of the embodiment of the present invention illustrated.

The present invention provides a CRT display control device comprising a central processing unit (1), a decoder (2), a CRTC (3), and the like, which displays the output of a computer main body on a screen of a CRT. From RA), it is detected that each row is divided by the row detection unit 4, and the horizontal synchronization signal HS and the display operation signal DE, which are output signals of the CRTC 3, and the chip selection signal of the CRTC ( CS and the output signal of the row detector 4 are combined by the interrupt signal generator 5, and the interrupt signal NMI is combined by the reset signal generator 6 in the CPU 1 The reset signal RST is supplied to the reset terminal of the CRTC 3 to supply the interrupt signal NMI to the central processing unit 1 each time a row is divided on the screen of the CRT. Causes the CRTC (3) to change the value of the memory start designation register inside the CRTC (3) to the address of the next line. By supplying the chip select signal CS to the CRTC 3, the row table addressing can be performed by causing the CRTC 3 to address the video RAM from the address written in the memory start designated register. Reference numeral Vs denotes a vertical synchronization signal, and MA denotes a memory address.

3 is a circuit block diagram showing an embodiment of the present invention having the above structure. The CPU 1 designates a memory location capable of performing row table addressing to a system memory (not shown), and if an interrupt signal NMI is input from the interrupt signal generator 5, a chip is input to the CRTC 3. After supplying the selection signal CS, the data stored in the row table are output one by one and written to the memory start designation register in the CRTC 3. The CRTC (3) outputs the memory address (MA) sequentially from the address of the memory start designated register, while outputting the vertical and horizontal synchronization signals (Vs) (Hs), the display operation signal (DE), and the scan line address (RA). Let's do it. At this time, when the reset signal RST is input from the reset signal generator 6, the CRTC 3 counts the memory address MA again from the address recorded in the memory start designation register, and the scan line address RA is generated. Starts counting from the first, ie, 0 scan lines. The row detection unit 4 detects that the rows are separated from the scan line address RA. Each row is detected by detecting the first scan line or the last scan line of the scan line constituting one row. It is to detect the distinction. In this way, it is detected that each row is divided for each row. By detecting the first scan line or the last scan line of the scan line constituting one row for each row, it is detected that each row is divided. In this way, the signal that detects the division of each row is supplied to the interrupt signal generator 5 and the reset signal generator 6, respectively. The interrupt signal generating unit 5 supplies an interrupt signal NMI to the central processing unit 1 when each row is divided according to the signal detected by the row detecting unit 4, and the interrupt signal (from the central processing unit 1). When the chip select signal CS is supplied through the decoder 2 to receive the NMI and access the CRTC 3, the interrupt signal NMI is returned by the chip select signal. Therefore, the interrupt signal NMI becomes a pulse signal.

Finally, the reset signal generator 6 keeps counting the memory address MA even if the interrupt signal NMI is supplied to the central processing unit 1 to change the value of the memory start designation register in the CRTC 3. Since the memory address of the next row is supplied to a video RAM (not shown), the reset signal RST is supplied from the horizontal retrace time until the display operation signal DE until the display operation signal DE is prevented. Therefore, the CRTC 3 is reset so that the memory address MA counts again from the address recorded in the memory start designation register in the CRTC, and the scan line address counts from the zero scan line.

In the one-single example of the present invention configured as described above, using the low-level CRTC reset function capable of sequentially addressing video RAM, the recording data of the memory start designated register is changed each time a row is changed. After changing according to the low table stored in memory, CRTC (3) is reset to count the memory address (MA) from the changed memory start designated register to access the video RAM, which is the same effect as the low table addressing. . In other words, when deleting one row or inserting one row among the displayed characters on the screen, even if the video RAM capacity is 2 pages or more, only the data representing each row of the row table in the system memory needs to be changed. It is possible to improve the data processing time of the processing device.

4 is a circuit diagram specifically realizing a circuit block diagram of the temporary example of the present invention as described above. This circuit diagram is designed according to the case where the scan lines per row are 13 scan lines.

The row detection unit 4 may be configured as an AND gate ADI. If only the third and fourth bits RA2 and RA3 are logically multiplied among the bits representing the scan line address RA, the row detection unit 4 forms one row. The last scan line of the scan lines is detected.

If the number of scan lines per row changes, the row detection unit 4 can be configured differently accordingly.

The signal output from the row detector 4 is supplied to the interrupt signal generator 5 and the reset signal generator 6, respectively. The interrupt signal generator 5 is composed of the AND gate AD2 and the D-type flip-flop FF1. When the display operation signal DE of the row detection signal takes the logical product of the AND gate AD2, it is shown in FIG. The same signal as (5-4) is supplied to the clock terminal of the D flip-flop FF1. Then, the D flip-flop FF1 outputs an interrupt signal NMI when the clock signal rises from a low signal to a high signal. When this interrupt signal NMI is sent to the central processing unit 1, the central processing unit 1 supplies the chip select signal DS through the decoder 2 to change the memory start designating register of the CRTC 3. This chip select signal CS is also supplied to the clear terminal CLR of the D flip-flop FF1 so that the interrupt signal NMI becomes a pulse signal as shown in (5-5) in FIG.

When the interrupt signal NMI is supplied to the central processing unit 1, the central processing unit 1 selects the CRTC 3 to chip the data of the row table stored in the system memory and designates the memory start in the CRTC 3. Although the contents of the memory start specification register have been changed, the CRTC (3) keeps supplying the memory address (MA) for the next row to the video RAM, so the next row displayed on the CRT screen indicates that The CRTC (3) must be reset in order to be displayed in the line. The circuit for generating such a reset signal RST is the reset signal generator 6, which is the OR gate OR1 (OR2) and the D flip-flop of the inverter INV. (FF2). The inverted signal of the row detection signal, the display operation signal DE, and the horizontal synchronization signal Hs are logically summed by the inverter INV and the OR gate OR1, and then the signal D as shown in (5-6) of FIG. It is supplied to the clock terminal of the mold flip flop FF2.

On the other hand, before the interrupt signal NMI is generated, the D-type flip-flop FF2 shows a low signal at its output stage Q, but since the output signal of the OR gate OR1 is a high signal, the output signal of the OR gate OR2 also continues. High signal. When the interrupt signal is generated, the D flip-flop FF2 is cleared, and the output terminal Q becomes a high signal. Therefore, the output terminal of the OR gate OR2 continues to be a high signal. When the output signal of the OR gate OR1 becomes two pulses with the display operation signal DE and the horizontal synchronization signal Hs as shown in (5-6) of FIG. 5, the D-type flip-flop (FF2) at the rising point ) Is operated so that the output terminal Q becomes a low signal as shown in (5-7) of FIG. 5, but the output signal of the oragate OR1 continues to be a high signal. On the other hand, when the output signal of the OR gate OR1 becomes a low signal, the OR gate output signal also becomes a low signal so that a reset signal such as (5-8) of FIG. 5 is supplied to the CRTC 3. . Therefore, since the CRTC 3 is reset by this reset signal RST, the memory address MA starts counting again from the address indicated by the memory start designation register. In this way, the interrupt signal (NMI) is generated every line, and accordingly, the low table in the system memory is written to the memory start designated register in turn, and the characters displayed on the screen of the CRT by resetting the CRTC (3) before displaying the character line are displayed. The line is displayed as the character line indicated by the memory start designation register, so that the character code data of the video RAM is displayed on the screen of the CRT by the low table addressing method.

As described above, the present invention detects that the line is divided from the scan line address, generates an interrupt signal every time the line is divided, and changes the contents of the memory start designated register of the CRTC according to the contents of the row table. Before the display, the CRTC is reset so that every line displays the character line of the character code data of the video RAM according to the contents of the memory start designated register on the screen of the CRT. Therefore, by performing low table addressing using a reset function with a low-level CRTC that can only perform sequential addressing, it is possible to increase the data processing speed of the computer terminal device and to reduce the product price.

Claims (1)

In displaying the output of the computer main body on the screen of the CRT by the CRT display control device composed of the central processing unit 1, the decoder 2, the CRTC 3, and the like, the CRTC 3 by the row detection unit 4; Detect that each row is separated from the scan line address RA, and each time the division of each row is detected by the row detector 4, the interrupt signal generator 5 in the central processing unit 1 Each time the interrupt signal NMI is received, a chip select signal for chip selecting the CRTC 3

At the same time, the contents of the row table in the system memory are written one by one to the memory start designated register in the CRTC (3), and the CRTC is reset by the reset signal generation circuit (6) immediately before the next memory address is output. Reset (3) to count the memory address (MA) from the address recorded in the memory start designation register for each character line so that low table addressing can be performed using the reset function with a low-level CRTC that can only perform sequential addressing. Low table addressing method using a reset function of the low-level CRTC, characterized in that.

Images