JP2954589B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an information processing apparatus for processing pixel data such as characters and figures.
Equipment, especially word processors and personal computers.
There is a display on the CRT or liquid crystal used in the pyuta etc.
Or on a device that records on recording paper by a printer.
High speed display data such as characters and figures on graphic memory
To read and write data and make changes at high speed.
Read / write display control. [Prior art] In recent years, Japanese word processors and personal computers
Data, etc., display characters and figures on the CRT and LCD screen
In order to achieve this, the degree of freedom of the display content is large,
A graphical method in which a 1-bit storage element corresponds to a dot
Display device adopting bit map display method using moly
Has become widely used. The disadvantage of the bitmap display method is that one display screen is displayed.
Images must be written to the graphic memory in one-dot correspondence
The display content change speed must be slow, and in the display
If the content is changed frequently, the program that controls this
Other control by increasing the load on the processor (hereinafter referred to as CPU)
Is delayed. To do this, the display data must be written to the graphics memory.
Speeds up the load processing, and also reduces the CPU load for this processing.
Methods for reducing the load have been proposed. JP-A-60-260989
The display method described in Japanese Patent Publication No.
Bit shift processing when writing to the graphic memory
Reduces CPU load in synthesis processing with processing and background data
It proposes a method to do it. [Problems to be Solved by the Invention] However, the conventional display method described above is
Display data from graphic memory or after synthesis
To write the display data of
Reaccess method and write data for display change
Display method of graphic memory
Effective use of memory not used as data memory
I did not consider the law. For example, to prevent the image from flickering when rewriting the screen
To graphic memory by time sharing method
Screen using a 1024-dot screen
In the case of dots x 512 dots, a graph with a minimum configuration of 16 bits
A read memory is required. 64 kilobits x 4 bits
One graphic memory using four DRAMs
Then, the graph memory has a capacity of 128 kilobytes.
It will be one. However, the display screen capacity is 64 kilobytes.
The remaining 64 kilobytes of graphic memos
The part of リ is not used for display image data
become. Furthermore, in the conventional display data processing method, the screen
In roll processing, data rewriting of the entire screen
Required at this time, crossing word boundaries by bit shifting.
If the data obtained is to be updated,
Requires multiple write operations and slows down the processing speed.
There was a problem that it became worse. Therefore, the object of the present invention is to
How to speed up the update process and effectively use the graphic memory
To be able to [Means for Solving the Problems] In order to achieve this object, the present invention provides a display device,
Stores programs and data for operating the display device
Program memory, data in word units, and the data
Transfer means for generating word address indicating transfer position of data
And a graphic provided separately from the program memory.
Memory and the display device for displaying a screen on the display device.
Address for reading data from graphic memory
Display address generating unit for generating
And between the display address generator and the graphic memory
Connected to write data to be stored in the graphic memory.
Writing means and the graphic data stored in the graphic memory.
Graphic means including reading means for reading data
An information processing apparatus comprising a
The physical memory control circuit stores the graphic memory.
The boundary for dividing the screen display area and CPU data area is set.
Graphic memory boundary setting circuit and screen display
The address from the data transfer means for the area is
Horizontal address or raster order changing in the scan direction
Address conversion for converting to vertically changing vertical addresses
Means and the data transfer means for the CPU data area.
The address from the first stage is converted to the address by the first address conversion means.
Changes in the raster scan direction independently of the dress conversion
Second address translation means for translating while fixing the address to a horizontal address
And further dividing the screen display area into a plurality of
Within a specified memory block addressed in a loop
The display interface is configured to form a round-up screen.
Third address for converting the address from the address generator
Equipped with conversion means, when scrolling the screen, a new display
Rewrite only the data and change the screen display start address.
It is characterized in that it is modified. [Action] The graphic memory boundary setting circuit
Memory is divided into a screen display area and a CPU data area.
Boundaries are set so that the graphics memory
CPU data in addition to the screen display data storage area of the display device
It can also be used as a storage area, making the graphic memory effective
Can be used. Then, the first address translating means corresponds to the screen display area.
The direction of the corresponding graphic memory address change
Address and vertical address, and a second address conversion means.
Is the graphic memory address corresponding to the CPU data area.
The direction of change of the address is determined by the first address conversion means.
Since it is fixed to the horizontal address independently of the dress conversion,
Display data from the data transfer means for the screen display area
Enhanced storage processing and data storage processing for CPU data area
Can be faster. Further, the third address conversion means further includes a lower display area.
Divide into multiple parts and address one of them in a loop
Display address to compose the
Because the address from the raw part is converted, the screen scroll
You only need to draw the new area, and
Reduce the data update processing load due to steps. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. The display device according to the present invention is, as shown in FIG.
Control is performed and data is stored in peripheral memory etc. in 1-byte units.
CPU 100 that exchanges data and the display device operate
Program memory 101 for storing various programs and data
And the characters shown on the CRT monitor 108 as shown in FIG.
Character generator that stores pattern data (hereinafter
CR from the lower CG) 102 and graphic memory 105, 106
Address for reading data to be displayed on T monitor 108
And CRT controller 103 that generates synchronization signals and CPU 100
CRT monitor at any position of graphic memory 105, 106
When writing pattern data to be displayed on 108,
Shifts the graphics data and stores them in the graphics memories 105 and 106.
To the write address
Logically process the written old pattern data to create a new pattern.
Generate new pattern data and graphically display the new pattern data.
The process of writing to the memories 105 and 106 and the pattern
From the graphics memory 105, 106 to display the
A peripheral control circuit 104 for performing a process of reading data and a CRT
A graph that stores pattern data to be displayed on the monitor 108
Via the signal lines 110 from the external memories and the flash memories 105 and 106.
Display data and instructions sent to the display device
00 and receive a response from the CPU 100 to an external device.
An input / output control unit 107 for communicating with characters and figures, etc.
A CRT monitor 108 for displaying patterns, etc., and the CPU 100
Program memory 101, CG102, CRT controller 103, peripherals
Internal connection between control circuit 104 and input / output control device 107
A wiring path (CPU bus) 109 is provided. FIG. 1 is an internal configuration of the peripheral control circuit 104 in FIG.
It shows. In FIG. 1, a control signal generating circuit 1
Peripheral control based on signals and operation clock signal CLK
The control data latch (A) 6 in the circuit 104 and the control data latch
Either switch (B) 16 or CRTC address converter 18
Send a register selection signal to one
(A) 6, control data latch (B) 16, or CRTC add
Data from the CPU 100 to one of the
Or background data latch 14 or data buffer
Send data latch signal and data output signal to 13
And address selectors (A) 4 and (B) 5
Send U address selection signal and simultaneously
Generates control signals for the
Write data from CPU 100 to memory 105, 106, or
Data against the background data latch 14 and data buffer 15.
Sends a touch signal or data output signal and
CPU address selection for selectors (A) 4 and (B) 5
Signal and simultaneously send it to the graphics memories 105 and 106.
Generates a control signal to
Read data from 5,106 or select address
CRT address selection signal to the (A) 4 and (B) 5
And simultaneously control the graphics memories 105 and 106.
Control signal and data latch signal for shift unit 17
The video signal to be displayed on the CRT monitor 108 is
Is to be written. Access to the graphics memories 105 and 106 is the third
Read by one display data read access as shown
And sends the data to the CRT monitor 108 as a video signal.
Time, the next display data read time and CPU access
Time-divided two times, each with an independent address graph
Accesses the memory and reads the next display data.
Writing to graphic memory by CPU or
This is for reading. The address translator 2 has a width of 1024 dots as shown in FIG.
(128 bytes), graph composed of 1024 vertical dots
The vertical direction of the display on the CRT monitor 108
If the size does not exceed 512 dots,
Divide into area 0 and area 1 at the boundary and display on CRT monitor 108
Area 0 used as an area for storing data to be written
Byte addresses that can speed up display
The vertical address configuration will increase next, and the CPU 100
Area used as storage area for data used during execution of RAM
1 is a horizontal address in which the byte address sequentially increases in the horizontal direction.
Configuration of the CRT monitor 108.
If the vertical size of the display exceeds 512 dots,
CRT monitor 10 for all areas of flash memory 105, 106
Used as an area to store data to be displayed in 8, characters, etc.
Byte data so that the display data can be written at high speed.
Vertical address configuration where dresses increase sequentially in the vertical direction
Address signal from the CPU 100.
Address signals CA0 to CA given to the graphic memories 105 and 106
It is converted to CA16. The address translator 2
As shown in FIG. 6, address signals A0 to A16 from CPU 100 are
Address after address conversion (hereinafter called real byte address)
U) Address cross (A) 2 for conversion to CA0 to CA16
01 and address cross (B) 202 and data selector 203
The data selector 203 is controlled by
DC, VS0, VS1 and CPU address of data latch (A) 6
The signal A16 is input as a control signal.
Address cross (A) 201 and address cross (B) 202
Each of the vertical addresses in the address conversion correspondence table shown in FIG.
(A) and vertical address (B) from CPU100
Address signals A0 to A16 to real byte addresses CA0 to CA16
Is converted, and as a result
The byte addresses of the stick memories 105 and 106 are as shown in Fig. 7.
Graphic memories 105 and 106 according to each conversion mode.
Real byte address configured to increase sequentially in the horizontal direction
Is converted from the address. In other words, CPU 100
Addresses of graphic memories 105 and 106 viewed from the vertical direction
Address, and the CPU 100 issues the corresponding address.
Even if it is generated, the real
The write addresses CA0 to CA16 are stored in the graphic memories 105 and 106.
Addresses configured to increase sequentially in the horizontal direction
Is what it is. The adder 3 calculates the real byte addresses CA1 to CA16 and CA0.
This is to add the graph
Real bytes converted from address signals to memories 105 and 106
Even address graph when address becomes odd
Adjacent to the memory 105 in the increasing direction of the address.
Generates an even address of the graphic memory.
You. At this time, the odd address graphic memory 106
The byte addresses CA1 to CA16 are applied as they are.
You. If the real byte address is even, CA0 is 0 and even
Address graphic memory 105 and odd address groups
The rough memory 106 stores the real byte addresses CA1 to CA4.
CA16 is applied as it is. From the above, the actual byte
If the address is even, the real byte address indicates
Odd address memory adjacent to even address memory
16 bits are selected at once from several address memories, and the actual
If the byte address is odd, the real byte address indicates
Adjacent to the odd address memory
16-bit selectable even address memory
You. The CRTC address converter 18, as shown in FIG.
Splits the display screen of the
CRT control to configure door-to-screen
Screen refresh address signal (ra) from
Dress selector (A) 4 and address selector (B) 5
To give the modifiy address (mra)
is there. The CRTC address converter 18, as shown in FIG.
In the split screen to be described,
Data required to perform the following operations
Address conversion control registers 172 and 17 for storing
3,174,175 and the above CRTC address based on the CPU access signal
One of the address conversion control registers 172, 173, 174, 175
Sends the register selection signal to the
Control register 172, 173, 174, 175
Generates a control signal to write the address data
Decoder 171 and the screen
CRTC address conversion control of fresh address signal (ra)
According to the address set in registers 172, 173, 174, 175
Operation of round-up screen configuration
Modified Eye Address (mra)
Adders 182, 183, 185 and subtractor 18
1,184 and selectors 186,187. 171 decodes the CPU instruction given from the CPU bus
This is a decoder for selecting and giving to each register. 17
2 is the start address (CRT control)
Register (S) that stores the value of the output address of the roller 103)
A). 173 is on graphic memory 105,106
For the display of divided upper screen in the display area of
Register (DSA1 and DSA1) for storing the read start address
Call). 174 is a table on the graphics memory 105, 106
For display of the lower screen divided into screens in the display area
Register for storing the start address (called DSA2).
). 175 is the image on the graphics memory 105, 106
Stores the first address of the upper screen area divided into planes
(Referred to as VSA). Adders 182, 183, 185, subtractors 181, 184 and selector 18
6,187 are prepared for the required number of bits. The subtractor is
Output (AB) and borrow output B for inputs A and B
I do. The adder outputs (A + B) to input A and B and
And outputs a lead output C. Selector operates on DA and DB inputs
If the input of S is 1, select DA and if 0, select DB and output
Is what you do. Address selectors (A) 4 and (B) 5 are even numbers
Address graphic memory 105 and odd address groups
An address signal to be applied to the rough memory 106 is generated.
And a signal from the control signal generation circuit 1.
The real address from the CPU 100 or the CRTC address change
Any of the Modified Eye Address (mra) from exchanger 18
Select one of them and load the row of graphic memories 105 and 106.
Address and column address in a time-sharing manner.
You. The graphic memory boundary setting circuit 7 is an address of the CPU 100.
Signal and the control signal of the control data latch (A) 6
Then, the CPU 100 enters the area 1 of the graphic memories 105 and 106.
When data is accessed for
Data shift and compositing process
Set to 0, output the data of CPU100 as it is without performing synthesis
Signal to set the mode (hereinafter referred to as data through signal)
Is to occur. The graphic memory boundary setting circuit 7 is shown in FIG.
Address signal from CPU 100 and control data
(A) 6 (DC, DT0, DT
Compare the value of 1) to generate the data through signal.
(A) 701, an address signal from the CPU 100,
Set area 0 or 1 to vertical address or horizontal address
Compare the values of the horizontal address specification registers (VS0, VS1)
Comparator (B) 703 for generating the horizontal address designation signal
Between the data through signal and the horizontal addressing signal.
It consists of a logic 702 that performs a logical sum. The shift amount is forcibly set to 0, and the synthesis is not performed.
The mode to output U100 data as it is is the control data
Of each control signal of the latch (B) 16 and the data through signal.
The signal obtained by taking the logical sum or logical product
(A) 9, shift part (B) 10, shift part (C) 11 and write
Can be set by sending data to data synthesis unit 12
It works. The control data latch (B) 16 is a data shift synthesizing unit.
A control value for selecting the data shift amount or the synthesis method
Data latches to be touched, FC indicates the synthesis method
Data latch, and DN is CPU1 as shown in FIG.
The group of data to be written from 00 to the graphic memories 105 and 106
Specify the shift amount from the word boundary of the rough memories 105 and 106.
The data latch shown in FIG.
PU100 reads data from graphic memories 105 and 106.
The amount of shift from the word boundary of the graphic memories 105 and 106
This is the data latch to be instructed, and the WSN is as shown in FIG.
Data to be written from the CPU 100 to the graphic memories 105 and 106
Data start position and the shift amount from the word boundary of CPU100.
Data latch, and WN is shown in Fig. 12.
Data to be written from CPU 100 to graphic memories 105 and 106.
Data latch that indicates the data width of the data by the number of bits.
You. The write dot instruction pattern generator 8 controls the control data
(B) in FIG. 12 according to the value of the data latch WN of 16.
From 1 bit to d7 going from d0 to d7 as shown
The write dot instruction pattern MD which is the data string of 1 is issued.
It is the one that produces it. Shaded area in Fig. 12 Indicates 1. The shift section (A) 9 is a 16-bit data rotator.
With control data latch (B) 16 data latch DN value and
Changed to the value of CA0 of the graphic memory real byte address
As shown in FIG. 12, the write dot instruction pattern MD
Is rotated in the direction from d0 to d15 and data is written.
Only the position indication pattern SMD is generated. Real buy
If the address CA0 is 0, the address CA0 is d0 as shown in FIG.
Rotate to the position shifted by the value of data latch DN
When the real byte address CA0 is 1,
To the position shifted by the value of the data latch DN from d8
It is something to rotate. The shift unit (B) 10 is a 16-bit data rotator
With control data latch (B) 16 data latch DN, WSN
Value and the value of CA0 of the graphic memory real byte address
Accordingly, as shown in FIG. 13, the write data WD is changed from d0.
Rotate in the direction of d15 and rotate the write data
This is for generating a light pattern SWD. Real byte ad
If the address CA0 is 0, as shown in FIG.
Rotate to the position shifted by the value of DN-WSN
If the real byte address CA0 is 1,
As shown in (b), only the data latch DN-WSN value is transferred from d8.
It is to rotate to the position where it was shifted. This
The start position of the write data is the data write position
Match the indicated pattern SMD. The background data latch 14 is transmitted from the control signal generation circuit 1.
Signal in the CPU access time shown in FIG.
16-bit background read out from the memory 105 and 106
This is for latching the data RD. The write data synthesizing unit 12 includes the shift unit (A) 9
(B) 10 and the data output from the background data latch 14.
Data write position indication pattern SMD, write data rotation
Pattern SWD, background data RD and control data latch
(B) SWD and RD are SMD based on the value of 16 data latch FC
Is a logical product, a logical sum, an exclusive logical sum, etc.
Synthesis And the other parts output RD as is Write to perform processing and write to graphic memories 105 and 106
It generates and outputs only data. This allows
If the real byte address CA0 is 0, it is shown in FIG.
Position rotated from d0 by the value of data latch DN
The write data of CPU 100 is located at
If 0 is 1, the data from d8 is read as shown in FIG.
Write data of CPU100 to the position rotated by the value of switch DN.
Data is located. The shift unit (C) 11 is a 16-bit data rotator.
Yes Data latch RSN value of control data latch (B) 16
And the value of CA0 of the graphic memory real byte address
Therefore, as shown in FIG.
The background data RD read from 6 is directed from d15 to d0 and
To rotate to generate CPU read data SRD.
You. When the real byte address CA0 is 0, (a) in FIG.
The data latch RSN value toward d0
Figure 14 when the real byte address CA0 is 1
RSN + 8 bit rotation toward d0 as shown in (b)
Is what you do. As a result, on the CPU read data SRD
The start position of the read data matches d0. The shift unit 17 is a signal transmitted from the control signal generation circuit 1.
As a result, the display data read time shown in FIG.
32 bits read twice from the stick memories 105 and 106
Latch and serially shift the display data of
Is converted and output. The number attached to the signal line means the number of lines. Next, the operation of the display device having the above configuration will be described.
You. Display to the input / output control unit 107 from the external device via the signal line 110
When the display data and display command are input, the CPU 100
Is detected, the display command is analyzed, and the display operation is started. Display of character patterns stored in CG102
Is the address of the character pattern stored in CG102
And write the pattern data to be displayed
Write address of memory 105, 106, shift value DN, and synthesis
Indication value FC, write data head position instruction value WSN, and write
Only the data width indication value WN is calculated, and then combined with the shift value DN.
Indication value FC, write data head position instruction value WSN, and write
Control data latch (B)
Write to the corresponding data latch in 16. Next, the CG102
Write to the graphic memory 105, 106 from this address
Pattern data and read it through the peripheral control circuit 104.
To the corresponding address in the graphics memory 105, 106
Put in. At this time, the peripheral control circuit 104 operates as shown in FIG.
Access to graphic memories 105 and 106
CPU access time to graphics memory 105, 106
Then, the write operation is performed as follows. In the address converter 2, the graphic memories 105, 10
Generate a real byte address n for writing to 6. Adder 3, address selector (A) 4, address selector
(A) When n is an even number, an even address graphic memo
N in the memory 105, and the odd address graphic memory 106
Apply n + 1. (B) Even address graph graph memo when n is odd
N + 1 in the memory 105 and the odd-numbered address graphic memory 106
Is applied with n. Thereby, when the real byte address n is an even number,
Even address graph indicated by the real byte address n
The odd number address adjacent to the memory 105 and the address
Select 16 bits for the dress graph memory 106
If the real byte address n is an odd number,
Odd address graphic memory 10 specified by address
Even address graph adjacent to 6 in the address increasing direction
A 16-bit selection is made for all of the push memories 105 at a time. Access signal RAS to graphic memories 105 and 106
And CAS and send background data from the address selected above.
Reads the data, latches it on the background data latch 14, and
Data RD. At the same time as the above, the write pattern generator 8, the shift unit
(A) 9, shift unit (B) 10, write data synthesizing unit 12
From FIG. 14, as shown in FIG. 14, (a) when n is an even number, 16 bits starting from d0
The write pattern at the position shifted by DN bit from d0.
Generate the data where the button is located. (B) When n is odd, for 16 bits starting from d8
The write pattern at a position shifted by DN bit from d8.
Generate the data where the button is located. When the background data latch operation is completed, the data
To the graphic memory 105, 106 via the server 13
Send the write data generated in
Sends data write signal WE to memories 105 and 106,
Write the generated data. Thus, as shown in FIG. 16, the CPU 100
The pattern data written for dress n
Write pattern data even when shifting
Is simultaneously written to real byte addresses n and n + 1
I will. As a result, the actual byte address is
Operation of writing to the n and n + 1 in two separate steps
Only needs to be performed once, and the writing process can be sped up.
The same speed can be obtained regardless of the writing position.
You. Next, it is stored in the graphic memories 105 and 106.
When the display operation is to display the pattern
Patterns stored in rough memories 105 and 106
Address to write the pattern to be displayed
Write addresses of the memory 105, 106, the shift value Dn,
A synthesis instruction value FC, a write data head position instruction value WSN,
Write data width indication value WN and read pattern data
The effective start position indication value RSN is calculated, and then the shift value DN
Write instruction FC, write data start position instruction WSN,
Data width indication value WN and effective start position indication value RSN.
The corresponding data latch in the control data latch (B) 16
Write to Tsuchi. Next, the corresponding graphics memory 105, 106
Move and display from the address via the peripheral control circuit 104
Read the pattern and graph it via the peripheral control circuit 104
The data is written to the corresponding addresses of the topic memories 105 and 106. This
In this case, the peripheral control circuit 104 performs time division as shown in FIG.
CPU access to the graphics memory 105, 106
Access time to the graphics memory 105, 106
The read operation is performed as described above, and the
Write turn data. In the address converter 2, the graphic memories 105, 10
Generate a read real byte address m to 6. Adder 3, address selector (A) 4, address selector
(A) If m is an even number, even address graph memo
M in the memory 105, and the odd-numbered address graphic memory 106
Apply m + 1. (B) When m is odd, even address graph
M + 1 in the memory 105 and the odd address graphic memory 106
Is applied to m + 1. Thereby, when the real byte address m is an even number,
Even address graph indicated by the real byte address m
The odd number address adjacent to the memory 105 and the address
Select 16 bits for the dress graph memory 106
If the real byte address m is an odd number,
Odd address graphic memory 10 specified by address
Even address graph adjacent to 6 in the address increasing direction
A 16-bit selection is made for all of the push memories 105 at a time. Access signal RAS to graphic memories 105 and 106
And CAS and send data from the address selected above.
Is read out and latched to the background data latch 14, and the background data
Get RD. As shown in FIG. 11, (a) when m is an even number, the shift unit (C) 11
The pattern at the position RSN bit shifted from d0 is
Generated as the title read data. (B) If m is odd, for 16 bits starting from d8
The pattern at the position shifted by dsn from d8 to 8 bits
Generated as the title read data. The read data generated by the
To the CPU 100. Thus, as shown in FIGS. 9 and 11, the CPU 100
Is read from the real byte address m.
The read pattern is not
Are simultaneously read from the site addresses m and m + 1. This
As a result, as shown in FIG.
Read operation is divided into two for +1 only once.
And the reading process can be sped up, and the reading position
The same speed can be obtained regardless of the above. Read more
Operation and the display operation on the display screen
Moved and stored in the graphics memory 105, 106
It is possible to speed up the display processing of the pattern data. Next, a part of the graphic memories 105 and 106 (see FIG. 4)
Area 0) as the display area
The remaining portions of the limbs 105 and 106 (region 1 in FIG. 4)
Explanation of operation when used as data area of PU100
I will tell. Graphic memo as data area of CPU100
When using the area 1 of the memory 105, 106,
Set the shift amount to 0 for the boundary, and read or write the area
Operation must be performed. In this case, the CPU 100
The control value DC in the control data latch (A) 6 is 1, and VS0 is
Control data to set 1, DT0 to 0, VS1 to 0, DT1 to 1
Write data to the latch (A) 6. This allows the graph
FIG. 4 shows the read memories 105 and 106 as viewed from the CPU 100.
Is divided into two areas, area 0 and area 1. region
0 indicates that the address increases in the vertical direction and the data shift
Area to perform the data synthesis processing, and area 1 is added in the horizontal direction.
And the data shift combining process described above is performed.
It is just an area through which data is passed. CPU 100 accesses area 0 for drawing processing
Considering the case where the CPU 100 is a 24 × 24 bit
When handling character patterns, three lines
Site depth, 24 bytes deep in raster order direction
In the 8086 and 8088 used as CPU 100,
String instruction (predetermined register
From the source address specified in the
The transfer of the number of bytes reduces the minimum instruction step and the shortest processing time.
What is done at a reasonable time. The maximum effect of this processing method
In order to obtain the result, it is necessary to take a large number of bytes for one transfer.
It is effective. ) Is prepared, so the
The addresses of the rough memories 105 and 106 are in the raster forward direction.
Should be lined up. On the other hand, large size including continuous raster such as clearing the whole screen
When performing the same operation on an
The address arrangement in the Tuscan direction is the frequency of process switching
Can be switched between the two.
This is a preferable configuration for various kinds of processing. Character display on the screen by the CPU 100 is
Group to display the character pattern specified by the
Tosling to byte address of rough memory 105, 106
This is performed by writing using a programming instruction. Place
Because half-width characters are 1.5 bytes wide,
If one half-width character is entered in the
Bit position of character pattern is not 4 bits in 5,106
Inconsistent situations occur even if they are done. At this time, in a configuration having no write / read means,
Is the graphic memory 10 from the character generator.
1 byte transfer in character pattern transfer processing to 5,106
Bit processing must be performed each time it is sent,
Memory movement by string instructions has not been available. The device should be equipped with the read / write means.
Bit shift processing, mask processing, etc. instead of CPU 100
Use the string instruction
Write to the graphics memory 105, 106 at high speed
Can be. Next, when the CPU 100 accesses the area 1, the
The memory boundary setting circuit 7 generates the address signal of the CPU 100.
From A0 to A16, the CPU access is to area 1
That the control data latch (B) 16
Sends a data through signal. Control data latch (B)
16 is a control data latch by the data through signal.
(B) Force FC, DN, RSN, WSN, WN output from 16
The shift amount is set to 0 for each, and the data of CPU 100 is not
The value is input and output as it is and output. This
Access of area 100 by CPU 100
Since area 1 is not affected,
It can be used as an area, and the graphic memory 105,
106 can be used effectively. By the way, in the illustrated embodiment, the area 0 and the area
1 and the vertical address, horizontal address and data of each area
Register settings and graphics memory settings.
Although the case where the setting is performed by the constant circuit 7 has been exemplified,
Address, horizontal address and data through status of each area
The settings are as shown in FIG. 21.
In the address area 22 of the CPU 100 (221,222),
For example, each area 221 has a horizontal address and a data address.
Area 222, the vertical address and data shift
The state of each area is fixed to the operation state, and the CPU 100
When accessing the display area of the memory 105, 106
The area 222 is accessed, and the CPU 100
When accessing the data areas of the memories 105 and 106, the area 221 is used.
Even if it is configured to access
Similar effects can be obtained. Next, referring to the circuit diagram shown in FIG.
The first diagrammatically shows the relationship between the memory 105 and 106 and the display screen.
Based on Fig. 8 and Fig. 19,
Explanation of the operation when configuring a door-to-screen
I do. Here, the upper screen is a text area, and the lower screen is a text area.
Used for stem region. Fig. 18 shows a round-up screen.
Is not being performed, the display start area
The contents of the DSA1 register 173 and DSA2 register 174
The graphic memory 105, which is schematically shown in FIG.
106 data is read and the display screen is displayed on the CRT monitor 108.
It is formed as shown in FIG. Indicated by A in FIG. 18 (b)
To see the lower part of the screen content
When the screen is scrolled in the direction, the CPU
Is added to the area pointing downward in FIG. 18 (a).
Graph to be newly displayed
Text (for example, new display text)
(For one line of text). Next, if you continue scrolling, the A
The area and the B area overlap. At this time, as shown in FIG.
Area A is the address value stored in DSA2 register 174
The area C is displayed next. sand
That is, during such scroll processing, the DSA1 register 17 is used.
Set 3 to draw new data in the area corresponding to area C
do it. Then, the graphic shown in FIG.
The memory area is displayed on the display screen as shown in FIG.
You. To satisfy these relationships, the CRTC address converter 18
At the output modifiable address (m
ra) and the contents of each register (see FIGS. 17-19)
The lowercase letter of the register name
And the input terminals of the subtractor 181 and the adder 183.
The relational expression of CRTC address (ra) which is the input to child A is
It is like that. ra <sa, ra-sa <0; A region mra = ra + dsa1 ra ≧ sa, ra−sa ≧ 0; B region mra = (ra−sa) + dsa2 ra + dsa1 ≧ dsa2 ra− (dsa2-dsa1) ≧ 0; C region mra = ((ra + dsa1)-dsa2) + vsa = vsa + ra-(dsa2-dsa1) From the above, the bitmap is used as the screen refresh method.
Uses the pre-fresh method and displays the screen in multiple areas.
In the display control device adopting the method of dividing into
When scrolling the screen that requires high-speed processing, the display start
Scroll one area by changing dress and new drawing
Action is taken. This can be applied to the illustrated embodiment.
For example, when scrolling the screen, the CPU
Only by rewriting register 173 and drawing the new display part
The crawl operation can be completed and the conventional screen
All display data was instructed as in scrolling
Moving in the direction eliminates the need
Screen scrolling with much less data processing
be able to. Note that the conventional display device corresponds to FIGS. 18 and 19.
(That is, bit pine as a screen refresh method)
Uses the Pleasure method and displays the screen in multiple areas
Screen scrolling of display device that adopts the method of dividing into
Considering the processing, the conventional display system described above
According to the control device, one region (FIG. 18 and FIG. 19)
The other area (see reference numeral A in FIG. 18)
Screen scrolling is possible if it does not overlap
Bit map memory area corresponding to one area
Overlaps the bit map memory area corresponding to the other area.
If a failure occurs, transfer a large amount of data on the bitmap memory.
Movement is inevitable, and eventually the display data corresponding to one area
Block all of the data in the direction indicated.
Thus, the scroll speed is determined. By the way, in the illustrated embodiment, the area is divided into a plurality of areas.
Loop through the screen area in the upper area of each screen
Address in the specified memory block
Example when configuring a round-up screen
However, the screen scrolling process as described above requires multiple areas.
There is no problem in performing in all areas. [Effect of the Invention] As described above, according to the present invention, the graphic memory is displayed on the screen.
Display area and CPU data area.
In addition to the screen display data storage area, the CPU data storage area
Available and make effective use of graphic memory
And the first address conversion means is provided on the screen display area.
Of the address of the graphic memory corresponding to the area
Direction is converted to a horizontal address or a vertical address, and the second address is
Means for converting the graphics corresponding to the CPU data area.
The direction of the address change of the memory is determined by the first address change.
Independent of the address conversion by the conversion means, fixed to the horizontal address.
To convert and access graphics memory
Display data storage processing for the screen display area
Switch to vertical / horizontal address
With this, this process can be performed at high speed
In addition, in the data storage process for the CPU data area,
No special address processing is required (address direction
When the display area is switched by switching the address,
Address processing is required each time, processing is complicated and
The data storage process for the CPU data area.
Processing can be performed quickly and accurately.
The dress conversion means divides the screen display area into more complicated
One of these areas constitutes a round-up screen
The address from the display address generator is converted as
Since the graphics memory is accessed,
To update the display data when scrolling the screen, write the display data
The data transfer means.
Faster scrolling by reducing the amount of transfer processing
The effect that can be obtained is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a peripheral control circuit according to the present invention, FIG.
FIG. 3 is a block diagram of the display device according to the present invention, FIG. 3 is a timing chart for explaining the respective operations when the peripheral control circuit accesses the graphic memory, and FIG. 4 is a diagram for explaining the area division of the graphic memory. FIG. 5 is an explanatory view of an address translation correspondence table for explaining the operation of the address translator according to the present invention, FIG. 6 is a block diagram of the address translator according to the present invention, and FIG. FIG. 8 is an explanatory diagram of an address translation by the translation operation of the address translator according to the present invention, FIG. 8 is an explanatory diagram of a character pattern, FIG. 9 is an explanatory diagram of a pattern reading position, FIG. 11 is an explanatory diagram of the operation of the shift unit (C), FIG. 12 is an explanatory diagram of the operation of the shift unit (A), FIG. 13 is an explanatory diagram of the operation of the shift unit (B), and FIG. FIG. 15 is an explanatory diagram of the operation of the data synthesizing unit, and FIG. FIG. 16 is an explanatory diagram of a data write / read method according to the present invention, FIG. 16 is an explanatory diagram of a data write / read method according to the present invention, FIG. 17 is a block diagram of a CRTC address converter, and FIGS. 18 (a) and (b). And the first
19 (a) and (b) are explanatory diagrams schematically showing the relationship between a graphic memory and a CRT monitor (display screen), FIG. 20 is a block diagram of a graphic memory boundary setting circuit, and FIG. FIG. 11 is an explanatory diagram of addressing as viewed from a CPU of a graphic memory according to a modified example of the present invention. 1 ... Control signal generation circuit, 2 ... Address converter, 3 ...
... Adder, 4 ... Address selector (A), 5 ... Address selector (B), 6 ... Control data clutch (A), 7 ... Graphic memory boundary setting circuit, 8 ...
... Write dot instruction pattern generator, 9... Shift unit (A), 10... Shift unit (B), 11... Shift unit (C), 12... Write data synthesizing unit, 14. ... Control data latch (B), 18 ... CRT address converter, 105 ... Even address graphic memory, 106 ... Odd address graphic memory.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kazuo Miyazaki               1-1-1 Higashitagacho, Hitachi City, Ibaraki Prefecture               Inside the Taga Factory of Hitachi, Ltd. (72) Inventor Yukio Abe               1-1-1 Higashitagacho, Hitachi City, Ibaraki Prefecture               Inside the Taga Factory of Hitachi, Ltd.                (56) References JP-A-62-237490 (JP, A)                 JP-A-60-21085 (JP, A)                 JP-A-57-41753 (JP, A)                 JP-A-59-52286 (JP, A)                 JP-A-61-246790 (JP, A)                 JP-A-60-22184 (JP, A)

Claims (1)

(57) [Claims] A display device, a program memory for storing a program or data for operating the display device, a data transfer unit for generating data in word units and a word address indicating a transfer position of the data, and separately from the program memory. A graphic memory provided, and a display address generator for generating an address for reading data from the graphic memory for displaying a screen on the display device;
A graphic memory connected between the data transfer means and the display address generating section and the graphic memory, the writing means for writing data stored in the graphic memory, and the reading means for reading data stored in the graphic memory; In an information processing apparatus including a control circuit, the graphic memory control circuit includes: a graphic memory boundary setting circuit in which a boundary for dividing the graphic memory into a screen display area and a CPU data area is set; A first address conversion means for converting an address from the data transfer means into a horizontal address changing in a raster scan direction or a vertical address changing in a raster forward direction, and an address from the data transfer means for the CPU data area, Ad by address conversion means Independently of the scan conversion, a second converting fixed laterally address changes in raster scan direction
Address converting means, and an address from the display address generating section so that the screen display area is further divided into a plurality of sections, one of which is addressed in a loop to form a round-up screen in a specified memory block. An information processing apparatus comprising: a third address conversion unit that converts a data to be displayed, and rewrites only data to be newly displayed and changes a screen display start address when the screen is scrolled. 2. 2. The first indicating means according to claim 1, wherein said writing means and reading means indicate a reading position of data to said data transfer means from said graphic memory by a bit number from a word boundary of said graphic memory. First data shift means provided in a data transfer path from the graphic memory to the data transfer means for shifting data from the graphic memory according to read position information by the first instruction means; A read circuit for sending the data shifted by the shift means to the data transfer means; and a second circuit for designating a write position of the data from the data transfer means to the graphic memory by the number of bits from a word boundary of the graphic memory. Instruction means, and from the data transfer means to the graphic memory A second data shift means provided in a data transfer path for shifting data from the data transfer means in accordance with write position information by the second instruction means, and transferring the data shifted by the second data shift means to the graphic memory An information processing apparatus, comprising: a writing circuit that writes data into a memory. 3. 2. The graphic memory according to claim 1, wherein the graphic memory comprises an odd address memory unit for storing data of an odd word address and an even address memory unit for storing data of an even word address which can be accessed independently and simultaneously. Reading means and writing means, first indicating means for indicating the position at which data to the data transfer means is read from the graphic memory by the number of bits from a word boundary of the graphic memory; and data transfer means from the graphic memory to the data transfer means. A data transfer path for shifting data from the graphic memory according to read position information by the first instruction means.
A data shift means, a read circuit for sending the data shifted by the first data shift means to the data transfer means, and a write position of the data from the data transfer means to the graphic memory, a word boundary of the graphic memory. Second instruction means for instructing by the number of bits from the data transfer means, and data provided from the data transfer means in the data transfer path from the data transfer means to the graphic memory are shifted according to the write position information by the second instruction means. A write circuit for writing the data shifted by the second data shift means into the graphic memory, and a read data from the odd address memory section and a read data from the even address memory section. The first data shift means is provided to the first data shift means. Read data generating means for generating data to be sent to the data transfer means from the data output from the data transfer means; write data to the odd address memory portion from the data output from the second data shift means to the write circuit; Write data generating means for generating write data to an even address memory section, and further from a word address for one of the odd address memory section and the even address memory section provided from the data transfer means, And an access address generating means for generating an access address to the other memory section. The data is read from the one memory section according to the access address from the access address generating means, and a word boundary is simultaneously shifted by shifting. Exceeded data Reading from the other memory unit, writing the data to the one memory unit in accordance with the access address from the access address generating means, and simultaneously writing data that exceeds a word boundary by shifting to the other memory unit. Information processing device. 4. 4. An information processing apparatus according to claim 3, wherein said first and second data shift means include a data rotator having a rotate bit width corresponding to two words. 5. 3. The method according to claim 3, wherein the write circuit includes read-modify-write means for inputting data output from the data shift means and data read from the graphic memory to generate write data. Characteristic information processing device. 6. 2. An information processing apparatus according to claim 1, wherein said third address conversion means comprises an adder, a subtractor, and a selector.