JPH0438582A - Image processor - Google Patents

Abstract

PURPOSE:To improve data processing efficiency by access-processing to plural bit planes simultaneously corresponding to image processing by a bit map system every single plane. CONSTITUTION:A image controller (IC) 11 accesses respective planes 0 to 3 and starts a plane simultaneous process (PSP) 12. The respective planes 0 to 3 read dist data. A data processing parts (DP) 14a to 14d latch the dist data to a data latching part (DL) 17. A pseudo data generating part 15 transfers pseudo data to the IC 11. The IC 11 generates fixed plotting pattern data, executes raster operation with the pseudo data and outputs them to the PSP 12. The DPs 14a to 14d latch a raster operation result to the DL 17, execute the raster operation of the raster operation result and the respective dist data, execute mask processing (making color), write the plotting pattern data in the planes 0 to 3 and display the color pattern of a straight line and so on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image processing device used in a bitmap type color display device.

(Prior Art) Conventionally, a bitmap type color display device used in a workstation or the like has a graphics controller made of an LSI (Large Scale Integrated Circuit) and a color CRT monitor. In response to commands from the host computer (CPU), the graphics controller performs drawing processing such as a straight line, a circle, etc., and BITBLT (bit
image control processing such as block transfer).

In the bitmap method, an image memory is provided to store image information (color display information) set for each pixel (pixel) on the display screen of a color CRT monitor. This image memory is also called a frame buffer.
Image information in which each pixel is composed of a plurality of 8-bit bit planes, for example, is stored.

Here, the graphics controller processes image information in the image memory in units of single planes due to limitations on the number of bins of the LSI.

Therefore, compared to monochrome display processing in which image processing is performed on 1 bit plane for 1 pixel, image processing on 8 bit planes is performed on 1 pixel.
This will require twice as much processing time.

(Problems to be Solved by the Invention) Conventionally, in a bitmap type color display device, a controller processes image information of a plurality of bit planes in units of a single plane, which requires a large amount of processing time. Therefore, when increasing the number of colors and resolution,
The image processing speed decreases, leading to a decrease in the data processing efficiency of the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing device that can process image information of multiple bit planes at high speed in a bitmap type color display device, thereby improving the data processing efficiency of the system. It is in.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a bitmap type color display device in which each pixel on a display screen is composed of a plurality of bit planes, based on a command from a host computer.
The image controller means executes image processing using a bitmap method for each single plane, and the image memory means includes a plurality of data processing means that execute data processing such as raster operations corresponding to each bit plane. The image processing apparatus includes plane simultaneous processing means that simultaneously executes access processing on a plurality of bit planes in accordance with image processing.

With such a configuration, it is possible to simultaneously process image information of multiple bit planes and realize high-speed image processing.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an image processing apparatus according to the same embodiment. This device can be roughly divided into post-computer (CPU) I (1), graphics controller (1), and graphics controller (1).
image controller) 11, plane simultaneous processing device 12
and an image memory (frame buffer) 13.

CPU10 is, for example, a central processing unit of a workstation, and outputs commands related to color image processing to image controller 11. The image controller II executes image control processing such as straight line drawing and BITBLT based on commands from the CPUIQ. The image memory 13 is a memory that stores color image information composed of a plurality of 4-bit bit planes 0 to 3, for example.
It is accessed by address A output from the image controller 11.

Plane simultaneous processing device i! f12 is each plane 0 to 3
The data processing units 14a to 14d each include a data latch unit 17, a mask processing unit 18, and a raster calculation unit 19. and a barrel shifter 20.The mask processing section 18, the raster operation section 19, and the barrel shifter 20 are components for performing high-speed logical operations necessary for bitmap image processing.The pseudo data generation section 15 is an image controller. Pseudo data rF F F F HJ or pseudo data r0000HJ is output to 11. Data latch unit 17 is a circuit that latches image information of each plane 0 to 3 or data from controller 11. Control unit I6 is a circuit that latches image information of each plane 0 to 3 or data from controller 11. This circuit performs overall control of I2.

Next, the operation of this embodiment will be explained.

First, the operation when drawing a straight line or the like, for example, will be explained. As shown in step S1 in FIG. 2, the image controller 11 outputs a predetermined address A to the image memory 13 to access each plane 0 to 3, and outputs a control signal to start the plane simultaneous processing device 12. let As a result, each plane 0 to 1 of the image memory 13
DesNation data is read from 3 (step 32). Plane simultaneous processing device 1
2, each data processing unit 1 corresponding to each plane 0 to 3
4a to 14d each have the data latch section 17 latch the destination data read from each plane 0 to 3 through the data bus Do=D3 (step S3). The pseudo data generation unit 15 generates pseudo data r000.
0HJ is output and transferred to the image controller 11 via the data bus D4 (step S4).

The image controller 11 generates predetermined drawing pattern data (
For example, 0100) is generated, and a raster operation is performed with the pseudo data transferred from the pseudo data generation section 15 (step S5). The image controller 11 receives raster calculation results (
For example, 0100) is output to the plane simultaneous processing device 12 via the data bus D4. Plane simultaneous processing device 1
2, each of the data processing units 14a to 14d latches the raster calculation results from the image controller 11 using the data latch unit 17 (step S6). Each of the data processing units 14a to 14d is connected to the image controller 1.
A raster operation is performed on the raster operation result from 1 (drawing pattern data) and each disc data, and mask processing (colorization) is executed (step 57).

Each of the data processing units 14a to 14d writes drawing pattern data, which is a processing result, to each of the planes 0 to 3 of the image memory 13 (step S8). As a result, the color pattern, such as a straight line, written in each plane 0 to 3 of the image memory 13 is displayed on the screen of the CRT display device.

Next, the image control processing of BITBLT will be explained.

As shown in step S20 in FIG. 3, the image controller 11 outputs a predetermined address A to the image memory 13 to access each plane O to 3, and outputs a control signal to start the plane simultaneous processing device 12. let As a result, source data (for example, a character string) is read from each plane 0 to 3 of the image memory 13. In the plane simultaneous processing device 12, each data processing unit 14a to 14d corresponding to each plane 0 to 3 respectively processes each plane 0 to 3.
from data bus D. -D is latched by the data latch section 17 and shifted by the barrel shifter 20 (step 521). The pseudo data generator 15 outputs pseudo data rFFFFHJ,
The data is transferred to the image controller 11 via the data bus D4 (step 522).

The image controller 11 shifts the pseudo source data from the pseudo data generator 15, outputs a predetermined address A to the image memory 13, and accesses each plane 0 to 3 (step 823). The plane simultaneous processing device I2 is
Each data processing unit 14a to 14d is connected to a data bus D from each plane 0 to 3, respectively.

~D, the data latch unit 17 latches the data (for example, a frame surrounding a character string) read through D (step 524). Furthermore, each data processing section 14a~
14d, the raster calculation unit 19 executes raster calculations on the destination data and the latched source data (
Step 525). The pseudo data generator 15 outputs the pseudo data r0000HJ and transfers it to the image controller 11 via the data bus D4 (step 526).

The image controller 11 generates pseudo source data rF F
A raster operation is performed on F F HJ and the pseudo distance data r0000 HJ (step 527). moreover,
The image controller 11 performs mask processing on the raster calculation results and outputs mask pattern data as the processing result (step 528). This mask pattern data becomes rFFFO when the lower 4 bits are masked.
This is pseudo mask pattern data that becomes HJ. In the plane simultaneous processing device 12, each data processing unit 14a to 14d
Each of the pseudo mask pattern data is latched by the data latch section 17, and the mask processing section 18 executes mask processing (colorization) (step 529). The image controller 11 outputs a predetermined address A to the image memory 13 and accesses each plane O to 3 (step 5).
30).

Each of the data processing units 14a to 14d writes the mask processing result to each plane 0 to 3 of the image memory 13 (step 531). As a result, pseudo mask pattern data is stored in each plane 0 to 3 of the image memory 13.
The mask operation result (mask operation result of the DIST data and source data) is written at the same time to the position corresponding to the bit of J, and the DIST data is written to the position corresponding to the bit where the pseudo mask pattern data is "0". They are written simultaneously.

In this way, the image information of each plane 0-3 can be accessed and processed simultaneously by each data processing section 14a-14d corresponding to each plane 0-3 of the plane simultaneous processing device 12. In this case, image controller 1
1, the pseudo data from the pseudo data generating section 15 is used to perform image processing as if on a single plane. In other words, the image controller 11 functions as an address generator and a rewrite data pattern generator for the image memory 13. and,
The plane simultaneous processing device 12 executes actual data processing (image processing) for each plane O to 3.

[Effects of the Invention] As detailed above, according to the present invention, image information of a plurality of bit planes can be processed simultaneously in an image processing device of a bitmap type color display device.
It is possible to realize high-speed processing of image information of multiple bit planes. Therefore, even when increasing the number of colors or resolution, the data processing efficiency of the system can be improved without causing a decrease in image processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a system according to an embodiment of the present invention, and FIGS. 2 and 3 are flowcharts for explaining the operation of the embodiment, respectively. II... Image controller, 12... Plane simultaneous processing device, 13... Image memory, 14a-14d...
- Plain data processing unit, 15...pseudo data generation unit. Applicant's Representative Patent Attorney Takehiko Suzue

Claims (1)

[Claims] Image memory means for storing color display information in which each pixel of a display screen is composed of a plurality of bit planes, and image processing using a bitmap method for each single plane based on commands from a host computer. and a plurality of data processing means for executing data processing such as raster operations corresponding to each bit plane of the image memory means, the plurality of bits being processed according to the image processing by the image controller means. An image processing apparatus comprising: plane simultaneous processing means for simultaneously performing access processing on planes.