JPS62183487A - Raster scan video controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a raster scan video control device used in bisotomaped alphanumeric and/or graphical image processing, and more particularly to a raster scan video control device for use in processing bi-sotomapped alphanumeric and/or graphical images. With respect to the control logic and circuitry necessary to overcome the mismatch between the number of data lines on a raster scan video controller and the number of data lines on a It is useful in CRT systems that generate and update images on video displays.

BACKGROUND OF THE INVENTION An update data cache is a mechanism by which a CRT controller with a small number of data lines can update a display memory with a large number of data lines. Particularly in high-performance color CRT systems, because pixel speed is much faster than memory time, and because each pixel is represented by multiple bits, the potential for multiple bits accessed in a display memory cycle to be extremely large. There is. This multiplicity is determined by the number of bits of pixels actually displayed and the number of pixels that can be displayed at a particular screen location. This number of pixels is related to multiple window characteristics, hidden objects within the graphics system, etc.

Most video display systems on the market today generally include a processor, a video controller, a display memory containing a single current screen image, other system memory, and a raster scan video display. . In normal (steady state) operation, the video controller continuously reads the contents of the display memory and uses this read information when the raster scanning beam is within its active display time. into the signals necessary to control. The video controller also provides horizontal and vertical retrace signals at appropriate intervals and provides raster scanning beam cancellation during retrace.

The processor also has access to the display memory so that the current screen image can be changed. This access is "through" or "around" the video controller. The present invention relates to the former type of system.

In either case, the use of the display memory is generally carefully controlled between update and display accesses to prevent interruptions while the video image is being changed.

Depending on the timing of the various components of the system, the display memory may be available for update only during vertical retrace intervals, or during both horizontal and vertical retrace intervals, or (C) during retrace periods and alternating memory cycles during the active display time of a scan line.However, in both of these cases, display memory updates are typically proceed at a slower speed than would be obtained without interference from the device's display access.

In high performance color CRT systems, the number of bits accessed in a display memory cycle can be extremely large. All CRT controllers are limited to a small number of data bits that the device can use to update or change memory.

The present invention provides a CR having a small number of data lines, for example 16.
It is intended to provide a mechanism by which a display memory having a large number of data lines, for example 128, can be updated in a T-control device. An alternative to this, for low-performance systems, is to provide display access to a CRT? There is a limit on the number of data lines on the 131I control device. Also, the use of a large number of data pins on a CRT controller significantly increases the cost of the device. Also, some C
There is a method of installing RT control devices in parallel, but this is complicated and expensive. Also, there is the ability to address memory differently, such as video access versus update access, which creates significant software problems.

Another object of the invention is to improve performance since update operations and video operations can often occur simultaneously.

(Means for Solving the Problems) The structure of the improved video control device according to the present invention is as described in claim (1).

Various embodiments of the invention are as described in claims (2) to (6). The improved video control device according to the present invention uses two types of chips:
an address module and at least one data module. This set of chips is known as BMAP and is designed to work with an external processor that generates instructions for the blue chip. The primary function of the address module is to generate video and update addresses while the data module is used to collect and integrate video data read from display memory. The video data output from the data module passes through a high-speed shift register and look-up table to the CRT.
Go to display.

The main parts of the address module are a synchronization signal generator, a window controller, an update controller, and an interface controller. The addressing module also has the ability to update the contents of the display memory according to instructions sent from the host system. Therefore, the host system does not need to access the display memory when attempting to insert any character or graphic element into the display memory. The host system simply sends the appropriate instructions and/or data to the BMAP.

The structure of the display memory is related to the operating frequency of the CRT controller and the complexity of the system. This can result in data width mismatches between the video controller, display memory, and host system.

The present invention provides an update cache for selectively updating the memory in a computer system where the data width of the memory is larger than the data width of the device that executes or controls the update. Such systems typically include one or more update devices, each of which has a plurality of signal connections through which it reads and writes data. For high performance memories, this number may be less than the number of signals provided by the memory. The present invention provides a set of transceivers with register storage for each update device.

Such a transceiver is hereinafter referred to as a registered transceiver. Each transceiver has multiple pairs of data signal connections and has control inputs that control the driving, receiving, and latching of the states of these data signals.

The total number of pairs in the set is greater than or equal to the number of data signals provided by the memory. A set of data lines connects each data signal in the memory to a unique data signal connection in each set of registered transceivers, such that each registered transceiver
In response to the control input, all memory data signals are treated the same. Another set of data lines connects each data signal of each update device to the data signal of one or more registered transceivers in the set. Each pair connecting one data signal to a memory signal connects the other data signal of the pair to the only data signal of that update device. Control logic provides appropriate control signals to select any subset of the set of registered transceivers associated with the update device. Each partial fiber has a number of data signal pairs less than or equal to the number of data signals provided by the update device. For each update access, the address module provides an address to the memory and transfers data from the memory to the set of registered transceivers or from the set of registered transceivers to the memory. Provide control signals for

Control signals are also provided for controlling the transfer of data from the update device to a selected subset of the registered transceivers or from the selected subset to the update device. The control signals further provide the ability to latch data from the update device into a selected subset of its registered transceivers. The control logic further enables simultaneous performance of video access and transfer between the update device and the selected subset, as needed and expedient.

Basically, the invention utilizes -m bidirectional registered transceivers and logic and signals to control them. The address module interface controller includes the logic and directs the distribution of control signals. The registered transceiver is placed between the display memory data line and the data line used for update access by the CRT controller or host processor. For memory updates, the video controller (BMAP) can access the display memory and latch the entire block of data into the registered transceiver in a manner similar to normal video access. The video controller can then change the data word by word. Once all changes are complete, the video control above should be
A write cycle may be used to write the updated data (in whole or in part) from the registered transceiver back to the display memory.

Random access related to update processing can be performed without changing the latched data. The transceiver/register functions as a data cache, and write operations are handled in a write-back manner.

The registered transceivers are logically grouped according to their width versus data access width.

The total number of devices used is determined by the access width of the display memory.

When using BMAP, update accesses are 16 bits, so the octal units are paired and one pair is selected for a given update access.

For high performance systems, this increases memory update speed if video operations and update operations can be parallelized. By using external transceivers/registers, video accesses can be paralleled with update accesses.

By implementing the present invention, the video controller has sufficient output signal power to allow update operations involving latched data to be performed simultaneously with video accesses to memory.

(Example) Bit Matsubu Truster Scanning Video (CRT) shown in FIG.
) The controller chip set has an address module 10 and a multiple data module 12.

The address module 10 includes a synchronization signal generator 30, an update controller 32, and a window controller 4 as main subsystems.
0 and an interface controller 34. Power supply (V
CC, Gnd) In addition to the usual connections for the clock (CLK) and reset, the following synchronization connections are made: vertical sync 100 (V5sync/C5sync)
-, horizontal synchronization 102 (H5ync), CBLANK
/IIBLANK signal 104, alternating line/vertical bluff'
) (ACLL/VBLANK) signal 106 is provided. The interface controller 34 has a connection 108 to the system bus and two memory interface connections 1)0.1)2. The window controller faces the data module side and the interface controller side, and the update controller only faces the interface controller side. The multiplications of data module 12 are selected according to need and convenience. The illustrated set of chips provides hardware support for windows in Windows alphanumeric and graphical raster scan video (CRT) display systems used in computer systems having one or more main processors, and provides hardware support for windows in multitasking computing systems. It is particularly advantageous for use with. The hardware support includes logic circuitry that allows multiple parallel windows to be programmed within the chip. This feature allows the CPU to maintain multiple window bit-mapped displays almost as easily as it maintains a conventional alphanumeric display.

The term "video access" is used herein to refer to an access to read the contents of display memory to be displayed on a screen. On the other hand, "update access" refers to a memory access used to update the contents of the display memory. "Update operation"
The term refers to the transfer of information between the update device and the registered transceiver. In embodiments of the invention, each video access and update access consists of 16 to 256 bits, and update operations always consist of 16-bit words. Of course, more extended systems may have a minimum access width of 32 bits, and update operations also involve 32 bits. The above video access is calculated in a superimposed manner as follows. When a display address is presented, the display memory (item 13 in FIG. 2) outputs the entire block of information stored at the display memory address. Data reads then go to a data accumulation module (not shown) or directly to shift register 15.

During update operations that do not access data already in registered transceiver 14, the BMAP address module outputs a "local address" along with the display address to select a 16-bit word from display memory. The local address is used to select the desired word from the corresponding video access. A total of 4 bits in the local address is required when using BMAP in a system with 8 bits per pixel and 32 pixels per video access.

The 18 most significant bits in the pixel address represent the 18 bit video address.

Since a 16-bit word consists of 16 1-bit pixels for monochromatic display systems and 2 pixels for systems with 8 bits per pixel, the pixel address offset can range from 1 bit to 4 bits. Can have varying lengths. There are various possible calculations, but their explanations will be omitted.

FIG. 2 is a block diagram of an elaborate system including an address module 10 and a data module 12. The data output by the data module then passes through a high speed shift register 15 and a color lookup table 17 to the video display 19.

The address module 10 also includes one or more host processors 1) and system memory 1) 4 (Il
The display memory 13 has the ability to update the contents of the display memory 13 in accordance with instructions sent from a host system having a host system (not shown).

Therefore, the host processor 1) does not need to access the display memory 13 if it wishes to insert any character or graphic element into the display memory 13. Instead, the host processor need only send the appropriate instructions to address module 10. To that end, the system comprises a data transceiver 1) 6 for interfacing said address module to the system bus, and an address transceiver 1) 8 for interfacing the address module and display memory to the system bus.

After receiving instructions sent from the host system, address module 10 executes the instructions one by one as if it were a dedicated microprocessor. Since the entire procedure is controlled by internal hardware, the instructions are executed in a very short time. In general, insertion speeds are 5 to 5 times faster than software procedures on the host processor.
0 times faster.

To prevent the transfer, the host processor also:
Address module 10 can be used in DMA/BitBit mode. The DMA/BitB1 procedure is similar to the character insertion procedure.

The data module 12 has 32 data inputs on the display memory 13 side and 8 data outputs on the shift register 15 side. By setting appropriate control inputs, one or more data modules can be used for a variety of applications. All systems that apply sequential memory access to increase data read speed need to include a data module (or equivalent hardware) in the back end.

Since the structure of display memory 13 is a function of the raster scan video controller's computational frequency and system complexity, FIG. 3 shows a typical memory structure that may be used with a BMAP chimp set.

For memory updates, the address module 10 reads the display memory in the same way as for video access;
The entire block of data can then be latched into a set of bidirectional transceivers/registers 14. These transceivers/registers 14 (e.g. 74F646)
is located in the data path used to update the display memory and acts as an update cache for the video controller. Therefore, the address module can change data word by word.

When the last word is changed, the address module 10
This updated data is written from transceiver/register 14 to display memory 13.

"Random" update accesses can also be made without latching the data.

The number of transceiver/register devices used is determined by the access width of the display memory. In the present embodiment (BMAP) this is 16 to 256 bits and correspondingly 4 to 32 octal units (eg 74F646) are used. Registered transceivers are grouped according to their width relative to the width of update operations. In the case of BMAP, the update operation is 16
Bits and therefore octal units are paired, and one pair is selected for a given update operation.

By using external transceivers/registers, video accesses can be paralleled with update operations. This means that under certain circumstances BMAP can do two things at the same time. Table 1 shows the need for registered transceivers for various applications.

The control logic must, of course, provide the necessary control signals to the selected registered transceiver. These may change in detail, but basically they function to control all of the following operations.

(a) Capture/latch the number of data bits in the display access from the display memory and send the number of bits in the selected set to the CRT controller or host processor in the update operation.

(b) Sending the number of bits of the selected set in the update operation from the latched data to the CRT controller or host processor.

(C) Capture/latch data from the CRT controller or host processor into the selected set of bits during the update operation.

(dl Sends the number of bits of the set selected in the update operation to the display memory from the CRT controller or host processor, along with latched data to balance the number of bits in the display memory. may be from a previous type (a) or type (C) operation.

(e) the number of bits selected in the update access,
It is passed from display memory to the CRT controller or host processor without latching or affecting previously latched data.

(f) optionally latching the number of bits of the set in the update access;
or from a CRT controller or host processor to display memory without affecting previously latched data.

(gl Optionally writes the number of bits in the display access from the previously latched data to the display memory.

This latched data may be from a previous type (a) or type (C1) operation.

(f) and (g) are extensions to the set of functionality necessary to the invention, some of which may or may not be illustrated by the examples.

In an optimal implementation of the invention, the video display controller selects an output signal sufficient to allow update operations of type (b) and type (C) to occur simultaneously with display accesses to memory. . Therefore, type (bl
If the occurrence of accesses of type (C) and (C) is maximized, the update speed is improved.

This updates the video display control to
This means that several consecutive update operations should be ordered/grouped so that they fall within the same display memory access.

To the extent that such ordering or grouping is common for procedures for updating pitted video display images, the actual update operations are accessed to read the information that directs the update process. So, scattered/
There is a tendency to take turns. For example, virtually all Bitmap video display controllers access information in the "source" and "destination" areas of display memory. The latter represents the actual update of the image, and the former is access to information that directs the update. Adds "instruction" access to these types, which also directs updates. In the present invention, these accesses scattered to other areas are handled by phantom operations of type tel and (, in which the data latched within registered transceiver 14 is not affected.

In the BMAP embodiment shown in FIG. 3, control information is output from the interface controller 34 shown in FIGS. 1, 4, and 5 by four local address lines and three status lines 52. be done. The local address lines serve to select one pair of registered transceivers from two to sixteen pairs. The status line indicates the type of access being performed, ie, video access or update operation.

In this example, a programmed logic array (P
Using external logic in the form of LA) 54, these signals are
Transform the control signals required by the registered transceiver used.

Decoders on the four local address lines are also required.

Regardless of the embodiment, the information output by the control logic must include the following for each update operation: (1) direction (read/write access); (2) selection to registered transceiver 14 (local address); and (3) for reading, whether the source of the data is display memory 13 or the registered transceiver. 1
(4) For reading from display memory 13,
whether data should be latched into the registered transceiver 14; (5) whether the data should be latched into the registered transceiver 14;
whether the data should be output to display memory 13; and (6) whether data from video controller 10 should be latched into registered transceiver 14 for writing.

Since data is cached write-punk rather than write-through, the control logic needs to include provision for writing the data back to display memory at the appropriate time (see point above). 5)). In this embodiment, this is true, namely the destination local address 50
all of the appropriate number of lower order bits (1 to 4) are 7, or when the access is the last of the block at the destination (left OR gate 56 in FIG.
) is clearly understood. Address (points (3), (4) above)
)) is also clearly known, so a new access to the display memory 13 is required. When the appropriate number of lower order bits (1 to 4) of the destination local address 50 are all zeros, or when the access is the first of a block of data at the destination (OR in Figure 5). gate 58) is indicated. A single write operation is handled by sending a signal at the beginning and end so that a block of bits of the display memory width is first read. The block is then rewritten with an equal number of bits during an update operation. The bits are changed by the video display controller or host processor.

The mask register 60 in FIG. 5 is programmed during system initialization to correspond to the width of display memory 13 accesses and the number of registered transceiver pairs 14. This is how many lower local address bits must be 1 to cause a writeback to occur, and how many lower local address bits must be 0 to cause a new read from display memory 13 to occur. control whether it should be done or not.

- A membrane variant adds a set of latches for the display memory address (i.e. for the upper part of the update address) and a comparison between the contents of this latch and each new address. , and a single bit flag to record whether the data in the registered transceiver has been updated. Therefore, an algorithm of the following form can be used to control the cache. In the following algorithm, n is the ratio of the number of bits in the display access divided by the number of bits in the update access.

Algorithm New memory address: = Update address DIVn Local address: = Update address MODn Access type, NEQ,
If “destination”, read block (new memory address) Otherwise (ELS B) New memory address, NEC, if old memory address, write block (old memory address) Update flag: = false Next If it is like this, it is the end. (END IF) If the block is continuously generated, it is the end. (END IF) If the block is like this, it is the end. (END IF) If the block is like this, it is the end.
IF) If access type = "write", latch the transceiver (local address) Update flag: = true otherwise (ELSE) Transceiver read local address) End if as follows (END IF) Interface to new 1 The processing is controlled by an 18-bit address, a local address, and a "type 2" output provided by the address module's window controller. The need for the 18-bit address depends on whether the update operation requires an update access. The update controller 32 is 3
Generate types of operations. Two of them must access display memory or system memory. The hardware used to generate the local address and "type 2" output is shown in FIG.

As shown in Figure 5, PC (program counter), D
A 4-bit address port is used to output one of the local addresses stored in C (destination counter) and SC (resource counter). External transceiver/register 14 using 4-bit mask register 60
Define address boundaries for If the operation is on the "first" word of the update access, then the BMA
P reads the destination pattern from display memory;
It is necessary to latch this data into transceiver/register 14 and read the required 16 bits of this latched data.

If the update operation is for the "last" term of the update access, the BMAP needs to combine the write operation with an access that writes the entire data block from the transceiver/register 14.

If the update operations are the first and last operations of an update access, the BMAP performs a read-modify-write operation directly to the display memory 13. Table 2 shows eight types of accesses related to output controllers.

Table 2 Type 2 Control Outputs Connected to external PLA 54 for generation of control signals for three Type 2 output terminals or corresponding DRAM 13 (display memory) and transceiver/register 14 for update access. . Both the ``type 2'' output and the ``local address'' output are LAS'', as in the cycle of display memory access.
(Local Address Strobe) signal and negated by the LDTACK" (Local Address Acknowledge) signal.

[Brief explanation of drawings]

1 is a block diagram of a bitmap alphanumeric and graphical display controller that may utilize the present invention; FIG. 2 is a block diagram of a sophisticated display system employing the controller of FIG. 1 and the present invention; and FIG. Figure 4 is a block diagram of the structure of a display memory system showing the present invention; Figure 4 is a block diagram of an interface controller used with the present invention; Figure 5 is a block diagram of an update address output controller used with the present invention. It is a line diagram. 10...Address module, 12...Multiple data module, 13...Display memory, 14...
- Registered transceiver, 30... Synchronization signal generator, 32... Update controller, 34... Interface controller, 40... Window controller, 54... Program logic array.

Claims (8)

[Claims] (1) An update cache having a first bit width for selectively updating the display memory under the control of an update device having a second bit width smaller than the first bit width. A raster scan video controller comprising a set of registered transceivers, each having a plurality of pairs of data signal connections, and each of which has a total number of pairs in said set provided by said memory. control inputs for controlling the driving, receiving and latching of said data signal connections to be at least equal to the number of data signals; a plurality of data lines connecting each data signal of said memory to a unique data signal in each said set of registered transceivers so as to treat all memory data signal connections identically; such that each pair of signal connections connects the other data signal connection of said pair to a unique data signal connection of said update device;
a plurality of data lines connecting each data signal connection of said update device to a data signal of one or more registered transceivers in said set; and a plurality of data lines of said set of registered transceivers associated with said update device. means for selecting any one of said subsets, each said subset having at most a number of data signal connection pairs equal to the number of data signal connections provided by said update device. and means for addressing the memory and transferring data from the memory to a set of registered transceivers; and means for addressing the memory and transferring data from the set of registered transceivers. means for transferring data to said memory; means for transferring data from said updating device to said registered transceiver of said selected subset; and means for transferring data to said updating device; means for transferring data from the update device into said selected subset of said registered transceivers; and means for latching data from said memory into said set of registered transceivers. and means for latching to the raster scan video controller. 2. The raster scan video controller of claim 1, wherein the registered transceiver is replaced by a functionally equivalent set of drivers, receivers, and latches. (3) comprising means for simultaneously reading said data from memory and providing a selected subset of said data to an updating device without latching the data; The raster scanning video control device according to item (2). (4) Means for simultaneously reading data from memory, latching the data into a set of registered transceivers, and providing a selected subset of the data to an update device. The raster scan video control device according to item (1) or item (2). (5) simultaneously transfer data from the update device to its registered transceivers of the selected subset, combine said data with data latched from other transceivers of the set, address memory, and A raster scan video controller as claimed in claim 1 or 2, including means for transferring the combined data to said memory. (6) addressing and transferring data to or from memory and, at the same time, unrelated data of one or more update devices and their registered transceivers of a selected subset; Claim No. 1 includes means for transferring to and from the latch.
) or (2). (7) The raster scanning video control device according to claim (1), (2)... or (6), wherein the first bit width is an integral multiple of the second bit width. update cache for use in (8) Claims (1), (2), ... or (6), wherein the display memory has multiple pixel storage capability for each on-screen pixel position. A CRT display station comprising a raster scan video control device as described in Section 1.