JPS63223970A - Information processor - Google Patents

Abstract

PURPOSE:To execute read-out and write processings of a display data shifted against a word boundary at high speed, by providing an even address graphic memory, an odd address graphic memory and a character generator, etc. CONSTITUTION:When a display data and a command are inputted to an input/ output control part 107 through a signal line 110, a CPU 100 starts its display operation. At the time of a display operation of a character pattern stored in a character generator CG 102, even when a pattern data which the CPU 100 write to a real byte address (n) is shifted from a word boundary, a write pattern data is written simultaneously to the real byte address (n) and (n) + 1. Also, even at the time of an operation for displaying a pattern on other position in an even or odd address graphic memory 105, 106, when it is shifted from the word boundary, a read pattern is read simultaneously from a real byte address (m) and (m) + 1. In such a way, write and read-out processings can be executed at high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device suitable for displaying characters, figures, etc., and particularly relates to a CRT or liquid crystal display used in word processors, personal computers, etc. Alternatively, the present invention relates to read/write control for rapidly reading and writing display data such as characters and figures to be recorded and displayed on a record on a graphic memory using links and links.

[Conventional technology]

In recent years, in Japanese word processors and personal computers, CRTs and liquid crystal displays display characters, figures, etc. on the surface, so the degree of freedom in display content is large.
Display devices that employ a bitmap display method using a graphic memory in which a 1-bit storage element corresponds to a dot have come into widespread use.

The disadvantage of the bitmap display method is that the display image for one display screen must be written to the graphics memory corresponding to one dot, which slows down the display speed, and if the display contents are to be changed frequently, this writing process must be controlled. This increases the load on the processor (hereinafter referred to as CPU), which delays processing for other controls.

To this end, methods have been proposed to speed up the process of writing display data to the graphic memory and to reduce the load on the CPU for this process. JP-A-60-26
The display method described in Japanese Patent No. 0989 is intended to reduce the load on the CPU for bit shift processing and compositing processing with background data when writing (update) data to a graphic memory.

[Problem that the invention seeks to solve]

However, the conventional display methods described above do not take into account memory access for reading display data for compositing from graphic memory or writing display data after compositing to graphic memory, and do not consider word boundaries by bit shifting. If you want to update data that exceeds the
Multiple write operations were required for this data.

[Means for solving problems]

In order to achieve this object, the present invention includes an odd address memory section that stores display data of odd word addresses that can be accessed independently and simultaneously in a graphic memory, and an even address memory section that stores display data of even word addresses. providing read/write means with read data from the odd address memory section and read data from the even address memory section to a first data shift means;
read data generation means for generating data to be sent to the data transfer means from the data output from the second data shift means; and write data to the odd address memory section from the display data output from the second data shift means. write data generating means for generating write data to the even address memory section; and determining an access address for the memory section and an access address for the other memory section from the word address for the one memory section given from the data transfer means. The present invention is constructed such that the data exceeding the word boundary is simultaneously read from the other memory section by a shift, and the data exceeding the word boundary is written into the other memory section by the shift. Features.

[Effect]

At the time of reading, when a word address indicating the read position is given from the data transfer means, the access address generation means
Access addresses are generated for two memory sections, a memory section having the word address and another memory section having a word address adjacent to the word address. The read data generation means simultaneously reads read data corresponding to the two memory parts from the memory part of the word address and another memory part having a word address adjacent to the word address, and reads data from the read data at a word boundary. Obtain straddling data. Therefore, even if read data spans two word addresses, it can be read from the graphic memory in one read process.

Further, during writing, if the word-by-word display data given from the data transfer means together with the word address indicating the write position is shifted and crosses a word boundary, the write data generation means generates the write data for the memory section at the word address. 1
Write data for another memory section having a word address adjacent to the word address is generated from the display data beyond the word boundary, and the access address generating means generates access addresses for the two memory sections. As a result, the write data of the two word addresses are simultaneously written to the two corresponding memory sections. Therefore, even if the display data transferred word by word spans two word addresses due to the shift process, it can be stored in the graphic memory in one write process.

With the above operations, the transfer process of reading display data spanning two word addresses on the graphic memory and writing it to a position spanning the two word addresses is completed with one read process and one write process.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 2, the display device according to the present invention includes a CPU 100 that controls one display device and exchanges data with peripheral memory in units of one byte, and stores programs and data for operating the display device. Program memory 1
01, a character generator (hereinafter referred to as CG) 102 that stores character pattern data as shown in FIG. When the CPU 100 writes pattern data to be displayed on the CRT monitor 108 to an arbitrary position in the graphic memories 105 and 106, the CPU 100 shifts the pattern data to be displayed on the CRT monitor 108.
5, 106, performs logical processing with the old pattern data written to the write address to generate a new pattern, and writes the new pattern data to the graphic memory 105, 106, and the CRT monitor 108. a peripheral control circuit 104 that performs a process of reading data from graphic memories 105 and 106 in order to display patterns on a CRT monitor 108; and a graphic memory 105 that stores pattern data to be displayed on a CRT monitor 108.
, 106, and an input/output control unit 107 for causing the CPU 100 to receive display data and commands sent from an external device to the display device via the signal line 110, and for transmitting a response from the CPU 100 to the external device. , a CRT monitor 108 for displaying patterns such as characters and figures, the CPU 100 and a program memory 101 . C:G10
2. An internal wiring path (C
PU bus) 109.

FIG. 1 shows the internal configuration of peripheral control circuit 104 in FIG. 2. As shown in FIG.

In FIG. 1, the control signal generation circuit 1 outputs one of the control data latch (A) 6 and the control data latch (B) 16 in the peripheral control circuit 104 based on the CPU access signal and the operation clock signal CLK. A register selection signal is sent to write data from the CPU 100 to either one of the control data latch (A) 6 or control data latch (B) 16, or data is written to the background data latch 14 or data buffer 13. Address selector (A) 4. Sends out latch signals and data output signals. (B
) 5, and at the same time generates a control signal for the graphic memories 105 and 106.
Write data starting from 00, or send a data latch signal or data output signal to the background data latch 14 or data buffer 15, and also send the data latch signal or data output signal to the address selector (
A)4. (B) Sends a CPU address selection signal to the address selector (A) 5, and simultaneously generates a control signal for the graphic memories 105 and 106 to cause the CPU 100 to read data from the graphic memories 105 and 106, or゜ (B) Sends a CRT address selection signal to 5, and at the same time sends a CRT address selection signal to graphic memory 10.
5, 106 and a data latch signal to the shift section 17, and write a video signal to be displayed on the CRT monitor 108 to the shift section 17.

Access to the graphic memories 105 and 106 is performed in one display data read access as shown in FIG.
The time it takes to read out the next display data and C
The PU access time is divided into two parts, each accessing the graphics memory at an independent address, and the next display data and the CPU writing or reading from the graphics memory.

As shown in FIG. 4, the address converter 2 converts the graphic memory 105° 106, which is configured into 1024 dots (128 bytes) horizontally and 1024 dots vertically, into a CRT monitor 108 whose display size in the vertical direction is 512 dots. If not, divide it into area 0 and area 1 at the border of 512 vertical dots, and set area (0) used as an area for storing data to be displayed on the CRT monitor 108 to a byte address that can speed up the display processing of characters, etc. The area (1) has a vertical address structure in which the addresses increase sequentially in the vertical direction, and is used as a storage area for data used by the CPU 100 during program execution.
This enables a horizontal address configuration in which byte addresses increase sequentially in the horizontal direction, and also allows the CRT monitor 108
If the vertical display size exceeds 512 dots, all areas of the graphic memories 105 and 106 are
It is used as an area for storing data to be displayed on the RT monitor 108, and enables a vertical address configuration in which byte addresses increase sequentially in the vertical direction so that writing processing to display data such as characters can be speeded up. So, CPU1
The address signal from 00 is sent to the graphic memory 105,
106 into address signals CAO to CAl6.

The address converter 2 includes a CPU 10 as shown in FIG.
Address signal 0 to A16 from 0 is converted into address (hereinafter referred to as real byte address) CAO-CA16
It is composed of an address cross (A) 201, an address cross (B) 202, and a data selector 203, and the data selector 203 includes control data latches (A) 6 (7) DC, VSO, VSI, and CPU. Address signal A16 is input as a control signal. The address cross (A) 201 and the address cross (B) 202 are the address signals AO-A from the CPU 100 so as to correspond to the vertical address (A) and the vertical address (B) in the address conversion correspondence table shown in FIG.
16 into real byte addresses CAO to CAl6, and as a result, the byte addresses of the graphic memory 105 and 106 seen from the CPU 100 change depending on each conversion mode as shown in FIG.
It is converted from a real byte address configured to increase sequentially in the horizontal direction of .degree.106. When I advise you,
Graphic memory 105, 10 seen from CPU 100
Even if the address No. 6 is a vertical address and the CPU 100 generates the corresponding address, the real byte addresses CAO to CA output from the address converter 2
l6 is an address configured to increase sequentially in the horizontal direction of the graphic memories 105 and 106.

The adder 3 adds the real byte addresses CAL to CAl6 and CAO, and when the real byte address converted from the address signal sent from the CPU 100 to the graphic memory 105, 106 becomes an odd number, it becomes an even address. For the graphic memory 105, even-numbered addresses of adjacent graphic memories in the increasing direction of the address are generated. At this time, the CA of the real byte address is stored in the odd address graphic memory 106.
L to CAl6 are applied as they are.

When the real byte address is an even number, CAO is O, so the real byte addresses CAL to CAl6 are applied as they are to the even address graphic memory 105 and the odd address graphic memory 106. Due to the above,
If the real byte address is an even number, 16 bits of the even address memory indicated by the real byte address and the adjacent odd address memory in the increasing direction of addresses are selected at once, and if the real byte address is an odd number, the real byte address is selected. It becomes possible to collectively select 16 bits of the even address memory indicated by the byte address and the even address memory adjacent in the direction of increasing address.

Address selectors (A) 4 and (B) 5 are for generating address signals to be applied to each even address graphic memory 105 and odd address graphic memory 106, and the CPU Real address from 100 or C
Select one of the display data addresses from the RT controller 103 and store it in the graphic memory 105, 10.
The signal is applied to 6 row addresses and column addresses in a time-division manner.

The CPU data through signal generator 7 allows the CPU 100 to control the graphic memories 105 and 106 based on the address signal of the CPU 100 and each control signal of the control data latch (A) 6.
When accessing area 1 of It happens. The mode in which the shift amount is forcibly set to O and the data and data of the CPU 100 are output as they are without performing synthesis is the logical sum or logical product of each control signal of the control data latch (B) 16 and the CPU data through signal. The resulting signal is sent to the shift section (A) 9 described later. Shift part (B) 1
0. Setting is possible by adopting a configuration in which the data is sent to the shift section (C) 11 and the write data synthesis section 12.

The control data latch (B) 16 is a data latch group that latches a control value for selecting the data shift amount or synthesis method of the data shift synthesis section.

FC is a data latch that specifies the compositing method, and DN is a data latch that specifies the amount of shift of data to be written from the CPU 100 to the graphic memories 105, 106 from the word boundaries of the graphic memories 105, 106, as shown in FIG. , and R8N is the CPU as shown in FIG.
100 is a data latch that instructs the amount of shift of data to be read into the graphic memories 105, 106 from the word boundary of the graphic memories 105, 106, and WSN is a data latch that indicates the shift amount from the word boundary of the graphic memories 105, 106 to be read from the CPU 100 to the graphic memories 105, 106 as shown in FIG. This is a data latch that indicates the data start position of the data to be written as a shift amount from the word boundary of the CPU 100.
This is a data latch that indicates the data width of data to be written from 00 to the graphic memories 105 and 106 in the number of bits.

The write dot instruction pattern generator 8 generates 1 bit from 1 bit to 8 bits from dO to d7 as shown in FIG. 12 according to the value of WN of the control data latch (B) 16.
A write dot designation pattern MD, which is a data string, is generated. In Fig. 12, perspective part (III)
indicates 1.

It generates a shift instruction pattern MD.

The flute section (A) 9 is a 16-bit data rotator, and the first rotator is rotated according to the DN value of the control data latch (B) 16 and the CAO value of the graphic memory real byte address.
Do the write dot instruction pattern MD as shown in Figure 2.
The data write position designation pattern SMD is generated by rotating in the direction from d15. If the real byte address CAO is 0, rotate to the position shifted by the value of the data latch DN from do as shown in FIG. 12(a), and if the real byte address CAO is 1, the first
As shown in FIG. 2(b), the rotation is made to a position shifted from d8 by the value of the data latch DN.

The shift unit (B) 10 is a 16-bit data rotator and controls the data latch DN of the control data latch (B) 16.
, WSH value and graphic memory real byte address C
According to the value of AO, the write data WD is rotated in the direction from dO to d15 as shown in FIG. 13 to generate a write data rotation pattern SWD. When the real byte address CAO is O, data latch DN (DN-WS
If the real byte address CAO is 1, the value obtained by subtracting the value of data latch WSH from the value of data latch DN from d8 as shown in FIG. 13(b) (DN-WSN). It rotates to the shifted position. As a result, the start position of the write data matches the data write position instruction pattern SMD.

The background data latch 14 latches the 16-bit background data RD read out from the graphic memories 105 and 106 during the CPU access time shown in FIG. 3 in response to a signal sent from the control signal generation circuit 1.

The write data synthesis section 12 generates a data write position instruction pattern SMD and a write data rotation pattern SWD which are outputs of the shift section (A) 9, shift section (B) 10, and background data latch 14.

Based on the background data RD and the value of data latch FC of control data latch (B) 16, SMD sets SWD and RD to 1.
The graphic memory 10 performs synthesis such as logical product, logical sum, exclusive OR, etc. (@E part) for the part, and outputs the RD as it is (part II) for the other parts.
5, 106 and outputs it.

As a result, if the real byte address CAO is 0, the first
If the write data of the CPU 100 is located at a position rotated from dO by the value of the data latch DN as shown in Figure 4 (a), and the real byte address CAO is 1, then the data written in Figure 14 (
As shown in b), the write data of the CPU 100 is located at a position rotated from d8 by the value of the data latch DN.

The shift section (C) 11 is a 16-bit data rotator and the data latch R3 of the control data latch (B) 16.
CAO of N value and graphic memory real byte address
The background data RD read from the graphic memories 105 and 106 as shown in FIG.
5 in the direction of dO to generate CPU read data SRD. If the real byte address CAO is 0, d as shown in FIG. 14(a).

When the real byte address CAO is 1, bit rotation is performed by the value of data latch R5N toward
), the bit rotation is performed by the value (R3N+8) obtained by adding 8 to the value of data latch R8N toward do. As a result, the start position of the read data on the CPU read data SRD coincides with dO.

The shift section 17 latches and sequentially shifts the 32-bit display data read out twice from the graphic memories 105 and 106 during the display data readout time shown in FIG. 3 in response to a signal sent from the control signal generation circuit 1. It converts the data into serial data and outputs it.

Note that the numbers attached to the signal lines mean the number of lines.

Next, the operation of the display device having the above configuration will be explained.

When display data and display commands are input from an external device to the input/output control unit 107 via the signal line 110, the CPU 1
00 detects this, analyzes the display command, and starts the display operation.

When displaying a character pattern stored in the CG 102, the address of the character pattern stored in the CG 102, the write address of the graphic memories 105 and 106 into which pattern data to be displayed are written, and the shift value DN are used. , the composite instruction value FC, the write data start position instruction value WSN, and the write data width instruction value WN are calculated, and then the shift value DN, the synthesis instruction value FC, the write data start position instruction value WSN, and the write Data width instruction value WN
are written to the corresponding data launches in the control data latch (B) 16, respectively. Next, pattern data to be written to the graphic memories 105 and 106 is read from the corresponding address of the CG 102 and written to the corresponding address of the graphic memories 105 and 106 via the peripheral control circuit 104. At this time, the peripheral control circuit 104 performs the following write operation on the graphic memories 105 and 106 during the CPU access time when the graphic memories 105 and 106 are accessed in a time-divided manner as shown in FIG.

■Graphic memory 105 in address converter 2
．． A write real byte address n to 106 is generated.

(a) If n is an even number, n is applied to the even address graphic memory 105 and n+1 is applied to the odd address graphic memory 106 from the adder 3, the address selector (A) 4, and the address selector (B) 5.

(b) If n is an odd number, apply n+2 to the even address graphic memory 105 and apply n+1 to the odd address graphic memory 106.

As a result, when the real byte address n is an even number, 16 bits of the even address graphic memory 105 indicated by the real byte address n and the even address graphic memory 106 adjacent in the increasing direction of addresses are selected at once, and the real byte address n is selected. When the byte address n is an odd number, the odd address graphic memory 106 indicated by the real byte address and the even address graphic memory 105 adjacent to each other in the increasing direction of addresses can be selected by 16 bits at once.

(2) Send access signals RAS and CAS to the graphic memories 105 and 106, read background data from the address selected in (2) above, and latch it in the background data latch 14 to obtain background data RD.

■■ At the same time, the write pattern generator 8. Shift part (A
)9. Shift part (,B)10. Write data synthesis section 12
As shown in Figure 14, (a) If n is an even number, for the 16 bits starting from do, from dO to D
Data in which the write pattern is located at a position shifted by N bits is generated.

(b) If n is an odd number, for 16 bits starting from d8, generate data in which the write pattern is located at a position shifted by DN bits from d8.

When the background data latch operation of
6, the write data generated in step (3) is sent, and at the same time, the data write signal WE is sent to the graphic memories 105 and 106, and the data generated in step (2) is written.

As a result of the above, as shown in FIG. 16, even if the pattern data written by the CPU 100 to real byte address n is shifted with respect to a one-word boundary, the written pattern data is are written at the same time. As a result, the conventional writing operation that was performed twice for real byte addresses n and n+1 as shown in Figure 15 can now be done in one time, making it possible to speed up the writing process and The same speed can be obtained regardless of the speed.

Next, when a display operation is performed to display a pattern stored in the graphic memories 105 and 106 at another location, the address of the pattern stored in the graphic memories 105 and 106 is used.

Graphic memory 105 in which patterns to be displayed are written
．． 106 write address, Schifmil value DN, composite instruction value FC, write data start position instruction value WSN,
The write data width instruction value WN and the valid start position instruction value RSN of the read pattern data are calculated, and then the shift value DN is calculated.
, composite instruction value FC, and write data start position instruction value W
SN, write data width instruction value WN, and valid start position instruction value R8N are respectively written into the corresponding data latches in the control data latch (B) 16. Next, from the corresponding address of the graphic memory 105, 10.6, the peripheral control circuit 1
The pattern to be moved and displayed is read out via the peripheral control circuit 104 and then transferred to the graphic memory 105, 1 via the peripheral control circuit 104.
Write to the corresponding address of 06. At this time, the peripheral control circuit 104.

The graphic memory 105 is time-divided as shown in FIG.
During the CPU access time when accessing the graphic memories 106, the following read operation is performed on the graphic memories 105 and 106, and pattern data is written by the write operation described above.

■Graphic memory 105 in address converter 2
．． A real byte address m to be read into 106 is generated.

■ Adder 3 and address selector (A) 4. From the address selector (B) 5, (a) If m is an even number, m is applied to the even address graphic memory 105 and m+1 is applied to the odd address graphic memory 106.

(b) If m is an odd number, m+2 is applied to the even address graphic memory 105 and m+1 is applied to the odd address graphic memory 106.

As a result, when the real byte address m is an even number, 16 bits of the even address graphic memory 105 indicated by the real byte address m and the adjacent odd address graphic memory 106 in the increasing direction of addresses are selected at once, and the real byte address m is When the byte address m is an odd number, the odd address graphic memory 106 indicated by the real byte address and the even address graphic memory 105 adjacent to each other in the increasing direction of addresses are collectively made 16-bit selectable.

(2) Send access signals RAS and CAS to the graphic memories 105 and 106, read data from the address selected in (2) above, and latch it in the background data latch 14 to obtain background data RD.

(2) As shown in FIG. 11, by the shift section (C) 11.

(a) If m is an even number, for 16 bits starting from dO, a pattern at a position shifted by R8N bits from do is generated as 8-bit read data.

(b) If m is an odd number, for 16 bits starting from d8, a pattern at a position shifted by R3N bits from d8 is generated as 8-bit read data.

The read data generated in step 2 is sent to the CPU 100 via the data buffer 15.

As shown in FIGS. 9 and 11, the CPU
Even if the pattern read by 100 from real byte address m is shifted with respect to a word boundary, the read pattern is read from real byte addresses m and m+1 simultaneously. As a result, the conventional two-time read operation for real byte addresses m and m+1 as shown in Figure 15 can now be done in one time, making it possible to speed up the read process and to You will get the same speed.

The above read operation and the above write operation allow you to move the display on the display screen and to move the graphic memo 1J105, 1
It is possible to speed up display processing of pattern data stored in 06.

Next, some of the graphic memories 105 and 106 are transferred to the CPU.
The operation when used as a data area of 100 will be explained. When using the graphic memories 105 and 106 as the data area of the CPU 100, the CPU 100
The data must be read or written with a shift amount of 0 relative to the word boundary. In this case, the CPU
100 is.

Control value DC in control data latch (A) 6 is set to 1, VSO
1. Write data to the control data latch (A) 6 so that DTO becomes O, VSI becomes O, and DTI becomes 1. As a result, the graphic memory 105 and 106 are used by the CPU 100.
As shown in Figure 4, area (0) and area (1)
It is divided into two areas. Area (0) is an area where the addresses increase in the vertical direction and the data shift synthesis process described above is performed, and area (1) is an area where the addresses increase in the horizontal direction and data is transferred without performing the data shift synthesis process described above. This is an area that will be ignored. When the CPU 100 accesses area (1), the CPU data through signal generator 8 detects from the address signal AO-A16 of the CPU 100 that the CPU access is to area (1), and activates the control data latch ( B) Send a CPU data through signal to 16. Control data latch (B) 1
6 is a control data latch (B
)16 output value FC:, DN, R8N.

Forcibly set the shift amount of each of WSN and WN to O, and set the data of the CPU 100 as a value to be input/output as it is without performing synthesis, and output it. As a result, CP for area (1)
Since the access by U100 is not affected by the data, area (1) can be used as a data area, and the graphic memories 105 and 106 can be used effectively.

〔Effect of the invention〕

As described in detail above, when the present invention is used, the peripheral control circuit reads data from the graphic memory that straddles a word boundary, which is a data processing unit of the graphic memory, and causes the data to straddle the word boundary of the graphic memory. Even when writing to a position, it becomes possible to perform processing at the same speed as a lifter that coincides with a word boundary, making it possible to speed up the reading and writing process.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the peripheral control circuit according to the present invention, Figure 2 is a block diagram of the peripheral control circuit according to the present invention.
The figure is a block diagram of the display device according to the present invention, FIG. 3 is a timing diagram explaining each operation when the peripheral control circuit accesses the graphic memory, and FIG. 4 is a timing diagram explaining the area division of the graphic memory. 5 is an explanatory diagram of an address translation correspondence table for explaining the operation of the address converter according to the present invention, FIG. 6 is a block diagram of the address converter according to the present invention, and FIG. 7 is a diagram showing the address converter according to the present invention. 8 is an explanatory diagram of the character pattern, FIG. 9 is an explanatory diagram of the pattern read position, FIG. 10 is an explanatory diagram of the pattern write position, and 11th The figure is an explanatory diagram of the operation of the shift section (C), the first
FIG. 2 is an explanatory diagram of the operation of the shift section (A), FIG. 13 is an explanatory diagram of the operation of the shift section (B), FIG. 14 is an explanatory diagram of the operation of the write data synthesis section, and FIG. 15 is a conventional method. FIG. 16 is an explanatory diagram of a data writing/reading method according to the present invention. 1... Control signal generation circuit, 2... Address converter,
3... Adder, 6... Control data latch (A), 7
. . . CPU data through signal generator, 8 . . Write dot instruction pattern generator, 9 . . . Shift section (A).
10...Shift part (B), 11...Shift part (C)
, 12...Write data synthesis unit, 14...Background data latch, 16...Control data latch B, 105...
- Even number address graphic memory, 106... odd number address graphic memory.
Voice, □HJ:. Agent Patent Attorney Katsuma Ogawa - 23 Aoi 1M No. 10 kuchiri ni S shaku ○ 10 乎1z fungus fist 14-snake G1,6

Claims (1)

[Scope of Claims] 1. A data transfer means for generating word-by-word data and a word address indicating a transfer position of the data, a storage section accessed in word-by-word units, and a data transfer means for transferring data to the data transfer means. a first instruction means for instructing a reading position from the storage section by the number of bits from a word boundary of the storage section; a first data shift means for shifting according to read position information from the first instruction means; a read means for sending data output from the first data shift means to the data transfer means; a second instruction means for instructing the write position of the data in the storage section by the number of bits from a word boundary of the storage section; and a second instruction means provided in a data transfer path from the transfer means to the storage section, a second data shifting means for shifting the data according to the write position information by the second instruction means; a writing means for writing the data output from the second data shifting means into the storage section;
A control device comprising a control signal generating means for controlling these, an odd address memory section that stores data at odd word addresses that can be accessed independently and simultaneously in the storage section, and an even address memory section that stores data at even word addresses. a memory section, and providing read data from the odd address memory section and read data from the even address memory section to the read means, to the first data shift means;
read data generation means for generating data to be sent to the data transfer means from the data output from the first data shift means; and read data generation means for generating data to be sent to the data transfer means from the data output from the first data shift means; and the odd address memory unit from the data output from the second data shift means to the write means. write data generation means for generating write data to the even address memory section and write data to the even address memory section; access address generation means for generating an access address for a memory section is provided, and data that exceeds a word boundary is simultaneously read out from the other memory section by a shift, and data that exceeds a word boundary is read out simultaneously from another memory section by a shift. An information processing device characterized in that writing is performed in the other memory section. 2. The information processing apparatus according to claim 1, wherein the first and second data shifting means each include a data rotator having a rotation bit width corresponding to two words. 3. In claim 1, the writing means includes read modify write means for generating write data by inputting the data output from the data shifting means and the data read from the storage section. An information processing device comprising: