JPS6043742A - Reading circuit of variable length data - Google Patents

Abstract

PURPOSE:To attain read-out of variable length data starting at an optional address and to match digits through a simple constitution. CONSTITUTION:The data head address A corresponding to the data to be read out and the number of digits of data information D showing the number of digits of said subject data are fed to a reading circuit of variable length data. A memory 10 has the output data width of 64 bits (16 digits) together with left and right memories 11 and 12 of 16X32 bits (8 digits) respectively. An independent read access is possible for the memories 11 and 12 of the memory 10 by addresses AL and AR produced by a memory address generating circuit 20 and based on the upper 5 bits of the address A. The data of 64 bits read out of the memory 10 is supplied to a data selection/positioning circuit 30 then outputted after putting close to the right the data having a designated number of digits starting at the data on a section area corresponding to the address A for matching digits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a variable length data reading circuit suitable for processing data of an arbitrary data length (number of data digits) starting from an arbitrary address.

[Technical background of the invention and its problems]

Generally, when processing this type of variable length data, it is necessary to read the data from the memory and also perform digit alignment depending on the address (data start address) and the number of bytes (data length) specified from the outside. There are two methods for reading out variable-length data: one is at the microprogram level, and the other is by software.

The former method very often requires two or more memory accesses, and also requires data shifting, which has the drawback of requiring a long time for data read processing.

In addition, in the latter method, for high-speed processing, the memory configuration is such that parallel reading is possible, and data read from the memory is digit-aligned using a data selector and output. If the target data has a large maximum number of digits, there is a drawback that the hardware configuration becomes complicated. Note that the data to be read out has a large maximum number of digits, for example, a pack (P
ACK ) format decimal number.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a variable-length data readout circuit capable of high-speed reading and digit alignment of variable-length data starting from an arbitrary address while having a simple configuration. There is a particular thing.

(Summary of the Invention) In the present invention, in a data processing device in which an address space from address O to address 21-1 to which addresses are assigned in units of 1-digit n pits is applied, and the maximum number of digits of data to be read is A memory having an output data width of 2 + 1 digits, wherein the left and right memories are type 1 and type 2, respectively.
A memory is provided that is read accessed using seed address information. As the type 1 address information for the left memory mentioned above, 11 bits are placed in the high order i- of the data start address for the data to be read, and 7 bits are placed in the fuj- bit of the data start address, depending on the bit state. Alternatively, +1 is used. Further, as the second address information for the right memory, the high-order 1- bit of the data start address is used as is. By supplying these type 1 and type 2 address information to the left and right memories, the 2k-digit read data read from the left and right memories, respectively, is processed as is or with the left and right swapped in the data selection alignment circuit. connected]
(+1 is added. This 2-digit concatenation information is processed by the data selection and alignment circuit to the left or the left by the number of digits specified by the lower bit of the data start address and the data digit number information indicating the number of digits of the data to be read. When the digit is shifted to the right, the digit at the predetermined position 2 is output as read data.

[Embodiments of the invention]

FIG. 1 shows a schematic configuration of a variable length data reading circuit according to an embodiment of the present invention. In a data processing device including this 0J variable length data reading circuit, addresses O to 21-1, . For example, address 28-1 (=255) (ν
1) It is assumed that an address space (128-byte memory area) of 0016 to FF+6 in hexadecimal notation is applied. Also, the maximum number of data digits (data length) of the data to be read is double digits (2 + 2 bits), for example, 25 digits (25
bit). That is, in this example, 1
Memory data of any number of digits (4 bits) to 8 digits (32 bits) can be handled. Thus, the variable length data reading circuit shown in FIG. 1 is provided with a data start address A for the data to be read and data digit number information indicating the number of digits of the data to be read as control data. Since the memory address space is 0016 to FF16 (hexadecimal representation) as described above, the data start address A is composed of 8 pits from the 0th bit ao (MSB) to the 7th bit a7 (LSB). In addition, regarding the data digit number information, since the maximum number of digits of the data to be read is 25 (-8), the 0th pit do (MSB) to the 3rd pit) d3(L
It consists of 4 bits (SB).

&! In Figure 1, the memory designated by the symbol JO is 64
It has an output data width (data width twice the longest number of digits of the data to be read) of bits (2 + 1 - 23 + 1 = 16 bits). This memory 10 is 16x32 bits (8 digits)
It consists of a left memory 11 and a right memory 12. In this embodiment, as shown in FIG. 2, a 64-bit area corresponding to each address in the memory 10 is divided into 4 bits (1 digit).
It is divided into units, and each divided area is made to correspond to each address (00ra to FF1e) in the address space described above. That is, address X5 in the address space
16*address x11g+...address x716(x
016 to F+6), bit θ to bit 3 of left memory 1. Bits 4 to 7, . . . correspond to bits 28 to 3, and address X516*address*916.・Address×F! 6 to bit θ to bit 3 and bit 4 to bit 6 of right memory 12.
Bit 7,... Bit 2 8 ~ Pi) 31
It corresponds to Address XX16 in the above address space is left memory 11. Which side of the partitioned area of the right memory 12 corresponds to is determined by the upper 1 bit of the lower 4 bits of the I77 address xx16, that is, the corresponding address xx16.
CL) Indicated by the logical value of the 5th bit from the upper (left) bit data. Furthermore, which address in the memory 10 (left memory 1, right memory 12) this partitioned area belongs to is indicated by the upper 4 bits of address xx16 in the address space. In this embodiment, the left memory 11 and right memory 12 constituting the memory 10f are at address A
L*AR is a read access town. Address AL I AR is left memory 11, right memory 12
The number of words in is 16 (2i × 1 /zk+1 = 2i
−1=28−3−1=24), so 1.4
Consists of bits. Address AL * AR is
Upper 5 of the data start address A (i-ni 28-3
=5) Based on the bit, the memory address generation circuit 2o
Nyoshi is generated.

FIG. 3 shows a specific configuration of the memory address generation circuit 2o. The adder indicated by the reference numeral 21 in the same figure is a 4-bit addition unit that adds 1 to the upper 4 bits (ao-as) of the data start address A. How to output the adder 21 (4 bits) is input to one input terminal of the data selector 22.

The other input terminal of the data selector 22 is supplied with the upper four bits (aO to a3) of the data start address A. In addition, at the selection signal end of the data selector 22, bit data of the 5th bit from the upper (left) side of the data start address A,
That is, the fourth pit) a4 is supplied. Therefore, the data selector 22 selects the data start address A when a4="o".
Select the upper 4 bits (ao-IL3) of a4=”l
”, the output of adder 2, that is, the data start address A
Select 4-bit data obtained by adding 1 to the upper 4 bits (ao-as) of . The selected output of the data selector 22 is supplied to the address input terminal of the left memory 11 as the address AL ('i4'r type 1 address information). Also,
The upper 4 bits (a(1-as)) of the data start address A are supplied as is to the address input terminal of the right memory 12 by the memory address generation circuit 20 as the address Aa (second type address information).

Here, the selected output of the data selector 22 is set to the address AL.
The upper 4 bits of the data start address A (ao-a
The reason why s) is set as address AR will be explained. In this embodiment, when reading variable-length data, data (32-bit word data) in eight segmented areas at addresses in the left memory 11 or right memory 12 to which the segmented area in the memory 10 corresponding to the data start address A belongs is read. and the following 8
Data of 1 segmented area (32 bits, 64 bits of word data) (16 digits) is read out from the memory 10.

The maximum number of digits of the data to be read in this embodiment is 8 digits (32 bits) as described above. therefore,
The data to be read from the memory 10 always includes data that is truly desired to be read. When the left memory 11 includes the partitioned area in the memory 10 corresponding to the data start address A, the 64-bit (16 digit) data to be read from the memory 10 is (as is clear from FIG. 2) ) The left memory 11 indicated by the upper 4 bits (aQ%a3) of the data start address A. This is the concatenation information of each word data (32 bits) at the address position of the right memory 12. ? For cfL, if the partitioned area in the memory 10 corresponding to the data start address A is included in the right memory 11, the memory 1
The 64-bit (16-digit) data to be read from 0 is the upper 4 bits of the data start address A) (ao = aa
The word data (32 bits) at the address location in the right memory 11 indicated by ') and the next address location in the left memory 11 (i.e., the address location indicated by the value obtained by adding 1 to the upper 4 bits of the data start address A). This is concatenated information of word data (32 bits). By the way, the partitioned area corresponding to the data start address A is either left memory 1 or right memory 1.
As is clear from the above explanation, which side of 2 is present is indicated by the logical value of the upper (left) 5th bit data of the data start address A (i.e., the 4th bit) a4. . Therefore, in this embodiment, when a4="0", the upper 4 bits of the data start address A (a(1 to a3
), and when a4="1", a data selector 22 is provided that selects the upper 4 bits of the data start address A (4-bit data obtained by adding 1 to a(1-aa)), and the selection of the data selector 22 The output is the address AL for the left memory 1. Also, as the address AB for the right memory 11, the upper 4 bits (ao-as) of the data start address A are used as is.Then, the addresses AL and AR are By supplying it to the address input terminal of memory 11# right memory 12 and performing memory read access, 64 bits (16 digits) including 2 data (maximum 32 bits) that have been truly read out can be read in one access. Data is read out in the form of 32 bits x 2.

64 bits (32 bits x 2) read from memory 10
) is supplied to the data selection and alignment circuit 30. The data selection alignment circuit 30 receives the 64-bit data read from the memory 10, aligns the digits, and outputs the specified number of digits of data starting from the data in the segmented area corresponding to the data start address A, right-justified. It is something.

FIG. 4 shows a specific configuration of the data selection and alignment circuit 30. In the figure, the data selectors indicated by reference numerals 31 and 32 select the 64-bit data read out from the memory 10 in the form of 32 bits x 2 from the left to the readout output (32 bits) of the left memory 11 and the readout output (32 bits) of the right memory 12. Readout output (32
You can select whether to arrange the bits in the order of bits or vice versa. The 64-bit data whose position is determined by the selection operation of the data selectors 31 and 32 is supplied to the shifter 33. The lid 33 is, for example, a thick type that can be shifted to the left, and the input data (64 bits) can be shifted to the designated shift digit. The upper 32 bits of the result are output (as the data read result). shifter 3
The number of shift digits of 3 is indicated by the lower 3 bits el-e3 of the output E of the 4-bit adder 34.

The adder 34 inputs the lower 3 bits a5 of the data start address A.
It is used to calculate the sum of ~a7 and data digit difference information D (do~da). Output E of adder 34 (e6- e
3) The lower 3 bits el-83 of the memo IJJO
This indicates in which partitioned area of the left memory 1 or right memory 12 the next digit of the data that is truly desired to be read is located. Similarly, the most significant bit eO of the output E (e6 to es) of the adder 34 indicates that the next digit of the data to be truly read from the memory 10 is located in the memory (left memory 11 or right memory 12) where the first digit of the data is located. ) is located in the same memory. As is clear, eo2"0" indicates that the next digit of the requested data is located in the same memory as the first digit of the desired data. On the other hand, eQ-"1" indicates that the next digit of the requestable data is located in a memory different from the memory in which the first digit of the data is located.

The lower three bits e+ to e9 of the output E of the adder 34 are used as information 7 to specify the number of digits to be shifted by the shifter 33.
3. Further, the most significant bit eo of the output E of the adder 34 is supplied to one input terminal of an exclusive OR circuit (hereinafter referred to as EX-OR) 35. Bar 0R35
The other input terminal of is the upper (left) data start address A.
The fifth bit of bit data, ie, the fourth bit a4, is supplied. The output S of the EX-OR 35 is supplied to the far selection signal ends of the data selectors 31 and 32. ■-The output S of OR35 is when a4:eo, that is, a4::
9o == “l” or a4”e6”0”
0".Similarly, the output S is a4 to e (when 1, that is, a4="1", eo2"0" or a42"0"re
When O2 is "1", it becomes 1".Here, a4:eo2"0
case 1 if a4-0゛', co=“1”, case 2 if a42 “1”, case 3 if eo-“0”, a42 “1°+eO2”1 Case 4
Then, the data position in the memory 10 corresponding to case case 4 (the storage position in the memory 10 of the maximum 8-digit data to be obtained) is shown in FIGS. 5(a) and (b).
This is shown in Figures 8(,) and (b). In case 1, as shown in Fig. 5(a) and (b), the data start address A is ×O summer 6 to ×616, and the data end address is
016 to X 616 (X is o!6 to F16). In addition, in case 2, as shown in FIGS. 6(a) and (b), the data start address A is ×O16 to ×716.
This is a case where the data final address is x716 to xElg. In addition, in case 3, as shown in FIG. 7(,) and (b), the data start address A is
This is a case where the data final address is x816 to xE16.

Furthermore, in case 4, as shown in FIGS. 8(a) and 8(b), the data start address A is x816~X1''16 and the data end address is XFra aX1ts~x61.
This is the case of 6.

Data selectors 31 and 32 are EX-OR, 95 output S
When is logical "0", that is, in case 1 or case 4, a data selection operation is performed such that the arrangement of 64-bit data read from memory 10 is rearranged left and right in units of 32 bits.

That is, the data selectors 31 and 32 select the 64-bit data read from the memory 10 from s2"o"K1 to 6. □, 2゜, □1. ka (3□ ・1ξ.

bits) and the read output (32 bits) of the left memory 11 and output to the shifter 33. On the other hand, W-OR,9
If the output S of 5 is logic ``1'', that is, case 2 or case 3, the data selectors 31 and 32 select the memory lO
A data selection operation is performed so that the 64-bit data read from the memory is output as is. That is, data selector 3
1.32 converts the 64-bit data read from the memory IJZO in the order of the readout output (32 bits) from the left memory 1 and the readout output (32 bits) from the right memory 12 from the left to the S2. In response to "1", it is output as is to the shifter 33.

In this way, in this embodiment, the output S of EX-OR35
The left memory 1 is output to the shifter 33 according to the logical value of
1. The left and right positions of each read output (32 bits) from right memory 12 are determined. This is due to the following reason. In this example, 64
A system is adopted in which data that can be requested by left-shifting bit read data is present in the upper 32 pits in a right-aligned form. Therefore, as mentioned above, the shifter 33 that can be shifted to the left is used, and the
The data is rearranged to the left or right according to the value of S so that the next digit of the data to be inserted in the 4-bit (16-digit) input data is located on the lower 32-bit (8-digit) side of the input data.

Now, as a specific example of case 1, data start address A is
116, and the data digit number information is 616, the data position in the memory 10 of the requestable data is f! Figure 9 (
7. The output data to the lid 33 is as shown in FIG. 9(b). in this case,
The output E (eo"-e3) of the adder 34 is 0111", and 7 can be specified as the number of shift digits of the shifter 33. As a result, the shifter 33 shifts the 64-bit data shown in FIG. 9(b) seven digits (28 bits) to the left, and outputs the upper eight digits (32 bits) as read data. As a result, the desired data can be obtained correctly right-justified.

Furthermore, as a specific example of case 2, if we consider the case where the data start address A is X616 and the data digit number information is 8160, the data position in the memory lo of the data that can be requested is shown in
, ), the output data to the shifter 33 is as shown in FIG. 10(b). In this case, the output E (e6 to e3) of the adder 34 is "1110", and 6 is specified as the number of shift digits of the shifter 33.

In this case, the shifter 33 is 6 shown in FIG. 10(b).
Shift the 4-bit data to the left by 6 digits (24 bits),
The upper eight digits (32 bits) are output as read data.

As a concrete example of case 3, data start address A
If we consider the case where is ×816 and the data digit number information is 416, the data position in the memo IJJo of the data that can be requested is the same as shown in FIG. 11(a), and the output data to the shifter 33 is 'li'l1 As shown in Figure (b). In this case, the output E (eo%@3) of the adder 34 is "1100", and the number of shift digits of the shifter 33 is 4.
4 effects are added. The shifter 33 is shown in Fig. 11 (b).
) Shift the 64-bit data shown in 4 digits to the left,
The upper 8 digits (32 bits) are output as all read data.

Further, as a specific case example, if we consider the case where the data start address A is ×CI6 and the data digit number information is 816, the data position in the memory Io of the data that can be requested is as shown in Figure 12 (,). The force and output data to the shifter 33 are as shown in FIG. 12(b). in this case,
The output E (eg-es) of the adder 34 becomes "1100", and 4 is designated as the shift digit of the '/7 data 33.

This causes the shifter 33 to move to 64 as shown in FIG. 12(b).
Shift the bit data 4 digits to the left, and then shift the upper 8 digits (3
2 pinto) is output as read data.

In the above embodiment, data alignment is performed using the shifter 33 that can be shifted to the left, but it is also possible to use a shifter that can be shifted to the left or right. FIG. 13 shows the configuration of a data selection and alignment circuit 30 using a lid 4I that can be shifted left and right. Note that the same parts as in FIG. 4 are given the same reference numerals. In the example of FIG. 13, the left memory 11° and the right memory 12 by the data selectors 31 and 32 are
The left and right positions of each read data (32 bits) are determined according to the fourth bit a4 (level inverted output by the inverter 42) of the data head address. In this case, when a42"1", left and right swapping is performed. The lower 3 bits of the output E of the adder 34) e1~
e3 is fixed by the subtractor 43 as 1a 816 ("100
0"). The lower 3 of the output E' of the subtracter 43
Bits cl'-83' are supplied to one input terminal of data selector 44. The other input terminal of the data selector 44 is supplied with the lower three bits eI-83 of the output E of the adder 34. The most significant bit co of the output E of the adder 34 is supplied to the selection signal end of the data selector 44.

Therefore, when the data selector 44 is eQ-0'', e1'
~e3' is selectively outputted to shifter 4 as (right) shift digit number designation information. Similarly, the data selector 44 is
1'', 01 to 03 are selectively outputted to the chic 41 as (left) shift digit number designation information.The shifter 41 is supplied with the above e6 as shift direction designation information.

The shifter 41 shifts to the right when eQ2 is "0", eo;"■
", a left shift is performed. The upper 32 bits (8 digits) of the left or right shift result of shifter 4 become read data.

In the above embodiment, the upper 8 digits (32 bits) of the shift result are output as all read data, but the lower 8 digits (32 bits) of the shift result are output as read data.
-It is also possible to appear in the evening. In this case,
You will need at least a chic who can shift to the right. In this case, each successive data (32 pins) from the left memo Vl and the right memo υJ2 are supplied to the left.

The right position is left only in case 1 mentioned above.

It is preferable to perform right swapping. Furthermore, the right shift digits are the lower three bits e of the output E' of the subtracter 43 shown in FIG.
It can be specified by l' to e3'.

Further, in the above embodiment, a case has been described in which data of a specified number of digits is right-justified and output, but the present invention can also be applied to those requiring left-justified data. Further, in the above embodiment, addresses 0016 to FFts (O address to 25
Although we have explained the case where the address space of Address 5) is applied to a data processing device where the maximum number of digits of the data to be read is 25 digits (the maximum number of bits is 4 x 23 bits), the following data processing is generally applicable. Can be applied to equipment. That is, the present invention applies an address space from address 0 to address 2i-1 in which addresses are assigned in units of 1 digit n pits, and the maximum number of digits of the data to be read is 2 digits (the maximum number of bits is n x 2). It can be applied to data processing devices that are (bits). In this case, the memory (corresponding to memory 10, left memory (left memory 1) of 2 digits (n x 2 bit width)) and the right memory (corresponding to right memory 12) carinal 2
+1 digit (+1 bit width for n x 2) memory, that is, the maximum number of digits of the data to be read (therefore, the read data @)
Uses double-width memory. Also, as an address for the left memory (first type address information), 11 pits are placed in the upper i- of the data start address or 11 bits are placed in the upper i- of the data start address.
Use the bit with +1. In this case, which one to use depends on the upper part of the data start address (from the left).
It is determined by the state of the i-th bit (i-th bit 11). Further, as the address for the right memory (second type address information), the upper i- bits of the data start address are used as they are. As is clear, in the above embodiment, n=4°, i=8, and n=3.

〔Effect of the invention〕

As described in detail above, according to the present invention, data of 2+1 digits including data of a specified number of digits starting from a specified address can be read with one memory read access. Further, according to the present invention, data based on the read data is left- or right-justified 2-digit data e'&alfj#;J"Tj'9o co!, K, a
(7) g q ′ l” allows high-speed reading of variable length data because the memory RET 9 only needs to be accessed once.

Furthermore, since data position (digit) alignment can be performed by shift operation, the hardware configuration can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a data readout circuit according to an embodiment of the present invention, and FIG. 2 shows each area obtained by dividing the left memory and right memory areas shown in FIG. Correspondence relationship f between the segmented area and each address in the applied address space: An explanatory diagram, FIG. 3 is a circuit diagram showing the specific configuration of the memory address generation circuit shown in FIG. 1, and FIG. 4 is shown in FIG. 1. 5 to 8 are circuit diagrams showing the specific configuration of the data selection and alignment circuit. FIGS. 12 is a diagram illustrating specific variable length data corresponding to FIGS. 5 to 8 and input data to the shifter 33 including the data, and FIG. 13 is a diagram illustrating the data selection position shown in FIG. 1. It is a figure which shows the modification of a matching circuit. 10 memory, 1... left memory, 12... right memory, 20... memory address generation circuit, 21°34...
Adder, 22, 31, 32.44... data selector,
30...Data selection alignment circuit, 33.41...
Shifter, 43...Subtractor. Applicant's representative Patent attorney Takehiko Suzue Figure 3 AL AR Figure 4 Takes Figure 5 (a) (b) (a) (b) 11 1111 11 No. 9 (a) No. 101 No. 12 (b) ) Flash (b) Figure (b) Figure (b) 1 cho 1% cho] ・11.・

Claims (1)

[Claims] In a data processing device, an address space from address 0 to address 2i-1 to which addresses are assigned in units of n bits of one digit is applied, and the maximum number of digits of the target data to be escaped is 2+1. A memory having a two-digit output data width, to which the first type address information is supplied, and a left memory having a two-digit output data width, and a left memory having a two-digit output data width, and a left memory having a two-digit output data width; From the right memory, the left and right sides can be read simultaneously with different address information, and 11 bits are added to the upper i- of the data start address for the data to be read, and the upper i of the data start address is - means to add L-6 to the bit state of the bit-th bit, as it is, or increment it by +1, and output it to the left memory as the first type address information; A means for outputting the seed address information to the right memory, and a means for outputting the 2-digit information read from the left and right memories respectively, either as is, or with +1 left and right swapped and concatenated. Data selection positioning that shifts left or right by the number of digits specified by the bit at the lower end of the data start address and the data digit number information indicating the number of digits of the data to be read, and outputs the digit at the predetermined position 2 as read data. A variable length data reading circuit comprising: