KR920001023Y1 - Multi-screen entry adress control circuit - Google Patents

Abstract

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Description

Multi Screen Write Address Control Circuit

1 is a circuit diagram according to the present invention.

2 is an operational waveform diagram of each part of the drafting.

3 is an exemplary view showing a screen area display according to the present invention.

* Explanation of symbols for the main parts of the drawings

10: load control unit 20: refresh section setting signal generator

30: load signal selection unit 40: multi-screen write address generation unit

50: address comparator 60: NAND gate

The present invention relates to a memory address control circuit used for multi-screen display in a video system such as a digital video tape recorder or a digital color television. In particular, the write address of the horizontal axis of the memory can be controlled according to the user's multi-screen selection. The present invention relates to a multi-screen write address control circuit capable of generating a multi-screen.

As part of the trend of high performance in video systems such as color television and video tape recorders, new technology has recently been introduced on the product to display MiltiM screens on one monitor in Europe and the United States. In order to configure a multi-screen, the screen is reduced by using a memory. That is, the original screen is scoured, written to memory, read out, and displayed on the monitor.

Therefore, when writing to the memory, the video signals of all the horizontal lines are not written to the memory, but only 1/2 horizontal line is displayed in 4 screens, 1/3 horizontal line is filled in 9 screens, and l / 4 horizontal line is written in 16 screens. The memory must be refreshed for the rest of the line period. In this case, the vertical axis of the screen is reduced by using a horizontal synchronization signal of the video signal, and the horizontal axis is reduced by using a row address strobe signal. It is well known that the row address strobe signal is a strobe signal for specifying a column address of a memory. However, in the past, when displaying multiple screens such as 4 screens, 9 screens, and 16 screens on one monitor, the volume and cost of the product are increased due to the complicated circuit configuration such as using various counters for address control for writing and refreshing memory. There has been a problem of rising.

Accordingly, an object of the present invention relates to a multi-screen write address control circuit capable of generating a desired multi-screen by controlling a multi-screen write address for multi-screen write and refresh as a simple circuit using the same counter. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram according to the present invention, and includes an inverter 13 for inverting a horizontal synchronous signal input through the horizontal synchronous signal input terminal 1 and a NAND gate 11 and 12 to enable a vertical memory write enable signal. Decode the vertical memory write enable signal and the vertical memory write enable delay signal input through the input terminal 2 and the inverted horizontal synchronization signal. A load controller 10 configured to generate a write load signal and a refresh load signal, and first and second flip-flops 21 and 22 to input vertically through the vertical synchronous signal input terminal 6. The refresh period setting signal generation unit 20 and the end gates 31 and 32 which are initialized by the synchronization signal and generate a refresh period setting signal by counting the refresh load signal of the load control unit 10. And an upper four-bit address (A4) consisting of an input terminal (75-78) in accordance with the write load signal and the refresh load signal. -A7) and a load signal selector 30 for selectively outputting one of the refresh period setting signals as a load signal, and first and second counters 4l and 42, wherein the horizontal synchronization signal, the write load signal, and the refresh signal are refreshed. According to the load signal, the low-order 4-bit address A0-A3 input through the first to fourth address input terminals 71-74 and the load signal of the load signal selector 30 are loaded and the row address strobe signal is loaded. A multi-screen writer for generating a multi-screen write address for writing or refreshing by counting a row address strobe signal input through the input terminal 4 and stopping counting by a predetermined count disable signal input. The address generator 40 compares the output multi-screen write address of the multi-screen write address generator 40 with a reference address input through the reference address input terminal 5, and generates a disable signal when they match. A NAND for generating a counting disable signal by comparing an address comparator 50 with the disable signal of the address comparator 50 and the vertical memory write enable delay signal, and applying the count disable signal to the multi-screen write address generator 40. It consists of a gate 60.

In FIG. 1, the 8-bit address A0-A7 of the first to eighth address input terminals 71-78 and the reference address of the reference address input terminal 5 are the same address bus of the multi-screen control means in the video system. It is an 8-bit address input via. In addition, the first and second counters 41 and 42 may use the 74LS161 of the US MOTOROLA Co., Ltd., a general purpose 4-bit binary counter, and the address comparator 50 compares the size of two input data with a general data size comparator. Use

FIG. 2 (a) is an operation waveform diagram of each part of FIG. 1, (a) is a signal input through the horizontal synchronous signal input terminal 1, and is a horizontal synchronous signal waveform of an image signal. (C) is a signal input through the vertical memory enable signal input terminal (2), which is inverted by the inverter (13). Is a waveform of a vertical memory enable signal for writing only the video signal into the memory, and (d) is a signal input through the vertical memory enable delay signal input terminal 3, and vertically delays the vertical memory enable signal. (E) is a waveform of a write load signal as an output signal of the NAND gate 11, (f) is a waveform of a refresh load signal as an output signal of the NAND gate 12, ( g) is the reference address input terminal (5) shows a reference address input through (5), (h) shows a multi-screen write address as the output of the multi-screen write address generator 40, and (i) shows a disc generated by the address comparator 50. The waveform of the enable signal is shown, and (h) is the waveform of the counting disable signal as the output signal of the NAND gate 60.

The horizontal synchronizing signal, the vertical memory write enable signal, and the vertical memory write enable delay signal are generated and input by a clock generation circuit of an image system.

FIG. 2B is a waveform diagram showing an enlarged view of the operation waveform diagram of FIG. 2A. FIG. 2B is an enlarged view of the horizontal synchronization signal input through the horizontal synchronization signal input terminal 1. FIG. (B) is an enlarged waveform of the vertical memory enable signal input through the vertical memory enable signal input terminal 2, and (c) is input through the vertical memory enable delay signal input terminal 3 rate. (D) is a signal input through the row address strobe signal input terminal 4, and is a waveform of the row address strobe signal as described above, and (e) is a reference address. The reference address input through the input terminal 5 is enlarged, and (f) is an enlarged representation of the multi-screen write address, which is the output of the multi-screen write address generator 40, and (g) is a NAND gay. It is a close-up of the output pyeongpa counting disable signal (60).

3 is an exemplary view of a screen generated according to the present invention, (a) is an exemplary diagram in which a source displays an image signal by dividing one screen into four screens, and (b) shows one screen. An example of dividing into nine screens so as to display image signals of different sources, and (c) illustrates an example of dividing one screen into 16 screens so that the sources display different image signals.

An operation example of FIG. 1 according to the present invention will now be described in detail with reference to FIGS. 2 and 3.

First, there are various types of multi-screens in which one screen is divided into a plurality of screens to display different image signals, respectively, such as four screens, nine screens, and sixteen screens as illustrated in FIGS. In order to generate the multi-screens, the original screens should be reduced to the vertical axis and the horizontal axis, respectively. The vertical axis uses the horizontal synchronizing signal of the video signal to write only 1/2 horizontal line on 4 screens, 1/3 horizontal line on 9 screens, and 1/4 horizontal line on 16 screens. Zoom out. For example, in the case of 9 screens, the 3n + 1th horizontal line (where n is a natural number) of the entire horizontal lines, that is, n. First, fourth. Seventh, only the horizontal lines of ... are written into the memory, and the remaining horizontal lines are not written. In addition, the horizontal axis typically uses a row address strobe signal for column addressing of the memory, using one horizontal line for 1/2 pixel for 4 screens, 1/3 pixel for 9 screens, and 1/4 pixel for 16 screens. Output only by writing to memory. For example, in the case of 9 screens, the 3n + 1th pixel (where n is a natural number) among the pixels of one horizontal line, that is, the first, fourth, and seventh times. Write only the pixels in the memory, and do not write the remaining pixels.

The above is a known fact, and since writing to the memory for reduction of each multi-screen is performed by the same process except that the reduction ratio is different, the case of 9 screens will be described here as an example. For convenience of explanation, a case in which the second, fifth, and eighth screens are sequentially written from the second screen among the nine screens of FIG. 3B will be described.

First of all, the load terminal (2) of the second counter 42 is used as a write start signal, as shown in (a) of FIG. ). The horizontal synchronizing signal, which is the write start signal, is inverted by the inverter 13 and input to one terminal of the NAND gates 11 and 12, respectively. In addition, the vertical memory write-in shown in (c) and (d) of FIG. 2 (a) input through the vertical memory write enable signal input terminal 2 and the vertical memory write enable delay signal input terminal 3, respectively. The enable signal and the vertical memory write enable delay signal are input to the other terminals of the NAND gates 11 and 12, respectively.

Accordingly, the NAND gate 11 decodes the signal inputted at both terminals to generate a write load signal as shown in (e) of FIG. 2 (a), so that the load terminal (1) of the first counter 41 ) And one terminal of the oragate (33, 35) at the same time. The NAND gate 12 decodes the signal input to both terminals, generates a refresh load signal as shown in (f) of FIG. 2A, and the clock terminal CK of the first flip-flop 21. Clear terminal of the first counter (41) ) And one terminal of the end gates 31 and 32 and one terminal of the oragate 34 and 36 at the same time.

The write load signal is " low " active as a signal for loading the first and second counters 41 and 42 with an address starting to write a pixel of one horizontal line of the image signal into a memory. The refresh load signal is used to load the first and second counters 4l and 42 which start to refresh the memory during the interpolation of a horizontal line which does not write an image signal to the memory when activated as "low". Use as a signal.

First, when the write load signal as shown in (e) of FIG. 2 (a) is activated to "low" and the refresh load signal as shown in (F) of FIG. 2 (a) is in a "high" state The writing section 1 will be described as follows.

The first counter 41 inputs the addresses A0-A3 of the lower four bits through the first-fourth address input terminals 71-74 by the "low" of the write load signal, so that the input terminals A, B, After loading through C and D, the row address strobe signal input through the row address strobe signal input terminal 4 is counted and the counted value is output to the output terminals QA, QB, QC, and QD. In addition, the AND gate 31 inputs “high” of the output refresh load signal of the NAND gate 12 and the address A4 through the fifth address input terminal 75, so that the address A4 may be input to the second gate. It outputs to the input terminal A of the counter 42.

In addition, the AND gate 32 inputs the address A5 through the refresh load signal “high” and the sixth address input terminal 75, so that the address A5 is input to the input terminal of the second counter 43. Output to B). In addition, the OR gate 33 outputs the address A6 to one terminal of the AND gate 37 by ORing the address A6 through the seventh address input terminal 77 with the write load signal " low ". . Since the ora gate 34 inputs the refresh load signal “high” to one terminal, the oragate 34 outputs a “high” signal. Accordingly, the AND gate 37 transmits the address A6 to the second counter 42. Output to the input terminal (C) of). In addition, the OR gate 35 logically combines the address A7 through the eighth address input terminal 78 with the write load signal " low " to the other input terminal, and the address A7 as one terminal of the AND gate 38. Outputs Since the ora gate 36 inputs the refresh load signal “high” to one terminal, the ora gate 36 outputs a “high” signal to the other input terminal of the AND gate 38. Therefore, the AND gate 38 inputs the address a7 to the input terminal D of the second counter 42.

Therefore, the first counter 4l inputs the first-fourth address AO-A3 to the input terminal AD to load the write load signal “low”, and the second counter 42 receives the first counter. The fifth eighth address A4-A7 is inputted to the input terminal AD to be loaded by the write start signal, that is, the horizontal synchronous signal " low ".

In this case, since the multi-screen write address of the nine screens as shown in FIG. 3 (b) is controlled, the addresses A0-A7 loaded in the first and second counters 41 and 42 correspond to the horizontal lines of one screen. Only one third, that is, a start address value for writing only one horizontal line increment by three horizontal lines is used.

In addition, since the multi-screen write address of the second, fifth, and eighth screens in the center of the nine screens of FIG. 3 (b) is controlled, the second, fifth, and eighth screens are horizontally stored in the memory. Assuming that the address value to start writing is 3E (= 62) in hexadecimal and the address value to finish writing is 7C (= 124), the address loaded in the first and second counters 41 and 42 ( A0-A7) becomes 3E (= 62) as shown in (h) of FIG. At this time, the row address strobe signal through the row address strobe signal input terminal 4 is also clocked as shown in (d) of FIG. 2 (b) to write the horizontal line I / 3 only by a predetermined controller of the imaging system. The clock terminal CK of the first counter 41 and the clock terminal CK of the second counter 42 are input. Accordingly, the first counter 41 and the second counter 42 are the address values 3E which are the data loaded as described above from the time when the write load signal of (e) of FIG. 2 (a) becomes "high". Start counting. In this case, the first and second counters 41 and 42 may receive a multi-screen write address that is increased as shown in (h) of FIG. 2 (a) and (f) of FIG. It generates and outputs to the memory through the output terminal (8) and to the address comparator (50).

The address comparator 50 compares the multi-screen write address with a reference address value 7C as shown in (g) of FIG. 2A input through the reference address input terminal 5 to write the multi-screen write address. When the address reaches (7C) as shown in (f) of FIG. 2 (b), the NAND gate 60 is generated as a disable signal by generating a logic signal of “high” as shown in (i) of FIG. Output to one terminal of. At this time, since the NAND gate 60 is inputting the vertical memory write enable signal " high " as shown in (d) of FIG. The same "low" counting disable signal is simultaneously output to the enable terminals ENP of the first and second counters 4l and 42. Accordingly, the first and second counters 41 and 42 stop counting and no longer increase the write address, thereby preventing invasion of the memory area, that is, 3, 6, and 9 screen areas of FIG. 3 (b) after 7C. can do. Although the address comparator 50 compares the reference address and the multi-screen write address by 8 bits, respectively, the least significant bit need not be compared.

Therefore, writing of the video signal in one horizontal line to the second, fifth and eighth screen areas as shown in FIG. 3 (b) of the memory is completed.

Secondly, after one horizontal line is inserted into the memory by the multi-screen write address as described above, and during the next two horizontal line periods, as shown above, an address for refreshing the memory without writing is generated. The refresh section II will be described.

In general, it is time-consuming and difficult to refresh all 256 horizontal lines of memory during two periods of horizontal sync signal, so refresh only 64 horizontal lines during the two periods of horizontal sync signal, and write again after writing the next one horizontal line. You have to repeat the process of refreshing 64 lines four times. Therefore, each load value for generating address to refresh memory 4 times is øø → 4ø (= 64) → 8ø (= 128) → Cø (= 192) → øø → 4ø → 8ø, . It should be repeated in this way, and the address for refresh should be increased from the load value of the refresh sections ll, IV, and VI as shown in FIG.

Meanwhile, the NAND gate 12 generates a "low" refresh load signal based on a vertical memory write enable delay signal input to both terminals and an inverted horizontal synchronization signal as shown in FIG. Start address generation for. The output refresh load signal of the NAND gate 12 is a clear terminal of the first counter 41. ) And thus the first counter 41 is cleared.

The vertical synchronization signal “low” input for each screen through the vertical synchronization signal input terminal 6 is the clear terminal of the first and second flip-flops 21 and 22. The first and second clip flops 21 and 22 are cleared at the start of the first horizontal line of each screen. The first flip-flop 21 outputs predetermined data latched to the input terminal D at a rising edge of the refresh load signal as the refresh load signal is input to the clock terminal CK. It is output to one terminal of the oragate 34 through Q). In addition, the first flip-flop 21 has an inverted output terminal ( ) And the input terminal D are connected to each other. The second flip-flop 22 also has an inverted output terminal ( ) And the input terminal D are connected to each other. And an inverting output terminal of the first flip-flop 21 ) Is connected to the clock terminal CK of the second flip-flop 22, and the output signal of the output terminal Q of the second flip-flop 22 is output to one terminal of the oragate 35. . Therefore, the first and second flip-flops 21 and 22 operate as normal counters, respectively, and thus outputs of (ø, ø) → (ø, 1) → (1, ø) → (1, 1), i.e. The first and second refresh period setting signals are repeatedly generated and output to one terminal of the oragate 36 and 34, respectively. That is, the output of the first flip-flop 21 is output to one terminal of the oragate 36 as a second refresh section setting signal, and the output of the second flip-flop 22 is a first refresh section setting signal. It is output to one terminal of the oragate 36. This first counter 4l has a clear terminal ( Cleared by the refresh load signal " low " Since the ora gates 33 and 35 input the write load signal " high " to one terminal, they output a " high " signal to one terminal of the AND gates 37 and 38, respectively. Therefore, the AND gates 37 and 38 input the second refresh section setting signal and the first refresh section setting signal respectively input to the other terminals, respectively, to the input terminals C and D of the second counter 42. Accordingly, the load values of the refresh sections of the first and second counters 41 and 42 are repeated from øøøøøøøø → ø1øøøøøø → 1øøøøøøøø → 11øøøøøø in hexadecimal, øø → 4ø → 8ø → Cø, starting from the load value for each refresh period. By operating the refresh address to generate a refresh address, it is possible to refresh all the stored data of 256 horizontal lines of the memory in four refresh periods.

Therefore, according to the above operation, the multi-screen writing section I, the refresh section II, the multi-screen writing section III, the refresh section IV, the multi-screen writing section V in FIG. By repeating the refresh section VI, the video signal of nine screens is written one by one, thereby enabling multi-screen display.

As described above, the present invention is a simple circuit, by controlling the multi-screen write address for writing and refreshing the multi-screen, so that the user can generate the desired multi-screen, thereby reducing the volume and cost of the product.

Claims (3)

The horizontal synchronization signal input terminal 1, the vertical memory write enable signal input terminal 2, the vertical memory write enable delay signal input terminal 3, the low address straw signal input terminal 4, and the reference In the multi-screen write address control circuit having an address input terminal (5), a vertical synchronization signal input terminal (6) and a first to eighth address input terminals (71-78), the horizontal synchronous signal input terminal (1) And an inverter 13 for inverting the horizontal synchronous signal through the N s, the vertical memory write enable signal, the vertical memory write enable delay signal, and the inverted horizontal synchronous signal to generate a write load signal and a refresh load signal. It is initialized by the vertical control signal through the load control knob 10 and the vertical synchronous signal input terminal 6 and counts the refresh load signal of the load control unit 10 to set the refresh period setting signal. A load signal generated by the refresh period setting signal generation unit 20 to generate one of an address through the fifth to eighth address input terminals 75-78 and the refresh period setting signal according to the write load signal and the refresh load signal; The load signal selector 30 to selectively output the address, the address of the first to fourth address input terminals 71 to 74, and the address output from the load signal selector 30 to the write load signal and the horizontal; Load by a synchronization signal and count the row address strobe signal to generate a multi-screen write address, and a refresh period setting signal selected and output by the load signal selector 30 by the refresh load signal and the write load signal. Load and count the row address strobe signal to generate an address for refresh, at a predetermined counting disc. A multi-screen write address generator 40 for stopping counting due to a signal input, an address comparator 50 for generating a disable signal when the multi-screen write address and the reference address are compared and matched, and the address; And a logic gate 60 for generating a counting disable signal by comparing the disable signal of the comparator 50 with the vertical memory output enable delay signal to both terminals, and applying the count signal to the multi-screen write address generator 40. And a multi-screen write address control circuit. The AND gate of claim 1, wherein the AND gates respectively control outputs of a predetermined address through the fifth to sixth address input terminals 75.76 according to the first state of the refresh load signal of the load signal selector 30. 31 and 32, an oragate 33.35 for controlling the output of a predetermined address through the seventh-eighth address input terminal 77.78 in accordance with the write load signal, and the second state of the refresh load signal. An ora gate 34 for controlling the output of the second refresh section setting signal, an org 36 for controlling the output of the first refresh section setting signal according to the second state of the refresh load signal, and the ora Input a predetermined address of the gate 33 to the multi-screen write address generator 40, or input a second refresh period setting signal of the OR gate 34 to the multi-screen write address generator 40Inputs the output address of the AND gate 37 and the predetermined address of the ORG gate 35 to the multi-screen write address generator 40, or inputs the first refresh period setting signal of the OR gate 36; And an AND gate (38) for outputting to the multi-screen write address generator (40). The display device of claim 1, wherein the multi-screen write address generator 40 is configured to supply the row address strobe signal, the refresh load signal of the first state, and the write load signal to a clock terminal CK and a clear terminal, respectively. ) And Lordanza ( ) By loading a predetermined address through the first to fourth address input terminals 71-74 and then through the address comparator 50 and the output terminal 8 through the output terminals QA-QD. A first counter 41 which outputs and is cleared according to the refresh load signal of the second state to indicate a refresh period and stops counting as the counting disable signal is input to the enable terminal ENP, and the horizontal synchronization. Signal and low address strobe signal respectively ) And clock shortwave ( Input the output signal of the load signal selector 30 through the address comparator 50 and the output terminal 8 and input the counting disable signal to the enable terminal ENP. And a second counter 42 which stops counting accordingly.