JP2606474B2 - Panel display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control apparatus for controlling display of a panel display having a display timing different from that of a CRT display by an application program created for the CRT display, and more particularly to a display control apparatus divided into two screens. And a panel display control device for controlling a single drive type panel display.

[0002]

2. Description of the Related Art In recent years, along with miniaturization of various OA devices such as a personal computer and a word processor, displays used for these devices have been changed to conventional CRs.
Panel types such as liquid crystal displays and plasma displays have come to be used in place of T displays.

In order to reduce the electrode capacity in accordance with the increase in the size of the above-mentioned panel type display, as shown in FIG. 8, the panel 21 is divided into, for example, upper and lower two screens, and these two screens are respectively divided. Two-side single-drive type LC driven by shift registers 22 and 23
D-panel displays have also been developed. In this type of display, as shown in the display timing diagram of FIG. 9, panel display data of 1 to 240 lines constituting the upper divided screen according to a panel control signal composed of a frame control signal FLM and a line control signal LC. PDA and panel display data PDA of 241 to 480 lines constituting the lower split screen
Are alternately supplied line by line.

On the other hand, panel type displays and CRs
The display timing is usually different from that of the T display. Therefore, in order to drive the above-described conventional two-panel single-drive panel display with an application program created for a CRT display, the following method has conventionally been adopted.

That is, according to the initial setting program,
The content of the timing control register of the existing CRT controller is set to the same timing as the panel timing.

[0006] Access to a display memory (VRAM) managed by the CRT controller is alternately performed on upper and lower two screens. Therefore, a memory address generating circuit for that purpose is provided for two upper and lower screens.

[0007]

However, as described above, when the contents of the control register are set to match the timing of the panel display, when the display mode is changed by the application program, the contents of the CRT controller are not changed. Since the contents of the timing control register are rewritten, there is a problem that the set timing for the panel is lost and the display operation is hindered. Therefore, in this case, a calculation means such as a local CPU for converting the contents of the register set for the CRT into timing data for the panel is required, and there is a problem that the cost of parts is increased.

In the above-mentioned method, since the memory addresses of the upper and lower two screens are generated alternately, there is a problem that a special address generation circuit including two counters having different preset values is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and does not cause a large increase in parts cost, and does not hinder a two-screen panel display by timing data set for a CRT display. An object of the present invention is to provide a highly compatible panel display control device capable of performing display control and using a general-purpose memory as a frame buffer.

[0010]

Means for Solving the Problems] panel display control apparatus according to the present invention, split-screen thin to be displayed control
And clock supply means for supplying a basic clock to be a basis of the display timing guru drive type panel display, Timing set inside and a predetermined clock signal
A CRT controller operable on the basis of a clock setting value, and capable of outputting a display timing signal and display data of the panel display to the outside based on the basic clock and an externally applied wait signal; A panel data conversion circuit for converting display data output from the display data to display data for a panel,
A memory for storing at least 1/2 frame + 1 line display data for the panel output from the panel data conversion circuit, the basic clock and the CRT converter;
Based on the input of the display timing signal from the controller
The display timing in the CRT controller
The display data is one lane for the output operation of the
In order to suspend only the period during which
Output to the CRT controller
In a panel timing controller for <br/> output panel vertical switching signal synchronized with the wait signal, and controls the read / write to the memory based on said panel upper and lower switching signal from the panel data converter One lie
During which the panel display data for the panel is output
Then, the display data for one line is written to the memory, and subsequently, the CRT controller
During the period when the operation is interrupted by the
1/2 frame away from previously written display data
Reads the display data of the line that is from the memory, and the memory controller to shifting the write address in the write scan and the reverse direction by one line and for each frame,
A data control circuit for alternately selecting display data output from the panel data conversion circuit and display data output from the memory for each line in accordance with the panel up / down switching signal and outputting the data to the panel display. It is characterized by the following.

[0011]

According to the present invention, the CRT controller operates in accordance with the basic clock for the panel and repeats the wait operation in accordance with the wait signal output from the panel timing controller, thereby forcibly synchronizing with the panel timing. Will be Also, according to the present invention, a half frame +
A one-line buffer is provided. By devising the addressing of reading and writing to and from this buffer, the general-purpose memory is used efficiently to alternately select display data supplied from a CRT controller and display data read from the buffer. Thus, data can be supplied in an order that matches the two-screen split panel display.

Therefore, according to the present invention, without changing the order of the display data output from the CRT controller at all, and without changing the timing data set inside the CRT controller at all,
Display control of a two-screen split type panel display can be performed according to an application program for the T display. Therefore, it is possible to provide a panel display control device having excellent compatibility.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a panel display control device according to one embodiment of the present invention. FIG. 1 is a block diagram showing a display controller 1 according to this embodiment, a display memory (hereinafter referred to as VRAM) 2 and a flat panel display 3 connected thereto.

The display controller 1 is configured as follows. That is, one of the CRT clock signal CCK defining the display timing of the CRT display and the panel clock signal PCK defining the display timing of the panel display is selected by the clock select circuit 11, and the CRT controller 12 and It is supplied to the panel timing controller 13. When controlling the display of a CRT display (not shown), these controllers 12 and 13 control the clock signal CC for the CRT.
When operating at K and performing display control of the flat panel display 3, it operates at the panel clock signal PCK.

The CRT controller 12 has therein:
A timing control register (not shown) and an external synchronization circuit 14 are provided. For a CRT (not shown), various types of horizontal synchronization signals and the like based on timing data set in the internal timing control register are provided. Outputs a timing signal to the panel timing controller 13
, The display timing signal DTMG is supplied, and the display timing signal DTMG is weighted based on the weight signal output from the panel timing controller 13 to match the timing for the panel.
Further, the CRT controller 12 sequentially reads the display data VDA from the VRAM 2 and
It is supplied to the panel data conversion circuit 15 as DA.

On the other hand, the panel timing controller 13
Is a timing signal DT from the CRT controller 12.
Based on MG and clock signal CLK from clock select circuit 11, wait signal WT, panel upper / lower screen switching signal SW, panel control signal (line control signal) LC, and shift clock signal SCK
And these signals are respectively connected to the external synchronization circuit 1
4, supply to the memory controller 16, the flat panel display 3, and the panel data conversion circuit 15.

The panel data conversion circuit 15 includes a CRT display data CD supplied from the CRT controller 12.
A is subjected to, for example, a process such as gradation provision to convert it into display data PDA1 for a panel.

A memory controller 16 has a read / write signal R / W for giving read / write timing of a memory 17 used as a 1/2 frame buffer and a read / write address of the memory 17 based on a panel upper / lower screen switching signal SW. Is supplied to the memory 17. In this case, the memory 17 needs a capacity of at least 少 な く と も frame + 1 line, for example, 241 lines if one frame is 480 lines. In this embodiment, it is assumed that one frame has 480 lines, and the memory 17 has a capacity of exactly フ レ ー ム frame + 1 line, that is, 241 lines. The panel display data PDA1 output from the panel data conversion circuit 15 is written to the memory 17 in accordance with the read / write signal R / W, and is displayed as display data PDA2 from the memory 17 in accordance with the read / write signal R / W. It is to be read.

The data control circuit 18 alternately selects the display data PDA1 output from the panel data conversion circuit 15 and the display data PDA2 read from the memory 17 line by line and supplies the display data PDA to the flat panel display 3. I do.

Next, the operation of the display controller configured as described above will be described. First, when performing display control of a CRT display (not shown),
The clock signal CCK for CRT is selected by the clock select circuit 11. As a result, the CRT controller 12, as shown in FIG. 2, sets the horizontal synchronization time and the horizontal synchronization start time set in the internal timing control register.
A horizontal synchronizing signal HSYN for giving a display timing of a CRT display based on timing data such as end timing and blanking period start / end timing.
C and a vertical synchronization signal VSYNC. Also, V
The display data VDA read from the RAM 2 is output from the CRT controller 12 as display data CDA in accordance with the various timing signals. In the drawing, the numbers described in the display data CDA indicate line numbers, and in this example, a screen of one frame is composed of 480 lines.

On the other hand, when the display control of the flat panel display 3 is performed, the clock signal PCK is selected by the clock select circuit 11.
Not only panel timing controller 13 but also CRT
The controller 12 also operates by the panel clock signal PCK. FIG. 3 shows the display timing at this time. In this figure, panel data PDA1,
The numbers assigned to the timing diagrams of the PDA 2 and the PDA indicate the line numbers of the flat panel display 3. The flat panel display 3 has 1 to 240
The lines constitute the upper screen, and the lines 241 to 480 constitute the lower screen.

As shown in FIG. 3, first, when the display timing signal DTMG becomes active, the CRT controller 12 outputs the first line of display data CDA constituting the upper screen of the panel. This display data CDA is
The panel data conversion circuit 15 converts the display data into panel display data PDA1. At this time, since the panel upper / lower screen switching signal SW is at the “1” level, the data control circuit 18 selects the display data PDA1, and
Output to the flat panel display 3.

When the display data of the first line is supplied to the flat panel display 3, a display timing signal D
Since the TMG becomes inactive, the panel timing controller 13 outputs a wait signal WT to the CRT controller 12 in response to this. Thereby, CR
The T controller 12 stops operating and wait signal WT
The state before the occurrence of is maintained.

During this wait operation, the panel timing controller 13 switches the read / write signal to the memory 17 to read the data of the 241st line of the lower screen stored in the memory 17. At this time, since the panel upper / lower screen switching signal SW is at the “0” level, the data control circuit 18 selects the display data PDA2 read from the memory 17 and outputs it to the flat panel display 3.

When the display data of the 241st line is supplied to the flat panel display 3, the output of the wait signal WT from the panel timing controller 13 is stopped. In response to this, the CRT controller 13 outputs the display timing signal DTMG. When activated, the operation is restarted, and the display operation of the next second line is forcibly started.

Thereafter, by repeating the same procedure,
The display data PDA is supplied to the flat panel display 3 alternately from the CRT controller 12 and the memory 17.

Here, by setting the pulse interval of the wait signal WT to an appropriate value, the CRT controller 1
2 can be synchronized with the panel timing.

FIGS. 4 and 5 show the CRT controller 1.
FIG. 2 is a schematic diagram showing a flow of display data PDA supplied to a flat panel display from a memory 2 and a memory 17.

First, when the CRT controller 12 scans the upper screen of the panel, as shown in FIG.
The RT controller 12 sends out the data on the first line of the flat panel display 3 according to the scanning, and simultaneously stores the data on the first line in the memory 17.
When all the data of the first line has been scanned, the data of the 241st line already stored in the memory 17 is sent to the lower screen of the flat panel display 3. Hereinafter, similarly, when the CRT controller 12 scans up to the 240th line of data, the display operation for one frame is completed. At this point, data of 1 to 240 lines is stored in the memory 17. The reading / writing of data in the memory 17 in this case will be described later in detail.

On the other hand, when the CRT controller 12 is scanning the lower screen of the panel, first, the first line data already stored in the memory 17 is sent to the flat panel display 3 as shown in FIG. The display operation of the first line is performed. Subsequently, the data of the 241st line from the CRT controller 12 after the cancellation of the wait is supplied to the flat panel display 3, and at the same time,
The data of the 241st line is stored in the memory 17.
Next, the data of the second line is read from the memory 17, and
It is supplied to the panel display 3. When the above operation is repeated and the data of the 480th line is stored in the memory 17, the data of the 241st to 480th lines are stored in the memory 17.

Here, writing of data to the memory 17 and reading of data from the memory 17 will be described in detail with reference to FIGS. Reading / writing of data in the memory 17 is controlled by the memory controller 16.

In this case, the memory 17 has a capacity of 241 lines for 1/2 frame buffer. FIG. 6 shows the relationship between the line addresses 1 to 241 of the memory 17 and the line numbers L _{1 to} L ₄₈₀ of the data read / written to the memory 17, and FIG. 7 shows the data output from the CRT controller 12. From CDA, data control circuit 18 to flat panel display 3
Data PDA and wait signal WT supplied to
Is shown. In FIG. 6, W
Indicates that the display data PDA1 output from the panel data conversion circuit 15 is supplied to the display via the data control circuit 18 and is written from the panel data conversion circuit 15 to the memory 17; This indicates that the data PDA2 is read and provided for display via the data control circuit 18. In FIG. 7, CC indicates a period in which the display data PDA1 is used, that is, a period in which the data CDA output from the CRT controller 12 is directly used for display as the display data PDA1. Data is written to the memory 17. FM is a period during which the display data PDA2 is used, that is, the memory 1
7 shows a period in which the display data PDA2 read from the memory cell 7 is being used for display, and the wait signal WT is turned on during this period.

[0033] When the CRT controller 12 is scanned over the screen, first, data of the line number L ₁ by the display data PDA1 based on data CDA outputted from the CRT controller 12 is subjected to the display as display data PDA And the line address 1 of the memory 17
Is stored in the area. Then, after the data of the line number L ₂₄₁ to the region of the line address 2 of the memory 17 has already been stored is subjected to the display as a read and display data PDA, data line number L ₂ by the display data PDA1 , Are provided for display as display data PDA, and are stored in the same line address 2 area of the memory 17. Similarly, after the data of the line number L ₄₇₉ to the area of the line address 240 of the memory 17 has already been stored it is subjected to the display as a read and display data PDA, the data line number L ₂₄₀ by the display data PDA1 Are provided for display as display data PDA and are stored in the same line address 240 area of the memory 17. Next, the data of the line number _L480 already stored in the area of the line address 241 of the memory 17 is read and provided for display as the display data PDA. Thus, the scanning of the upper screen by the CRT controller 12 is completed.

Next, the CRT controller 12 scans the lower screen. After the data of the line number L ₁ already stored in the region of the line address 1 of the memory 17 is subjected to the display as a read and display data PDA, the data line number L ₂₄₁ by the display data PDA1 is, display data It is provided for display as a PDA and is stored in the same line address 1 area of the memory 17. Next, the data of the line number L ₂ of the area of the line address 2 of the memory 17 has already been stored is read out display data PDA
Then, the data of the line number L ₂₄₂ based on the display data PDA1 is provided for display as the display data PDA and is stored in the same line address 2 area of the memory 17. Similarly, after the data of the line number L ₂₄₀ already stored in the area of the line address 240 of the memory 17 is read and provided for display as the display data PDA, the data of the line number L ₄₈₀ based on the display data PDA 1 is displayed. Are provided for display as display data PDA and the same line address 24
0 is stored in the area. Thus, the scanning of the lower screen by the CRT controller 12 is completed. As described above, CR
One frame of scanning by the T controller 12 is performed.

When the next upper screen is scanned by the CRT controller 12, the address of the memory 17 goes back by one line from the line address at the time of scanning of the previous frame, and the writing is performed from the line address 241. That is, the data of the line number L ₁ according to the display data PDA ₁ is provided for display as the display data PDA and the line address 24
1 area. Next, after the data of the line number L ₂₄₁ already stored in the area of the line address 1 of the memory 17 is read and provided for display as the display data PDA, the data of the line number L ₂ by the display data PDA 1 is , Are provided for display as display data PDA and are stored in the area of the same line address 1 in the memory 17. Similarly, the line address 239 of the memory 17
After the data of the line number L ₄₇₉ of the region it has already been stored is subjected to the display as a read and display data PDA, the data line number L ₂₄₀ by the display data PDA1 is subjected to the display as display data PDA With the same line address 239 in the memory 17. Next, the data of the line number _L480 already stored in the area of the line address 240 of the memory 17 is read and provided for display as the display data PDA.

As described above, in the present invention, a memory having a capacity of at least 1/2 frame + 1 line is used as the memory 17, and the write address to the memory 17 is shifted by one line every time the frame changes. Therefore, even if one line is written at the beginning of a frame,
7 is not erased.

Thereafter, read / write to the memory 17 is repeated in the same manner. By doing so, the memory 17 of 241 lines (2/1 frame + 1 line) using the general-purpose memory can be efficiently used as a 1/2 frame buffer.

As described above, according to the display controller of this embodiment, the CRT controller 12
Since the synchronization with the panel timing is achieved by forcibly applying a wait from the outside, sufficient compatibility can be ensured even with a conventional CRT application program.

The memory 17 using a general-purpose memory is efficiently used as a 1/2 frame buffer to store display data sequentially in the memory 17 and display data PDA output from the panel data conversion circuit 15.
1 and the display data PDA2 output from the CRT controller 12 are alternately selected, so that the display control of the two-screen single-drive flat panel display 3 can be performed without any trouble.

[0040]

As described above, according to the present invention,
Since the CRT controller is forcibly weighted by the panel timing controller, synchronization with the panel timing is performed.
It is possible to provide a panel display control device capable of ensuring complete compatibility without having to change the timing setting value and the like inside the T controller.

Further, according to the panel display control device of the present invention, a buffer memory using a general-purpose memory is provided, and display data supplied from a CRT controller is provided.
Since the display data and the display data read from the memory are alternately selected, data can be supplied in an order that matches the two-screen split type panel display.

According to the present invention, the required buffer capacity is at least フ レ ー ム frame + 1 line, so that the hardware amount does not increase significantly.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display controller according to an embodiment of the present invention.

FIG. 2 is a timing chart showing CRT display timing by the controller of FIG. 1;

FIG. 3 is a timing chart showing panel display timing by the controller of FIG. 1;

FIG. 4 is a schematic diagram showing a flow of display data supplied to a panel display when a CRT controller scans an upper screen.

FIG. 5 is a schematic diagram showing a flow of display data supplied to the panel display when the CRT controller scans the upper screen.

FIG. 6: Memory read / read by memory controller
It is a figure which shows a light typically.

FIG. 7 is a timing chart for explaining the operation of FIG. 6;

FIG. 8 is a block diagram of a two-screen single drive type panel display.

FIG. 9 is a timing chart showing display timing of the panel display of FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Display controller, 2 ... VRAM, 3 ... Flat panel display, 11 ... Clock select circuit, 12 ... CRT controller, 3 ... Panel timing controller, 14 ... External synchronization circuit, 15 ... Panel data conversion circuit, 16 ... Memory controller , 17 ...
Memory, 18 ... Data control circuit.

Claims (1)

(57) [Claims] 1. A two-screen split single driver for display control.
And clock supply means for supplying a basic clock to be a basis of the display timing of the drive type panel display, timing is set in and a predetermined clock signal
A CRT controller operable based on the set value and capable of outputting a display timing signal and display data of the panel display to the outside based on the basic clock and an externally applied wait signal; A panel data conversion circuit for converting output display data into panel display data; a memory for storing at least フ レ ー ム frame + 1 line of panel display data output from the panel data conversion circuit; Clock and from the CRT controller
Based on the input of the display timing signal, the CRT
The display timing signal and display data in the controller
The output operation of the data may be one line of the display data.
The wait signal, which is interrupted only for a certain period,
And it outputs the serial CRT controller, a panel timing controller for outputting a panel vertical switching signal synchronized with the wait signal, and controls the read / write to the memory based on said panel upper and lower switching signal, the panel data conversion One line of display data for the panel is output from the circuit.
During this period, the display data for one line is written into the memory, and subsequently the CRT controller
The period during which the operation is interrupted by the wait signal
Then, the display data written immediately before is 1/2
The display data of the line separated from the frame is read from the memory.
Look out, and the memory controller to and shifting the write address for each frame in the write scan and the reverse direction line by line, from said memory and display data output from the panel data converting circuit according to said panel upper and lower switching signal A data control circuit for alternately selecting display data to be output for each line and outputting the selected display data to the panel display.